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authorJohn Rigby <john.rigby@linaro.org>2011-08-11 14:34:22 -0600
committerJohn Rigby <john.rigby@linaro.org>2011-09-22 20:27:49 -0600
commit234e16fba6feaf66eacd6371b9d050035eff5736 (patch)
tree7dc451252f0a476ba6b936f52619a003d214e88c
parentbc196029f53c2d82eb9a12eb8b66e696b6284941 (diff)
downloadu-boot-linaro-stable-234e16fba6feaf66eacd6371b9d050035eff5736.tar.gz
OMAP4 Panda: clock config for USB
Turn on some clocks that were formerly configured by x-loader USB in kernel does not work without this. Perhaps the PHY gets in a strange state. Signed-off-by: John Rigby <john.rigby@linaro.org>
-rw-r--r--arch/arm/cpu/armv7/omap4/clocks.c13
-rw-r--r--board/ti/panda/panda.c19
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 4f0e0cd88..008bfd8b5 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -248,6 +248,15 @@ static inline void wait_for_lock(u32 *const base)
}
}
+static void force_on(u32 *const reg, u32 val)
+{
+ u32 temp;
+
+ temp = readl(reg);
+ temp |= val;
+ writel(temp, reg);
+}
+
static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
u8 lock)
{
@@ -441,6 +450,10 @@ static void setup_non_essential_dplls(void)
/* Now setup the dpll with the regular function */
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
+ /* Force on these two clocks */
+ force_on(&prcm->cm_div_m2_dpll_usb, 1 << 8);
+ force_on(&prcm->cm_clkdcoldo_dpll_usb, 1 << 8);
+
#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 9afed807b..e60a2e267 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -67,6 +67,25 @@ int misc_init_r(void)
void set_muxconf_regs_non_essential(void)
{
+ /*
+ * Enable USB phy ref clock before reconfiguring pins because
+ * the phy seems to get in a bad state otherwise.
+ */
+#define OMAP44XX_SCRM_BASE 0x4a30a000
+#define OMAP44XX_SCRM_ALTCLKSRC (OMAP44XX_SCRM_BASE + 0x110)
+#define OMAP44XX_SCRM_AUXCLK1 (OMAP44XX_SCRM_BASE + 0x314)
+#define OMAP44XX_SCRM_AUXCLK3 (OMAP44XX_SCRM_BASE + 0x31c)
+ /* enable software ioreq */
+ sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
+ /* set for sys_clk (38.4MHz) */
+ sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
+ /* set divisor to 2 */
+ sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
+ /* set the clock source to active */
+ sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
+ /* enable clocks */
+ sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
+
do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));