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authorStefano Babic <sbabic@denx.de>2012-04-09 13:33:04 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-04-16 14:53:59 +0200
commitfbf4a074e0b7eb4864836084eff2a747617be0b4 (patch)
tree27c8c5f6a2135a21233d59cf6ffcc76bcc5e87da
parent38fcc71cc58b1c9a224b707b03eb6574cb2dc027 (diff)
downloadu-boot-linaro-next-fbf4a074e0b7eb4864836084eff2a747617be0b4.tar.gz
ARM1136: MX35: Make asm routines volatile in cache ops
As well as pushed for ARM926EJS, we certainly don't want the compiler to reorganise the code for dcache flushing Fix checkpatch warnings as well. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marex@denx.de> CC: Albert Aribaud <albert.u.boot@aribaud.net>
-rw-r--r--arch/arm/cpu/arm1136/cpu.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index f2e30b519..f72bab669 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -70,10 +70,12 @@ int cleanup_before_linux (void)
static void cache_flush(void)
{
unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
- asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+ /* clean entire data cache */
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+ /* invalidate both caches and flush btb */
+ asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+ /* mem barrier to sync things */
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
#ifndef CONFIG_SYS_DCACHE_OFF
@@ -84,13 +86,13 @@ static void cache_flush(void)
void invalidate_dcache_all(void)
{
- asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
}
void flush_dcache_all(void)
{
- asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
- asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
static inline int bad_cache_range(unsigned long start, unsigned long stop)
@@ -116,7 +118,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+ asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
@@ -127,11 +129,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+ asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
- asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
void flush_cache(unsigned long start, unsigned long size)