From 2fbea6cef42d121352f919d9b0d91f697ec4c1c4 Mon Sep 17 00:00:00 2001
From: Alexandre Rames <alexandre.rames@linaro.org>
Date: Tue, 7 Jun 2016 09:21:11 +0100
Subject: Cherry-pick: Fix a bug in the MacroAssembler CSEL helpers.

This also introduces regression tests.

This is a cherry-pick of dd47fed5e4cd380a8a5a3dd4ab80d8531a5e7c93.

Change-Id: I1ea770b10559425379bb42184120136b1147dd86
---
 src/a64/macro-assembler-a64.cc |  7 +++----
 test/test-assembler-a64.cc     | 36 +++++++++++++++++++++++++++++++++++-
 test/test-disasm-a64.cc        | 12 ++++++------
 3 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/src/a64/macro-assembler-a64.cc b/src/a64/macro-assembler-a64.cc
index 5681d4ad..d26d2a20 100644
--- a/src/a64/macro-assembler-a64.cc
+++ b/src/a64/macro-assembler-a64.cc
@@ -1283,12 +1283,11 @@ bool MacroAssembler::CselSubHelperTwoOrderedImmediates(MacroAssembler* masm,
                                                        Condition cond) {
   bool emit_code = (masm != NULL);
 
-  if ((left == 0) && (right == 1)) {
+  if ((left == 1) && (right == 0)) {
     if (emit_code) masm->cset(rd, cond);
     return true;
-  } else if ((left == 0) && (right == -1)) {
-    Register zr = AppropriateZeroRegFor(rd);
-    if (emit_code) masm->csinv(rd, zr, zr, InvertCondition(cond));
+  } else if ((left == -1) && (right == 0)) {
+    if (emit_code) masm->csetm(rd, cond);
     return true;
   }
   return false;
diff --git a/test/test-assembler-a64.cc b/test/test-assembler-a64.cc
index aaba4f94..4603dcd5 100644
--- a/test/test-assembler-a64.cc
+++ b/test/test-assembler-a64.cc
@@ -8619,7 +8619,7 @@ TEST(ccmp_shift_extend) {
 }
 
 
-TEST(csel) {
+TEST(csel_reg) {
   SETUP();
   ALLOW_ASM();
 
@@ -8683,6 +8683,40 @@ TEST(csel) {
 TEST(csel_imm) {
   SETUP();
 
+  int values[] = {-123, -2, -1, 0, 1, 2, 123};
+  int n_values = sizeof(values) / sizeof(values[0]);
+
+  for (int i = 0; i < n_values; i++) {
+    for (int j = 0; j < n_values; j++) {
+      int left = values[i];
+      int right = values[j];
+
+      START();
+      __ Mov(x10, 0);
+      __ Cmp(x10, 0);
+      __ Csel(w0, left, right, eq);
+      __ Csel(w1, left, right, ne);
+      __ Csel(x2, left, right, eq);
+      __ Csel(x3, left, right, ne);
+
+      END();
+
+      RUN();
+
+      ASSERT_EQUAL_32(left, w0);
+      ASSERT_EQUAL_32(right, w1);
+      ASSERT_EQUAL_64(left, x2);
+      ASSERT_EQUAL_64(right, x3);
+    }
+  }
+
+  TEARDOWN();
+}
+
+
+TEST(csel_mixed) {
+  SETUP();
+
   START();
   __ Mov(x18, 0);
   __ Mov(x19, 0x80000000);
diff --git a/test/test-disasm-a64.cc b/test/test-disasm-a64.cc
index 215ece83..9b8b368c 100644
--- a/test/test-disasm-a64.cc
+++ b/test/test-disasm-a64.cc
@@ -2276,25 +2276,25 @@ TEST(cond_select_macro) {
                                               &synthesises_right);
   VIXL_CHECK(!synthesises_left && !synthesises_right);
 
-  COMPARE_MACRO(Csel(w13,     0,     1, eq), "cset w13, eq");
+  COMPARE_MACRO(Csel(w13,     0,     1, eq), "cset w13, ne");
   MacroAssembler::GetCselSynthesisInformation(w13, 0, 1,
                                               &synthesises_left,
                                               &synthesises_right);
   VIXL_CHECK(!synthesises_left && !synthesises_right);
 
-  COMPARE_MACRO(Csel(x14,     1,     0, eq), "cset x14, ne");
+  COMPARE_MACRO(Csel(x14,     1,     0, eq), "cset x14, eq");
   MacroAssembler::GetCselSynthesisInformation(x14, 1, 0,
                                               &synthesises_left,
                                               &synthesises_right);
   VIXL_CHECK(!synthesises_left && !synthesises_right);
 
-  COMPARE_MACRO(Csel(w15,     0,    -1, eq), "csetm w15, eq");
+  COMPARE_MACRO(Csel(w15,     0,    -1, eq), "csetm w15, ne");
   MacroAssembler::GetCselSynthesisInformation(w15, 0, -1,
                                               &synthesises_left,
                                               &synthesises_right);
   VIXL_CHECK(!synthesises_left && !synthesises_right);
 
-  COMPARE_MACRO(Csel(x18,    -1,     0, eq), "csetm x18, ne");
+  COMPARE_MACRO(Csel(x18,    -1,     0, eq), "csetm x18, eq");
   MacroAssembler::GetCselSynthesisInformation(x18, -1, 0,
                                               &synthesises_left,
                                               &synthesises_right);
@@ -2360,7 +2360,7 @@ TEST(cond_select_macro) {
 
   // Test with `Operand` inputs.
   COMPARE_MACRO(Csel(x0, x1, Operand(x2, LSL, 3), eq), "lsl x16, x2, #3\n"
-                                                        "csel x0, x1, x16, eq");
+                                                       "csel x0, x1, x16, eq");
   MacroAssembler::GetCselSynthesisInformation(x0, x1,  Operand(x2, LSL, 3),
                                               &synthesises_left,
                                               &synthesises_right);
@@ -2431,7 +2431,7 @@ TEST(cond_select_macro) {
                                               &synthesises_right);
   VIXL_CHECK(!synthesises_left && !synthesises_right);
 
-  COMPARE_MACRO(Csel(w25, wzr, 1, eq), "cset w25, eq");
+  COMPARE_MACRO(Csel(w25, wzr, 1, eq), "cset w25, ne");
   MacroAssembler::GetCselSynthesisInformation(w25, wzr, 1,
                                               &synthesises_left,
                                               &synthesises_right);
-- 
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