Add support for random number generation.

Arm8.5 introduces RNDR and RNDRRS which both return a 64-bit random number.

Change-Id: I0d942c742232efae5f605233410935512c79b576

3 files changed, 42 insertions, 1 deletions

diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 5def1293..20f4057f 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -15026,6 +15026,45 @@ TEST(system_mrs) {
   TEARDOWN();
 }
 
+TEST(system_rng) {
+  SETUP_WITH_FEATURES(CPUFeatures::kRNG);
+
+  START();
+  // Random number.
+  __ Mrs(x1, RNDR);
+  // Assume that each generation is successful now.
+  // TODO: Return failure occasionally.
+  __ Mrs(x2, NZCV);
+  __ Mrs(x3, RNDR);
+  __ Mrs(x4, NZCV);
+
+  // Reseeded random number.
+  __ Mrs(x5, RNDRRS);
+  // Assume that each generation is successful now.
+  // TODO: Return failure occasionally.
+  __ Mrs(x6, NZCV);
+  __ Mrs(x7, RNDRRS);
+  __ Mrs(x8, NZCV);
+  END();
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  RUN();
+  // Random number generation series.
+  // Check random numbers have been generated and aren't equal when reseed has
+  // happened.
+  // NOTE: With a different architectural implementation, there may be a
+  // collison.
+  // TODO: Return failure occasionally. Set ZFlag and return UNKNOWN value.
+  ASSERT_NOT_EQUAL_64(x1, x3);
+  ASSERT_EQUAL_64(NoFlag, x2);
+  ASSERT_EQUAL_64(NoFlag, x4);
+  ASSERT_NOT_EQUAL_64(x5, x7);
+  ASSERT_EQUAL_64(NoFlag, x6);
+  ASSERT_EQUAL_64(NoFlag, x8);
+#endif
+
+  TEARDOWN();
+}
 
 TEST(cfinv) {
   SETUP_WITH_FEATURES(CPUFeatures::kFlagM);
diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc
index cdddf860..2dfedfc6 100644
--- a/test/aarch64/test-disasm-aarch64.cc
+++ b/test/aarch64/test-disasm-aarch64.cc
@@ -3232,6 +3232,8 @@ TEST(system_mrs) {
   COMPARE(mrs(x0, NZCV), "mrs x0, nzcv");
   COMPARE(mrs(x30, NZCV), "mrs x30, nzcv");
   COMPARE(mrs(x15, FPCR), "mrs x15, fpcr");
+  COMPARE(mrs(x20, RNDR), "mrs x20, rndr");
+  COMPARE(mrs(x5, RNDRRS), "mrs x5, rndrrs");
 
   // Test mrs that use system registers we haven't named.
   COMPARE(dci(MRS | (0x5555 << 5)), "mrs x0, S3_2_c10_c10_5");
diff --git a/test/test-api.cc b/test/test-api.cc
index 219d4dfb..9b3d55dd 100644
--- a/test/test-api.cc
+++ b/test/test-api.cc
@@ -393,7 +393,7 @@ TEST(CPUFeatures_format) {
       // Armv8.4
       "RCpc (imm), FlagM, USCAT, FHM, DIT, "
       // Armv8.5
-      "BTI, AXFlag",
+      "BTI, AXFlag, RNG",
       CPUFeatures::All());
 }