Simplify the *CacheOp enums.

This adds a CacheOpEncoder class to encode InstructionCacheOp and DataCacheOp
values, in the same way as SystemRegister.

I've also replaced the hexadecimal field values with decimals, since this is
easier to read and also matches the table in the Arm ARM.

Change-Id: I05bb334ebce77f2b3847fb70afdfc30aaf798e30

1 files changed, 15 insertions, 20 deletions

diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h
index 02422ef2..b0a5975f 100644
--- a/src/aarch64/constants-aarch64.h
+++ b/src/aarch64/constants-aarch64.h
@@ -364,30 +364,25 @@ enum SystemRegister {
   FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value
 };
 
+template<int op1, int crn, int crm, int op2>
+class CacheOpEncoder {
+ public:
+  static const uint32_t value =
+      ((op1 << SysOp1_offset) |
+       (crn << CRn_offset) |
+       (crm << CRm_offset) |
+       (op2 << SysOp2_offset)) >> SysOp_offset;
+};
+
 enum InstructionCacheOp {
-  IVAU = ((0x3 << SysOp1_offset) |
-          (0x7 << CRn_offset) |
-          (0x5 << CRm_offset) |
-          (0x1 << SysOp2_offset)) >> SysOp_offset
+  IVAU = CacheOpEncoder<3, 7, 5, 1>::value
 };
 
 enum DataCacheOp {
-  CVAC  = ((0x3 << SysOp1_offset) |
-           (0x7 << CRn_offset) |
-           (0xa << CRm_offset) |
-           (0x1 << SysOp2_offset)) >> SysOp_offset,
-  CVAU  = ((0x3 << SysOp1_offset) |
-           (0x7 << CRn_offset) |
-           (0xb << CRm_offset) |
-           (0x1 << SysOp2_offset)) >> SysOp_offset,
-  CIVAC = ((0x3 << SysOp1_offset) |
-           (0x7 << CRn_offset) |
-           (0xe << CRm_offset) |
-           (0x1 << SysOp2_offset)) >> SysOp_offset,
-  ZVA   = ((0x3 << SysOp1_offset) |
-           (0x7 << CRn_offset) |
-           (0x4 << CRm_offset) |
-           (0x1 << SysOp2_offset)) >> SysOp_offset
+  CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
+  CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
+  CIVAC = CacheOpEncoder<3, 7, 14, 1>::value,
+  ZVA = CacheOpEncoder<3, 7, 4, 1>::value
 };
 
 // Instruction enumerations.