Update the CPUFeatures tests.

Also fix issues in the CPUFeaturesAuditor and Assembler.

Change-Id: I7404e63107d46812eb098d2e7166225136080687

3 files changed, 24 insertions, 6 deletions

diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc
index 74a89fef..d416441c 100644
--- a/src/aarch64/assembler-aarch64.cc
+++ b/src/aarch64/assembler-aarch64.cc
@@ -1523,7 +1523,7 @@ void Assembler::stlrb(const Register& rt, const MemOperand& dst) {
 }
 
 void Assembler::stlurb(const Register& rt, const MemOperand& dst) {
-  VIXL_ASSERT(CPUHas(CPUFeatures::kRCpcImm));
+  VIXL_ASSERT(CPUHas(CPUFeatures::kRCpc, CPUFeatures::kRCpcImm));
   VIXL_ASSERT(dst.IsImmediateOffset() && IsImmLSUnscaled(dst.GetOffset()));
 
   Instr base = RnSP(dst.GetBaseRegister());
@@ -1538,7 +1538,7 @@ void Assembler::stlrh(const Register& rt, const MemOperand& dst) {
 }
 
 void Assembler::stlurh(const Register& rt, const MemOperand& dst) {
-  VIXL_ASSERT(CPUHas(CPUFeatures::kRCpcImm));
+  VIXL_ASSERT(CPUHas(CPUFeatures::kRCpc, CPUFeatures::kRCpcImm));
   VIXL_ASSERT(dst.IsImmediateOffset() && IsImmLSUnscaled(dst.GetOffset()));
 
   Instr base = RnSP(dst.GetBaseRegister());
@@ -1554,7 +1554,7 @@ void Assembler::stlr(const Register& rt, const MemOperand& dst) {
 }
 
 void Assembler::stlur(const Register& rt, const MemOperand& dst) {
-  VIXL_ASSERT(CPUHas(CPUFeatures::kRCpcImm));
+  VIXL_ASSERT(CPUHas(CPUFeatures::kRCpc, CPUFeatures::kRCpcImm));
   VIXL_ASSERT(dst.IsImmediateOffset() && IsImmLSUnscaled(dst.GetOffset()));
 
   Instr base = RnSP(dst.GetBaseRegister());
@@ -2620,12 +2620,14 @@ void Assembler::mvn(const Register& rd, const Operand& operand) {
 
 void Assembler::mrs(const Register& xt, SystemRegister sysreg) {
   VIXL_ASSERT(xt.Is64Bits());
+  VIXL_ASSERT(CPUHas(sysreg));
   Emit(MRS | ImmSystemRegister(sysreg) | Rt(xt));
 }
 
 
 void Assembler::msr(SystemRegister sysreg, const Register& xt) {
   VIXL_ASSERT(xt.Is64Bits());
+  VIXL_ASSERT(CPUHas(sysreg));
   Emit(MSR | Rt(xt) | ImmSystemRegister(sysreg));
 }
 
@@ -6147,6 +6149,19 @@ bool Assembler::CPUHas(const CPURegister& rt, const CPURegister& rt2) const {
 }
 
 
+bool Assembler::CPUHas(SystemRegister sysreg) const {
+  switch (sysreg) {
+    case RNDR:
+    case RNDRRS:
+      return CPUHas(CPUFeatures::kRNG);
+    case FPCR:
+    case NZCV:
+      break;
+  }
+  return true;
+}
+
+
 bool AreAliased(const CPURegister& reg1,
                 const CPURegister& reg2,
                 const CPURegister& reg3,
diff --git a/src/aarch64/assembler-aarch64.h b/src/aarch64/assembler-aarch64.h
index 250a0bc3..7b529344 100644
--- a/src/aarch64/assembler-aarch64.h
+++ b/src/aarch64/assembler-aarch64.h
@@ -4349,6 +4349,8 @@ class Assembler : public vixl::internal::AssemblerBase {
   bool CPUHas(const CPURegister& rt) const;
   bool CPUHas(const CPURegister& rt, const CPURegister& rt2) const;
 
+  bool CPUHas(SystemRegister sysreg) const;
+
  private:
   static uint32_t FP16ToImm8(Float16 imm);
   static uint32_t FP32ToImm8(float imm);
diff --git a/src/aarch64/cpu-features-auditor-aarch64.cc b/src/aarch64/cpu-features-auditor-aarch64.cc
index 3207e73b..353e17aa 100644
--- a/src/aarch64/cpu-features-auditor-aarch64.cc
+++ b/src/aarch64/cpu-features-auditor-aarch64.cc
@@ -286,13 +286,14 @@ void CPUFeaturesAuditor::VisitLoadStoreRCpcUnscaledOffset(
     case LDAPUR_w:
     case LDAPURSW:
     case LDAPUR_x:
-      scope.Record(CPUFeatures::kRCpc);
-      VIXL_FALLTHROUGH();
+
+    // These stores don't actually have RCpc semantics but they're included with
+    // the RCpc extensions.
     case STLURB:
     case STLURH:
     case STLUR_w:
     case STLUR_x:
-      scope.Record(CPUFeatures::kRCpcImm);
+      scope.Record(CPUFeatures::kRCpc, CPUFeatures::kRCpcImm);
       return;
   }
 }