diff options
author | TatWai Chong <tatwai.chong@arm.com> | 2018-12-27 16:01:02 -0800 |
---|---|---|
committer | TatWai Chong <tatwai.chong@arm.com> | 2019-01-29 23:33:48 +0000 |
commit | 04edf680e65e6aa55e64f56badf6a51a343fc890 (patch) | |
tree | 64e208dea7992dbc1395c354427704ced4ad285d /src | |
parent | 7e3a5c85976dfd832ff2e6ebf428ec791b8804dc (diff) |
Add support for random number generation.
Arm8.5 introduces RNDR and RNDRRS which both return a 64-bit random number.
Change-Id: I0d942c742232efae5f605233410935512c79b576
Diffstat (limited to 'src')
-rw-r--r-- | src/aarch64/constants-aarch64.h | 4 | ||||
-rw-r--r-- | src/aarch64/cpu-features-auditor-aarch64.cc | 9 | ||||
-rw-r--r-- | src/aarch64/disasm-aarch64.cc | 6 | ||||
-rw-r--r-- | src/aarch64/simulator-aarch64.cc | 18 | ||||
-rw-r--r-- | src/aarch64/simulator-aarch64.h | 3 | ||||
-rw-r--r-- | src/cpu-features.h | 4 |
6 files changed, 42 insertions, 2 deletions
diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h index f1361c36..5c3bd491 100644 --- a/src/aarch64/constants-aarch64.h +++ b/src/aarch64/constants-aarch64.h @@ -400,7 +400,9 @@ class SystemRegisterEncoder { // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). enum SystemRegister { NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, - FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value + FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, + RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number. + RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value // Reseeded random number. }; template<int op1, int crn, int crm, int op2> diff --git a/src/aarch64/cpu-features-auditor-aarch64.cc b/src/aarch64/cpu-features-auditor-aarch64.cc index 3fa4e54c..0a55a780 100644 --- a/src/aarch64/cpu-features-auditor-aarch64.cc +++ b/src/aarch64/cpu-features-auditor-aarch64.cc @@ -1118,6 +1118,15 @@ void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) { scope.Record(CPUFeatures::kAXFlag); break; } + } else if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) { + if (instr->Mask(SystemSysRegMask) == MRS) { + switch (instr->GetImmSystemRegister()) { + case RNDR: + case RNDRRS: + scope.Record(CPUFeatures::kRNG); + break; + } + } } } diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc index 43654f38..c3527eec 100644 --- a/src/aarch64/disasm-aarch64.cc +++ b/src/aarch64/disasm-aarch64.cc @@ -5585,6 +5585,12 @@ int Disassembler::SubstituteImmediateField(const Instruction *instr, case FPCR: AppendToOutput("fpcr"); break; + case RNDR: + AppendToOutput("rndr"); + break; + case RNDRRS: + AppendToOutput("rndrrs"); + break; default: AppendToOutput("S%d_%d_c%d_c%d_%d", instr->GetSysOp0(), diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index e7f9e9ce..dcf2ef86 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -113,6 +113,11 @@ Simulator::Simulator(Decoder* decoder, FILE* stream) print_exclusive_access_warning_ = true; guard_pages_ = false; + + // Initialize the common state of RNDR and RNDRRS. + uint16_t seed[3] = {11, 22, 33}; + VIXL_STATIC_ASSERT(sizeof(seed) == sizeof(rndr_state_)); + memcpy(rndr_state_, seed, sizeof(rndr_state_)); } @@ -3908,6 +3913,19 @@ void Simulator::VisitSystem(const Instruction* instr) { case FPCR: WriteXRegister(instr->GetRt(), ReadFpcr().GetRawValue()); break; + case RNDR: + case RNDRRS: { + uint64_t high = jrand48(rndr_state_); + uint64_t low = jrand48(rndr_state_); + uint64_t rand_num = (high << 32) | (low & 0xffffffff); + WriteXRegister(instr->GetRt(), rand_num); + // Simulate successful random number generation. + // TODO: Return failure occasionally as a random number cannot be + // returned in a period of time. + ReadNzcv().SetRawValue(NoFlag); + LogSystemRegister(NZCV); + break; + } default: VIXL_UNIMPLEMENTED(); } diff --git a/src/aarch64/simulator-aarch64.h b/src/aarch64/simulator-aarch64.h index 075a6061..13803e4f 100644 --- a/src/aarch64/simulator-aarch64.h +++ b/src/aarch64/simulator-aarch64.h @@ -3354,6 +3354,9 @@ class Simulator : public DecoderVisitor { CPUFeaturesAuditor cpu_features_auditor_; std::vector<CPUFeatures> saved_cpu_features_; + + // The simulated state of RNDR and RNDRRS for generating a random number. + uint16_t rndr_state_[3]; }; #if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L diff --git a/src/cpu-features.h b/src/cpu-features.h index 25c49d7e..cd82d3c5 100644 --- a/src/cpu-features.h +++ b/src/cpu-features.h @@ -100,7 +100,9 @@ namespace vixl { /* Branch target identification. */ \ V(kBTI, "BTI", NULL) \ /* Flag manipulation instructions: {AX,XA}FLAG */ \ - V(kAXFlag, "AXFlag", NULL) + V(kAXFlag, "AXFlag", NULL) \ + /* Random number generation extension, */ \ + V(kRNG, "RNG", NULL) // clang-format on |