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authorTatWai Chong <tatwai.chong@arm.com>2019-01-14 15:50:40 -0800
committerTatWai Chong <tatwai.chong@arm.com>2019-01-30 18:49:14 +0000
commit4a6b62c4e28f60f2c551ca1b780f9c7773ac5069 (patch)
tree4903fdff37145b87f36b55bf826098a6ad255421
parentb17136850494798da9814c434a4a5f136aa434a9 (diff)
Make Fmov(Register, VRegister, index) accept index = 0.
fmov only support index = 1 in "fmov <Xd>, <Vn>.D[index]" and "fmov <Vd>.D[index], <Xn>" encoding. In case of index = 0, MacroAssembler should transfer fmov 64-bit value between vector element and general-purpose register to "mov <Xd> <Vn>.D[0]" and "mov <Vd>D[0], <Xn>" respectively. Change-Id: I5309f0376584e2806f2ee6e8871743d1b31e226f
-rw-r--r--src/aarch64/macro-assembler-aarch64.h12
-rw-r--r--test/aarch64/test-assembler-aarch64.cc5
-rw-r--r--test/aarch64/test-disasm-aarch64.cc5
3 files changed, 20 insertions, 2 deletions
diff --git a/src/aarch64/macro-assembler-aarch64.h b/src/aarch64/macro-assembler-aarch64.h
index bdd85494..fbab0778 100644
--- a/src/aarch64/macro-assembler-aarch64.h
+++ b/src/aarch64/macro-assembler-aarch64.h
@@ -1518,12 +1518,20 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
void Fmov(const VRegister& vd, int index, const Register& rn) {
VIXL_ASSERT(allow_macro_instructions_);
SingleEmissionCheckScope guard(this);
- fmov(vd, index, rn);
+ if (vd.Is1D() && (index == 0)) {
+ mov(vd, index, rn);
+ } else {
+ fmov(vd, index, rn);
+ }
}
void Fmov(const Register& rd, const VRegister& vn, int index) {
VIXL_ASSERT(allow_macro_instructions_);
SingleEmissionCheckScope guard(this);
- fmov(rd, vn, index);
+ if (vn.Is1D() && (index == 0)) {
+ mov(rd, vn, index);
+ } else {
+ fmov(rd, vn, index);
+ }
}
// Provide explicit double and float interfaces for FP immediate moves, rather
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 20f4057f..5354d17b 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -10782,6 +10782,9 @@ TEST(fmov_reg) {
__ Fmov(d0, 0.0);
__ Fmov(v0.D(), 1, x1);
__ Fmov(x2, v0.D(), 1);
+ __ Fmov(v3.D(), 1, x4);
+ __ Fmov(v3.D(), 0, x1);
+ __ Fmov(x5, v1.D(), 0);
END();
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
@@ -10801,6 +10804,8 @@ TEST(fmov_reg) {
ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s6);
ASSERT_EQUAL_128(DoubleToRawbits(-13.0), 0x0000000000000000, q0);
ASSERT_EQUAL_64(DoubleToRawbits(-13.0), x2);
+ ASSERT_EQUAL_128(0x0000000000006400, DoubleToRawbits(-13.0), q3);
+ ASSERT_EQUAL_64(DoubleToRawbits(-13.0), x5);
#endif
TEARDOWN();
diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc
index 2dfedfc6..61031829 100644
--- a/test/aarch64/test-disasm-aarch64.cc
+++ b/test/aarch64/test-disasm-aarch64.cc
@@ -6377,6 +6377,11 @@ TEST(neon_modimm) {
COMPARE_MACRO(Fmov(v0.V4H(), Float16(-5.0)), "fmov v0.4h, #0x94 (-5.0000)");
COMPARE_MACRO(Fmov(v31.V8H(), Float16(29.0)), "fmov v31.8h, #0x3d (29.0000)");
+ COMPARE_MACRO(Fmov(v5.D(), 1, x14), "fmov v5.D[1], x14");
+ COMPARE_MACRO(Fmov(x14, v5.D(), 1), "fmov x14, v5.D[1]");
+ COMPARE_MACRO(Fmov(v3.D(), 0, x21), "mov v3.d[0], x21");
+ COMPARE_MACRO(Fmov(x21, v3.D(), 0), "mov x21, v3.d[0]");
+
// An unallocated form of fmov.
COMPARE(dci(0x2f07ffff), "unallocated (Unallocated)");