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authorJacob Bramley <jacob.bramley@arm.com>2018-09-26 14:43:29 +0100
committerJacob Bramley <jacob.bramley@arm.com>2018-10-03 14:28:43 +0000
commit385eb9037db9b478295ca22e2cf2de2e74c32aec (patch)
tree28874e2a4c23f4765f2a94bf7ca7bf4ad3f21554
parent4482be77f92ce8c0ace34096440e134f61d60016 (diff)
Add support for DCPoP (CVAP).
Change-Id: If191c5380ace4bdcc5ea2e2a5af159ab75c24e92
-rw-r--r--src/aarch64/assembler-aarch64.cc2
-rw-r--r--src/aarch64/constants-aarch64.h1
-rw-r--r--src/aarch64/cpu-features-auditor-aarch64.cc13
-rw-r--r--src/aarch64/disasm-aarch64.cc4
-rw-r--r--src/aarch64/simulator-aarch64.cc1
-rw-r--r--test/aarch64/test-assembler-aarch64.cc26
-rw-r--r--test/aarch64/test-cpu-features-aarch64.cc4
-rw-r--r--test/aarch64/test-disasm-aarch64.cc3
8 files changed, 50 insertions, 4 deletions
diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc
index 937809b1..f2a07785 100644
--- a/src/aarch64/assembler-aarch64.cc
+++ b/src/aarch64/assembler-aarch64.cc
@@ -1765,7 +1765,7 @@ void Assembler::sys(int op, const Register& xt) {
void Assembler::dc(DataCacheOp op, const Register& rt) {
- VIXL_ASSERT((op == CVAC) || (op == CVAU) || (op == CIVAC) || (op == ZVA));
+ if (op == CVAP) VIXL_ASSERT(CPUHas(CPUFeatures::kDCPoP));
sys(op, rt);
}
diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h
index de659f07..29fe9d86 100644
--- a/src/aarch64/constants-aarch64.h
+++ b/src/aarch64/constants-aarch64.h
@@ -382,6 +382,7 @@ enum InstructionCacheOp {
enum DataCacheOp {
CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
+ CVAP = CacheOpEncoder<3, 7, 12, 1>::value,
CIVAC = CacheOpEncoder<3, 7, 14, 1>::value,
ZVA = CacheOpEncoder<3, 7, 4, 1>::value
};
diff --git a/src/aarch64/cpu-features-auditor-aarch64.cc b/src/aarch64/cpu-features-auditor-aarch64.cc
index 66f0d806..45512835 100644
--- a/src/aarch64/cpu-features-auditor-aarch64.cc
+++ b/src/aarch64/cpu-features-auditor-aarch64.cc
@@ -1009,6 +1009,19 @@ void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) {
// features are not implemented, so we record the corresponding features
// only if they are available.
if (available_.Has(required)) scope.Record(required);
+ } else if (instr->Mask(SystemSysMask) == SYS) {
+ switch (instr->GetSysOp()) {
+ // DC instruction variants.
+ case CVAP:
+ scope.Record(CPUFeatures::kDCPoP);
+ break;
+ case IVAU:
+ case CVAC:
+ case CVAU:
+ case CIVAC:
+ // No special CPU features.
+ break;
+ }
}
}
diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc
index 1c00443d..16f7b37f 100644
--- a/src/aarch64/disasm-aarch64.cc
+++ b/src/aarch64/disasm-aarch64.cc
@@ -2113,6 +2113,10 @@ void Disassembler::VisitSystem(const Instruction *instr) {
mnemonic = "dc";
form = "cvau, 'Xt";
break;
+ case CVAP:
+ mnemonic = "dc";
+ form = "cvap, 'Xt";
+ break;
case CIVAC:
mnemonic = "dc";
form = "civac, 'Xt";
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc
index 4763a54a..4a31a91f 100644
--- a/src/aarch64/simulator-aarch64.cc
+++ b/src/aarch64/simulator-aarch64.cc
@@ -3610,6 +3610,7 @@ void Simulator::SysOp_W(int op, int64_t val) {
case IVAU:
case CVAC:
case CVAU:
+ case CVAP:
case CIVAC: {
// Perform a dummy memory access to ensure that we have read access
// to the specified address.
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 9ccf7920..7bd54517 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -21791,14 +21791,36 @@ TEST(system_dc) {
START();
__ Mov(x20, msg_addr);
__ Dc(CVAC, x20);
- __ Mov(x21, x20);
+ __ Mov(x21, msg_addr);
__ Dc(CVAU, x21);
- __ Mov(x22, x21);
+ __ Mov(x22, msg_addr);
__ Dc(CIVAC, x22);
// TODO: Add tests to check ZVA.
END();
RUN();
+ ASSERT_EQUAL_64(msg_addr, x20);
+ ASSERT_EQUAL_64(msg_addr, x21);
+ ASSERT_EQUAL_64(msg_addr, x22);
+
+ TEARDOWN();
+}
+
+
+TEST(system_dcpop) {
+ SETUP_WITH_FEATURES(CPUFeatures::kDCPoP);
+ const char* msg = "DCPoP test!";
+ uintptr_t msg_addr = reinterpret_cast<uintptr_t>(msg);
+
+ START();
+ __ Mov(x20, msg_addr);
+ __ Dc(CVAP, x20);
+ END();
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+ RUN();
+ ASSERT_EQUAL_64(msg_addr, x20);
+#endif
TEARDOWN();
}
diff --git a/test/aarch64/test-cpu-features-aarch64.cc b/test/aarch64/test-cpu-features-aarch64.cc
index a4c35cda..8152f550 100644
--- a/test/aarch64/test-cpu-features-aarch64.cc
+++ b/test/aarch64/test-cpu-features-aarch64.cc
@@ -2774,6 +2774,10 @@ TEST_CRC32(crc32ch_0, crc32ch(w0, w1, w2))
TEST_CRC32(crc32cw_0, crc32cw(w0, w1, w2))
TEST_CRC32(crc32cx_0, crc32cx(w0, w1, x2))
+#define TEST_DCPOP(NAME, ASM) \
+ TEST_TEMPLATE(CPUFeatures(CPUFeatures::kDCPoP), DCPoP_##NAME, ASM)
+TEST_DCPOP(dc_0, dc(CVAP, x0))
+
#define TEST_PAUTH(NAME, ASM) \
TEST_TEMPLATE(CPUFeatures(CPUFeatures::kPAuth), PAuth_##NAME, ASM)
TEST_PAUTH(autda_0, autda(x0, x1))
diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc
index c42d07a0..38a3609b 100644
--- a/test/aarch64/test-disasm-aarch64.cc
+++ b/test/aarch64/test-disasm-aarch64.cc
@@ -3197,7 +3197,8 @@ TEST(system_dc) {
COMPARE(dc(CVAC, x2), "dc cvac, x2");
COMPARE(dc(CVAU, x3), "dc cvau, x3");
- COMPARE(dc(CIVAC, x4), "dc civac, x4");
+ COMPARE(dc(CVAP, x4), "dc cvap, x4");
+ COMPARE(dc(CIVAC, x5), "dc civac, x5");
COMPARE(dc(ZVA, x0), "dc zva, x0");
COMPARE(dc(ZVA, xzr), "dc zva, xzr");