Fix vld, vst instructions with post-index.

Change-Id: I23298cb948eb73e4a98c7b3e24fd0717214be8ee

6 files changed, 278 insertions, 14 deletions

diff --git a/src/aarch32/assembler-aarch32.cc b/src/aarch32/assembler-aarch32.cc
index 7e882909..138a3c29 100644
--- a/src/aarch32/assembler-aarch32.cc
+++ b/src/aarch32/assembler-aarch32.cc
@@ -18862,7 +18862,7 @@ void Assembler::vld3(Condition cond,
       if (encoded_dt.IsValid() && nreglist.IsTransferAllLanes() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al) || AllowStronglyDiscouraged()) {
           const DRegister& first = nreglist.GetFirstDRegister();
           uint32_t len_encoding = nreglist.IsSingleSpaced() ? 0x0 : 0x1;
@@ -18891,7 +18891,7 @@ void Assembler::vld3(Condition cond,
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al) || AllowStronglyDiscouraged()) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitT32_32(0xf9a0020dU | (encoded_dt.GetEncodingValue() << 10) |
@@ -18920,7 +18920,7 @@ void Assembler::vld3(Condition cond,
       if (encoded_dt.IsValid() && nreglist.IsTransferAllLanes() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al)) {
           const DRegister& first = nreglist.GetFirstDRegister();
           uint32_t len_encoding = nreglist.IsSingleSpaced() ? 0x0 : 0x1;
@@ -18947,7 +18947,7 @@ void Assembler::vld3(Condition cond,
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al)) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitA32(0xf4a0020dU | (encoded_dt.GetEncodingValue() << 10) |
@@ -26679,7 +26679,7 @@ void Assembler::vst3(Condition cond,
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al) || AllowStronglyDiscouraged()) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitT32_32(0xf980020dU | (encoded_dt.GetEncodingValue() << 10) |
@@ -26707,7 +26707,7 @@ void Assembler::vst3(Condition cond,
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al)) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitA32(0xf480020dU | (encoded_dt.GetEncodingValue() << 10) |
diff --git a/src/aarch32/disasm-aarch32.cc b/src/aarch32/disasm-aarch32.cc
index 8ea217c1..4767d261 100644
--- a/src/aarch32/disasm-aarch32.cc
+++ b/src/aarch32/disasm-aarch32.cc
@@ -15307,7 +15307,7 @@ void Disassembler::DecodeT32(uint32_t instr) {
                                                             DRegister(last),
                                                             spacing,
                                                             lane),
-                                           MemOperand(Register(rn), PreIndex));
+                                           MemOperand(Register(rn), PostIndex));
                                       break;
                                     }
                                     case 0x00000002: {
@@ -16240,7 +16240,7 @@ void Disassembler::DecodeT32(uint32_t instr) {
                                                                 spacing,
                                                                 transfer),
                                                MemOperand(Register(rn),
-                                                          PreIndex));
+                                                          PostIndex));
                                           break;
                                         }
                                         case 0x00000002: {
@@ -16387,7 +16387,7 @@ void Disassembler::DecodeT32(uint32_t instr) {
                                                             DRegister(last),
                                                             spacing,
                                                             lane),
-                                           MemOperand(Register(rn), PreIndex));
+                                           MemOperand(Register(rn), PostIndex));
                                       break;
                                     }
                                     case 0x00000002: {
@@ -52048,7 +52048,7 @@ void Disassembler::DecodeA32(uint32_t instr) {
                                                       DRegister(last),
                                                       spacing,
                                                       lane),
-                                     MemOperand(Register(rn), PreIndex));
+                                     MemOperand(Register(rn), PostIndex));
                                 break;
                               }
                               case 0x00000002: {
@@ -54735,7 +54735,7 @@ void Disassembler::DecodeA32(uint32_t instr) {
                                                           DRegister(last),
                                                           spacing,
                                                           transfer),
-                                         MemOperand(Register(rn), PreIndex));
+                                         MemOperand(Register(rn), PostIndex));
                                     break;
                                   }
                                   case 0x00000002: {
@@ -54876,7 +54876,7 @@ void Disassembler::DecodeA32(uint32_t instr) {
                                                       DRegister(last),
                                                       spacing,
                                                       lane),
-                                     MemOperand(Register(rn), PreIndex));
+                                     MemOperand(Register(rn), PostIndex));
                                 break;
                               }
                               case 0x00000002: {
diff --git a/src/aarch32/disasm-aarch32.h b/src/aarch32/disasm-aarch32.h
index 54f46960..b72b1567 100644
--- a/src/aarch32/disasm-aarch32.h
+++ b/src/aarch32/disasm-aarch32.h
@@ -463,6 +463,7 @@ class Disassembler {
       *this << "[" << operand.GetBaseRegister();
       if (operand.GetAddrMode() == PostIndex) {
         *this << "]";
+        if (operand.IsRegisterOnly()) return *this << "!";
       }
       if (operand.IsImmediate()) {
         if ((operand.GetOffsetImmediate() != 0) ||
diff --git a/src/aarch32/instructions-aarch32.h b/src/aarch32/instructions-aarch32.h
index cc9ecc39..f11f2b02 100644
--- a/src/aarch32/instructions-aarch32.h
+++ b/src/aarch32/instructions-aarch32.h
@@ -712,7 +712,7 @@ class NeonRegisterList {
         type_(kOneLane),
         lane_(lane),
         length_(1) {
-    VIXL_ASSERT((lane_ >= 0) && (lane_ < 4));
+    VIXL_ASSERT((lane_ >= 0) && (lane_ < 8));
   }
   NeonRegisterList(DRegister first,
                    DRegister last,
@@ -736,7 +736,7 @@ class NeonRegisterList {
         spacing_(spacing),
         type_(kOneLane),
         lane_(lane) {
-    VIXL_ASSERT((lane >= 0) && (lane < 4));
+    VIXL_ASSERT((lane >= 0) && (lane < 8));
     VIXL_ASSERT(first.GetCode() <= last.GetCode());
 
     int range = last.GetCode() - first.GetCode();
diff --git a/src/aarch32/operands-aarch32.cc b/src/aarch32/operands-aarch32.cc
index e0c960f8..a3068944 100644
--- a/src/aarch32/operands-aarch32.cc
+++ b/src/aarch32/operands-aarch32.cc
@@ -519,6 +519,7 @@ std::ostream& operator<<(std::ostream& os, const MemOperand& operand) {
   os << "[" << operand.GetBaseRegister();
   if (operand.GetAddrMode() == PostIndex) {
     os << "]";
+    if (operand.IsRegisterOnly()) return os << "!";
   }
   if (operand.IsImmediate()) {
     if ((operand.GetOffsetImmediate() != 0) || operand.GetSign().IsMinus() ||
diff --git a/test/aarch32/test-disasm-a32.cc b/test/aarch32/test-disasm-a32.cc
index 2bb22aab..db2902e6 100644
--- a/test/aarch32/test-disasm-a32.cc
+++ b/test/aarch32/test-disasm-a32.cc
@@ -1734,6 +1734,268 @@ TEST(assembler_hvc_negative) {
 #endif
 
 
+TEST(macro_assembler_vld) {
+  SETUP();
+
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld1.8 {d0}, [r1]\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld1.8 {d0}, [r1]!\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, kMultipleLanes),
+                    AlignedMemOperand(r8, kNoAlignment, r2, PostIndex)),
+               "vld1.8 {d0}, [r8], r2\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld1.8 {d0[]}, [r1]\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, kAllLanes),
+                    AlignedMemOperand(r9, kNoAlignment, PostIndex)),
+               "vld1.8 {d0[]}, [r9]!\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld1.8 {d0[]}, [r1], r2\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, 0),
+                    AlignedMemOperand(r10, kNoAlignment)),
+               "vld1.8 {d0[0]}, [r10]\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, 1),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld1.8 {d0[1]}, [r1]!\n");
+  COMPARE_BOTH(Vld1(Untyped8,
+                    NeonRegisterList(d0, 2),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld1.8 {d0[2]}, [r1], r2\n");
+
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld2.8 {d0,d1}, [r1]\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld2.8 {d0,d1}, [r1]!\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r8, PostIndex)),
+               "vld2.8 {d0,d1}, [r1], r8\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld2.8 {d0[],d1[]}, [r1]\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kAllLanes),
+                    AlignedMemOperand(r9, kNoAlignment, PostIndex)),
+               "vld2.8 {d0[],d1[]}, [r9]!\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld2.8 {d0[],d1[]}, [r1], r2\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, 0),
+                    AlignedMemOperand(r10, kNoAlignment)),
+               "vld2.8 {d0[0],d1[0]}, [r10]\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, 1),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld2.8 {d0[1],d1[1]}, [r1]!\n");
+  COMPARE_BOTH(Vld2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, 2),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld2.8 {d0[2],d1[2]}, [r1], r2\n");
+
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld3.8 {d0,d1,d2}, [r1]\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld3.8 {d0,d1,d2}, [r1]!\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r11, kNoAlignment, r2, PostIndex)),
+               "vld3.8 {d0,d1,d2}, [r11], r2\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kAllLanes),
+                    MemOperand(r1)),
+               "vld3.8 {d0[],d1[],d2[]}, [r1]\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kAllLanes),
+                    MemOperand(r11, PostIndex)),
+               "vld3.8 {d0[],d1[],d2[]}, [r11]!\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kAllLanes),
+                    MemOperand(r1, r2, PostIndex)),
+               "vld3.8 {d0[],d1[],d2[]}, [r1], r2\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, 0),
+                    MemOperand(sp)),
+               "vld3.8 {d0[0],d1[0],d2[0]}, [sp]\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, 1),
+                    MemOperand(r1, PostIndex)),
+               "vld3.8 {d0[1],d1[1],d2[1]}, [r1]!\n");
+  COMPARE_BOTH(Vld3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, 2),
+                    MemOperand(r1, r2, PostIndex)),
+               "vld3.8 {d0[2],d1[2],d2[2]}, [r1], r2\n");
+
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d6, kDouble, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld4.8 {d0,d2,d4,d6}, [r1]\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld4.8 {d0,d1,d2,d3}, [r1]!\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld4.8 {d0,d1,d2,d3}, [r1], r2\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld4.8 {d0[],d1[],d2[],d3[]}, [r1]\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d6, kDouble, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld4.8 {d0[],d2[],d4[],d6[]}, [r1]!\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, kAllLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld4.8 {d0[],d1[],d2[],d3[]}, [r1], r2\n");
+  COMPARE_BOTH(Vld4(Untyped16,
+                    NeonRegisterList(d0, d6, kDouble, 3),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vld4.16 {d0[3],d2[3],d4[3],d6[3]}, [r1]\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, 6),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vld4.8 {d0[6],d1[6],d2[6],d3[6]}, [r1]!\n");
+  COMPARE_BOTH(Vld4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, 7),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vld4.8 {d0[7],d1[7],d2[7],d3[7]}, [r1], r2\n");
+
+  CLEANUP();
+}
+
+
+TEST(macro_assembler_vst) {
+  SETUP();
+
+  COMPARE_BOTH(Vst1(Untyped8,
+                    NeonRegisterList(d0, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst1.8 {d0}, [r1]\n");
+  COMPARE_BOTH(Vst1(Untyped8,
+                    NeonRegisterList(d0, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst1.8 {d0}, [r1]!\n");
+  COMPARE_BOTH(Vst1(Untyped8,
+                    NeonRegisterList(d0, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vst1.8 {d0}, [r1], r2\n");
+  COMPARE_BOTH(Vst1(Untyped8,
+                    NeonRegisterList(d0, 0),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst1.8 {d0[0]}, [r1]\n");
+  COMPARE_BOTH(Vst1(Untyped8,
+                    NeonRegisterList(d0, 1),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst1.8 {d0[1]}, [r1]!\n");
+  COMPARE_BOTH(Vst1(Untyped8,
+                    NeonRegisterList(d0, 2),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vst1.8 {d0[2]}, [r1], r2\n");
+
+  COMPARE_BOTH(Vst2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst2.8 {d0,d1}, [r1]\n");
+  COMPARE_BOTH(Vst2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst2.8 {d0,d1}, [r1]!\n");
+  COMPARE_BOTH(Vst2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vst2.8 {d0,d1}, [r1], r2\n");
+  COMPARE_BOTH(Vst2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, 3),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst2.8 {d0[3],d1[3]}, [r1]\n");
+  COMPARE_BOTH(Vst2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, 4),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst2.8 {d0[4],d1[4]}, [r1]!\n");
+  COMPARE_BOTH(Vst2(Untyped8,
+                    NeonRegisterList(d0, d1, kSingle, 5),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vst2.8 {d0[5],d1[5]}, [r1], r2\n");
+
+  COMPARE_BOTH(Vst3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst3.8 {d0,d1,d2}, [r1]\n");
+  COMPARE_BOTH(Vst3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst3.8 {d0,d1,d2}, [r1]!\n");
+  COMPARE_BOTH(Vst3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vst3.8 {d0,d1,d2}, [r1], r2\n");
+  COMPARE_BOTH(Vst3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, 0),
+                    MemOperand(r1)),
+               "vst3.8 {d0[0],d1[0],d2[0]}, [r1]\n");
+  COMPARE_BOTH(Vst3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, 6),
+                    MemOperand(r1, PostIndex)),
+               "vst3.8 {d0[6],d1[6],d2[6]}, [r1]!\n");
+  COMPARE_BOTH(Vst3(Untyped8,
+                    NeonRegisterList(d0, d2, kSingle, 7),
+                    MemOperand(r1, r2, PostIndex)),
+               "vst3.8 {d0[7],d1[7],d2[7]}, [r1], r2\n");
+
+  COMPARE_BOTH(Vst4(Untyped8,
+                    NeonRegisterList(d10, d13, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst4.8 {d10,d11,d12,d13}, [r1]\n");
+  COMPARE_BOTH(Vst4(Untyped8,
+                    NeonRegisterList(d10, d13, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst4.8 {d10,d11,d12,d13}, [r1]!\n");
+  COMPARE_BOTH(Vst4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, kMultipleLanes),
+                    AlignedMemOperand(r8, kNoAlignment, r9, PostIndex)),
+               "vst4.8 {d0,d1,d2,d3}, [r8], r9\n");
+  COMPARE_BOTH(Vst4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, 0),
+                    AlignedMemOperand(r1, kNoAlignment)),
+               "vst4.8 {d0[0],d1[0],d2[0],d3[0]}, [r1]\n");
+  COMPARE_BOTH(Vst4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, 0),
+                    AlignedMemOperand(r1, kNoAlignment, PostIndex)),
+               "vst4.8 {d0[0],d1[0],d2[0],d3[0]}, [r1]!\n");
+  COMPARE_BOTH(Vst4(Untyped8,
+                    NeonRegisterList(d0, d3, kSingle, 0),
+                    AlignedMemOperand(r1, kNoAlignment, r2, PostIndex)),
+               "vst4.8 {d0[0],d1[0],d2[0],d3[0]}, [r1], r2\n");
+
+  CLEANUP();
+}
+
+
 TEST(assembler_vldm_vstm_negative) {
   SETUP();