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| author | Jacob Bramley <jacob.bramley@arm.com> | 2019-01-15 14:01:32 +0000 |
|---|---|---|
| committer | Jacob Bramley <jacob.bramley@arm.com> | 2019-02-11 15:20:01 +0000 |
| commit | 2f762bd8c4e2deea145317863241d7b02107cbd7 (patch) | |
| tree | 5c1a1448d663e0e6b9a2939c7c4d5a277a69057e | |
| parent | f59d45e4fcd4bbc22c6c2ac6a92c4aa6c4f5b6c7 (diff) | |
Trivial comment fix near SystemRegister.
Change-Id: Ia12ff287d33444fa0a994806468f116cb0ce8f9c
| -rw-r--r-- | src/aarch64/constants-aarch64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h index 5c3bd491..696bc9ce 100644 --- a/src/aarch64/constants-aarch64.h +++ b/src/aarch64/constants-aarch64.h @@ -397,7 +397,7 @@ class SystemRegisterEncoder { // System/special register names. // This information is not encoded as one field but as the concatenation of -// multiple fields (Op0<0>, Op1, Crn, Crm, Op2). +// multiple fields (Op0, Op1, Crn, Crm, Op2). enum SystemRegister { NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, |