aboutsummaryrefslogtreecommitdiff
path: root/sim-rev64-4h-trace-arm64.h
blob: 6ad08091f841a44fc61dc2479bbba84efd64d520 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_REV64_4H_TRACE_AARCH64_H_
#define VIXL_SIM_REV64_4H_TRACE_AARCH64_H_

const uint16_t kExpected_NEON_rev64_4H[] = {
  0xfff0, 0xff83, 0xff82, 0xff81,
  0xfffd, 0xfff0, 0xff83, 0xff82,
  0xfffe, 0xfffd, 0xfff0, 0xff83,
  0xffff, 0xfffe, 0xfffd, 0xfff0,
  0x0000, 0xffff, 0xfffe, 0xfffd,
  0x0001, 0x0000, 0xffff, 0xfffe,
  0x0002, 0x0001, 0x0000, 0xffff,
  0x0010, 0x0002, 0x0001, 0x0000,
  0x007d, 0x0010, 0x0002, 0x0001,
  0x007e, 0x007d, 0x0010, 0x0002,
  0x007f, 0x007e, 0x007d, 0x0010,
  0x3333, 0x007f, 0x007e, 0x007d,
  0x5555, 0x3333, 0x007f, 0x007e,
  0x7ffd, 0x5555, 0x3333, 0x007f,
  0x7ffe, 0x7ffd, 0x5555, 0x3333,
  0x7fff, 0x7ffe, 0x7ffd, 0x5555,
  0x8000, 0x7fff, 0x7ffe, 0x7ffd,
  0x8001, 0x8000, 0x7fff, 0x7ffe,
  0xaaaa, 0x8001, 0x8000, 0x7fff,
  0xcccc, 0xaaaa, 0x8001, 0x8000,
  0xff80, 0xcccc, 0xaaaa, 0x8001,
  0xff81, 0xff80, 0xcccc, 0xaaaa,
  0xff82, 0xff81, 0xff80, 0xcccc,
  0xff83, 0xff82, 0xff81, 0xff80,
};
const unsigned kExpectedCount_NEON_rev64_4H = 24;

#endif  // VIXL_SIM_REV64_4H_TRACE_AARCH64_H_