diff options
Diffstat (limited to 'sim-uqsub-4h-trace-arm64.h')
| -rw-r--r-- | sim-uqsub-4h-trace-arm64.h | 617 |
1 files changed, 617 insertions, 0 deletions
diff --git a/sim-uqsub-4h-trace-arm64.h b/sim-uqsub-4h-trace-arm64.h new file mode 100644 index 0000000..c3f68ba --- /dev/null +++ b/sim-uqsub-4h-trace-arm64.h @@ -0,0 +1,617 @@ +// Copyright 2015, VIXL authors +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of ARM Limited nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +// --------------------------------------------------------------------- +// This file is auto generated using tools/generate_simulator_traces.py. +// +// PLEASE DO NOT EDIT. +// --------------------------------------------------------------------- + +#ifndef VIXL_SIM_UQSUB_4H_TRACE_AARCH64_H_ +#define VIXL_SIM_UQSUB_4H_TRACE_AARCH64_H_ + +const uint16_t kExpected_NEON_uqsub_4H[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x5555, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x3333, 0x5554, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x007f, 0x3332, 0x5553, 0x0000, 0x0000, 0x0000, 0x0000, + 0x007e, 0x007e, 0x3331, 0x5545, 0x0000, 0x0000, 0x0000, 0x0000, + 0x007d, 0x007d, 0x3323, 0x54d8, 0x0000, 0x0000, 0x0000, 0x0000, + 0x007c, 0x006f, 0x32b6, 0x54d7, 0x0000, 0x0000, 0x0000, 0x0000, + 0x006e, 0x0002, 0x32b5, 0x54d6, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0001, 0x0001, 0x32b4, 0x2222, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 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0x0000, 0x0000, +}; +const unsigned kExpectedCount_NEON_uqsub_4H = 576; + +#endif // VIXL_SIM_UQSUB_4H_TRACE_AARCH64_H_ |