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Diffstat (limited to 'sim-fcvtl-4s-trace-arm64.h')
-rw-r--r-- | sim-fcvtl-4s-trace-arm64.h | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/sim-fcvtl-4s-trace-arm64.h b/sim-fcvtl-4s-trace-arm64.h new file mode 100644 index 0000000..cfd579f --- /dev/null +++ b/sim-fcvtl-4s-trace-arm64.h @@ -0,0 +1,81 @@ +// Copyright 2015, VIXL authors +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of ARM Limited nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +// --------------------------------------------------------------------- +// This file is auto generated using tools/generate_simulator_traces.py. +// +// PLEASE DO NOT EDIT. +// --------------------------------------------------------------------- + +#ifndef VIXL_SIM_FCVTL_4S_TRACE_AARCH64_H_ +#define VIXL_SIM_FCVTL_4S_TRACE_AARCH64_H_ + +const uint32_t kExpected_NEON_fcvtl_4S[] = { + 0xffc00000, 0xffd22000, 0xc77fe000, 0x34000000, + 0xffd22000, 0xc77fe000, 0x34000000, 0xb4000000, + 0xc77fe000, 0x34000000, 0xb4000000, 0xb9ffe000, + 0x34000000, 0xb4000000, 0xb9ffe000, 0xffffe000, + 0xb4000000, 0xb9ffe000, 0xffffe000, 0x3f800000, + 0xb9ffe000, 0xffffe000, 0x3f800000, 0x3f802000, + 0xffffe000, 0x3f800000, 0x3f802000, 0xc0000000, + 0x3f800000, 0x3f802000, 0xc0000000, 0x477fe000, + 0x3f802000, 0xc0000000, 0x477fe000, 0x38800000, + 0xc0000000, 0x477fe000, 0x38800000, 0x387fc000, + 0x477fe000, 0x38800000, 0x387fc000, 0x33800000, + 0x38800000, 0x387fc000, 0x33800000, 0x00000000, + 0x387fc000, 0x33800000, 0x00000000, 0x80000000, + 0x33800000, 0x00000000, 0x80000000, 0x7f800000, + 0x00000000, 0x80000000, 0x7f800000, 0xff800000, + 0x80000000, 0x7f800000, 0xff800000, 0x3eaaa000, + 0x7f800000, 0xff800000, 0x3eaaa000, 0x3fc00000, + 0xff800000, 0x3eaaa000, 0x3fc00000, 0x41200000, + 0x3eaaa000, 0x3fc00000, 0x41200000, 0xbfc00000, + 0x3fc00000, 0x41200000, 0xbfc00000, 0xc1200000, + 0x41200000, 0xbfc00000, 0xc1200000, 0x3effe000, + 0xbfc00000, 0xc1200000, 0x3effe000, 0x3f000000, + 0xc1200000, 0x3effe000, 0x3f000000, 0x3f002000, + 0x3effe000, 0x3f000000, 0x3f002000, 0x3f7fe000, + 0x3f000000, 0x3f002000, 0x3f7fe000, 0x7fcfe000, + 0x3f002000, 0x3f7fe000, 0x7fcfe000, 0x7fd22000, + 0x3f7fe000, 0x7fcfe000, 0x7fd22000, 0x7fc00000, + 0x7fcfe000, 0x7fd22000, 0x7fc00000, 0x7fd22000, + 0x7fd22000, 0x7fc00000, 0x7fd22000, 0xb3800000, + 0x7fc00000, 0x7fd22000, 0xb3800000, 0xbeffe000, + 0x7fd22000, 0xb3800000, 0xbeffe000, 0xbf000000, + 0xb3800000, 0xbeffe000, 0xbf000000, 0xbf002000, + 0xbeffe000, 0xbf000000, 0xbf002000, 0xbf7fe000, + 0xbf000000, 0xbf002000, 0xbf7fe000, 0xbf800000, + 0xbf002000, 0xbf7fe000, 0xbf800000, 0xbf802000, + 0xbf7fe000, 0xbf800000, 0xbf802000, 0xffcfe000, + 0xbf800000, 0xbf802000, 0xffcfe000, 0xffd22000, + 0xbf802000, 0xffcfe000, 0xffd22000, 0xffc00000, + 0xffcfe000, 0xffd22000, 0xffc00000, 0xffd22000, + 0xffd22000, 0xffc00000, 0xffd22000, 0xc77fe000, +}; +const unsigned kExpectedCount_NEON_fcvtl_4S = 40; + +#endif // VIXL_SIM_FCVTL_4S_TRACE_AARCH64_H_ |