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Diffstat (limited to 'sim-fcvtau-ws-trace-arm64.h')
-rw-r--r-- | sim-fcvtau-ws-trace-arm64.h | 145 |
1 files changed, 145 insertions, 0 deletions
diff --git a/sim-fcvtau-ws-trace-arm64.h b/sim-fcvtau-ws-trace-arm64.h new file mode 100644 index 0000000..dd9054a --- /dev/null +++ b/sim-fcvtau-ws-trace-arm64.h @@ -0,0 +1,145 @@ +// Copyright 2015, VIXL authors +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of ARM Limited nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +// --------------------------------------------------------------------- +// This file is auto generated using tools/generate_simulator_traces.py. +// +// PLEASE DO NOT EDIT. +// --------------------------------------------------------------------- + +#ifndef VIXL_SIM_FCVTAU_WS_TRACE_AARCH64_H_ +#define VIXL_SIM_FCVTAU_WS_TRACE_AARCH64_H_ + +const uint32_t kExpected_fcvtau_ws[] = { + 0u, + 0u, + 0u, + 1u, + 1u, + 1u, + 1u, + 1u, + 2u, + 10u, + 0u, + 4294967295u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 8388608u, + 8388609u, + 8388610u, + 8388611u, + 16143410u, + 16777212u, + 16777213u, + 16777214u, + 16777215u, + 4194304u, + 4194305u, + 4194305u, + 4194306u, + 8071705u, + 8388606u, + 8388607u, + 8388607u, + 8388608u, + 2097152u, + 2097152u, + 2097153u, + 2097153u, + 4035853u, + 4194303u, + 4194303u, + 4194304u, + 4194304u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 4294967295u, + 4294967295u, + 4294967295u, + 4294967295u, + 0u, + 0u, + 0u, + 2147483520u, + 2147483648u, +}; +const unsigned kExpectedCount_fcvtau_ws = 104; + +#endif // VIXL_SIM_FCVTAU_WS_TRACE_AARCH64_H_ |