From 0cafdc3cb6361190dd22e44c322bde4a6fd631dd Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Mon, 8 Sep 2014 18:01:07 +0100 Subject: add board_recovery_image_0.8.1.zip Signed-off-by: Ryan Harkin --- SITE1/HBI0262B/board.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 SITE1/HBI0262B/board.txt (limited to 'SITE1/HBI0262B/board.txt') diff --git a/SITE1/HBI0262B/board.txt b/SITE1/HBI0262B/board.txt new file mode 100644 index 0000000..d537971 --- /dev/null +++ b/SITE1/HBI0262B/board.txt @@ -0,0 +1,20 @@ +BOARD: HBI0262 +TITLE: V2M-Juno DevChip Configuration File + +[SCC REGISTERS] +TOTALSCCS: 10 ;Total Number of SCC registers +SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats +SCC: 0x100 0x003F1000 ;A57 PLL Register 0 (800MHz) +SCC: 0x104 0x0001F300 ;A57 PLL Register 1 +SCC: 0x108 0x00371000 ;A53 PLL Register 0 (700MHz) +SCC: 0x10C 0x0001B300 ;A53 PLL Register 1 +SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz) +SCC: 0x11C 0x0001F100 ;SYS PLL Register 1 +SCC: 0x0F8 0x0BEC0000 ;BL1 entry point + +SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default + ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK + ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1) +SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default + ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK + ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1) -- cgit v1.2.3