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Diffstat (limited to 'SITE1/HBI0249A/board.txt')
| -rw-r--r-- | SITE1/HBI0249A/board.txt | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/SITE1/HBI0249A/board.txt b/SITE1/HBI0249A/board.txt new file mode 100644 index 0000000..ae53571 --- /dev/null +++ b/SITE1/HBI0249A/board.txt @@ -0,0 +1,80 @@ +BOARD: HBI0249
+TITLE: V2P-CA15_A7 Configuration File
+
+[DCCS]
+TOTALDCCS: 1 ;Total Number of DCCS
+M0FILE: dbb_v107.ebf ;DCC0 Filename
+M0MODE: MICRO ;DCC0 Programming Mode
+
+[FPGAS]
+TOTALFPGAS: 0 ;Total Number of FPGAs
+
+[TAPS]
+TOTALTAPS: 3 ;Total Number of TAPs
+T0NAME: STM32TMC ;TAP0 Device Name
+T0FILE: NONE ;TAP0 Filename
+T0MODE: NONE ;TAP0 Programming Mode
+T1NAME: STM32CM3 ;TAP1 Device Name
+T1FILE: NONE ;TAP1 Filename
+T1MODE: NONE ;TAP1 Programming Mode
+T2NAME: CORTEXA15 ;TAP2 Device Name
+T2FILE: NONE ;TAP2 Filename
+T2MODE: NONE ;TAP2 Programming Mode
+
+[OSCCLKS]
+TOTALOSCCLKS: 9 ;Total Number of OSCCLKS
+OSC0: 50.0 ;CPUREFCLK0 A15 CPU (20:1 - 1.0GHz)
+OSC1: 50.0 ;CPUREFCLK1 A15 CPU (20:1 - 1.0GHz)
+OSC2: 40.0 ;CPUREFCLK0 A7 CPU (20:1 - 800MHz)
+OSC3: 40.0 ;CPUREFCLK1 A7 CPU (20:1 - 800MHz)
+OSC4: 40.0 ;HSBM AXI (40MHz)
+OSC5: 23.75 ;HDLCD (23.75MHz - TC PLL is in bypass)
+OSC6: 50.0 ;SMB (50MHz)
+OSC7: 50.0 ;SYSREFCLK (20:1 - 1.0GHz, ACLK - 500MHz)
+OSC8: 50.0 ;DDR2 (8:1 - 400MHz)
+
+[SCC REGISTERS]
+TOTALSCCS: 32 ;Total Number of SCC registers
+SCC: 0x018 0x1FFFFFFF ;Reset control (CA7s running, CA15s running) - uncomment this for normal operation
+;SCC: 0x018 0x1FFFF000 ;Reset control - (CA7s running, CA15s reset) - uncomment this to hold A15 cluster in reset
+;SCC: 0x018 0x00001FFF ;Reset control - (CA7s reset, CA15s running) - uncomment this to hold A7 cluster in reset
+SCC: 0x01C 0xFF00FF00 ;CFGRW3 - SMC CS6/7 N/U
+SCC: 0x118 0x01CD1011 ;CFGRW17 - HDLCD PLL external bypass
+SCC: 0x700 0x00320003 ;CFGRW48 - Boot cluster and CPU (CA15[0]) - uncomment this to boot on A15 cluster
+;SCC: 0x700 0x10320003 ;CFGRW48 - Boot cluster and CPU (CA7[0]) - uncomment this to boot on A7 cluster
+
+ ;Set the CPU clock PLLs
+SCC: 0x120 0x022F1010 ;CFGRW19 - CA15_0 PLL control - 20:1 (lock OFF)
+SCC: 0x124 0x0011710D ;CFGRW20 - CA15_0 PLL value
+SCC: 0x128 0x022F1010 ;CFGRW21 - CA15_1 PLL control - 20:1 (lock OFF)
+SCC: 0x12C 0x0011710D ;CFGRW22 - CA15_1 PLL value
+SCC: 0x130 0x022F1010 ;CFGRW23 - CA7_0 PLL control - 20:1 (lock OFF)
+SCC: 0x134 0x0011710D ;CFGRW24 - CA7_0 PLL value
+SCC: 0x138 0x022F1010 ;CFGRW25 - CA7_1 PLL control - 20:1 (lock OFF)
+SCC: 0x13C 0x0011710D ;CFGRW26 - CA7_1 PLL value
+
+ ;Power management interface
+SCC: 0xC00 0x00000003 ;Control (enable power management)
+SCC: 0xC04 0x000005DC ;Latency in uS
+SCC: 0xC08 0x00000000 ;Reserved
+SCC: 0xC0C 0x00000000 ;Reserved
+
+ ;CA15 performance values: 0xVVVFFFFF
+SCC: 0xC10 0x384061A8 ;CA15 PERFVAL0, 900mV, 20,000*20= 500MHz
+SCC: 0xC14 0x38407530 ;CA15 PERFVAL1, 900mV, 25,000*20= 600MHz
+SCC: 0xC18 0x384088B8 ;CA15 PERFVAL2, 900mV, 30,000*20= 700MHz
+SCC: 0xC1C 0x38409C40 ;CA15 PERFVAL3, 900mV, 35,000*20= 800MHz
+SCC: 0xC20 0x3840AFC8 ;CA15 PERFVAL4, 900mV, 40,000*20= 900MHz
+SCC: 0xC24 0x3840C350 ;CA15 PERFVAL5, 900mV, 45,000*20=1000MHz
+SCC: 0xC28 0x3CF0D6D8 ;CA15 PERFVAL6, 975mV, 50,000*20=1100MHz
+SCC: 0xC2C 0x41A0EA60 ;CA15 PERFVAL7, 1050mV, 55,000*20=1200MHz
+
+ ;CA7 performance values: 0xVVVFFFFF
+SCC: 0xC30 0x3840445C ;CA7 PERFVAL0, 900mV, 10,000*20= 350MHz
+SCC: 0xC34 0x38404E20 ;CA7 PERFVAL1, 900mV, 15,000*20= 400MHz
+SCC: 0xC38 0x384061A8 ;CA7 PERFVAL2, 900mV, 20,000*20= 500MHz
+SCC: 0xC3C 0x38407530 ;CA7 PERFVAL3, 900mV, 25,000*20= 600MHz
+SCC: 0xC40 0x384088B8 ;CA7 PERFVAL4, 900mV, 30,000*20= 700MHz
+SCC: 0xC44 0x38409C40 ;CA7 PERFVAL5, 900mV, 35,000*20= 800MHz
+SCC: 0xC48 0x3CF0AFC8 ;CA7 PERFVAL6, 975mV, 40,000*20= 900MHz
+SCC: 0xC4C 0x41A0C350 ;CA7 PERFVAL7, 1050mV, 45,000*20=1000MHz
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