diff options
Diffstat (limited to 'SITE1/HBI0249A/board.txt')
| -rw-r--r-- | SITE1/HBI0249A/board.txt | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/SITE1/HBI0249A/board.txt b/SITE1/HBI0249A/board.txt index 3a0f7ee..baa7dca 100644 --- a/SITE1/HBI0249A/board.txt +++ b/SITE1/HBI0249A/board.txt @@ -34,7 +34,8 @@ OSC7: 50.0 ;SYSREFCLK (20:1 - 1.0GHz, ACLK - 500MHz) OSC8: 50.0 ;DDR2 (8:1 - 400MHz)
[SCC REGISTERS]
-TOTALSCCS: 31 ;Total Number of SCC registers
+TOTALSCCS: 32 ;Total Number of SCC registers
+
SCC: 0x01C 0xFF00FF00 ;CFGRW3 - SMC CS6/7 N/U
SCC: 0x118 0x01CD1011 ;CFGRW17 - HDLCD PLL external bypass
;SCC: 0x700 0x00320003 ;CFGRW48 - [25:24]Boot CPU [28]Boot Cluster (default CA7_0)
@@ -46,6 +47,16 @@ SCC: 0x700 0x0032F003 ;CFGRW48 - [25:24]Boot CPU [28]Boot Cluster (def ; [12]: Use per-cpu mailboxes for power management (default: disabled)
; [11]: A15 executes WFEs as nops (default: disabled)
+SCC: 0x400 0x33330c00 ;CFGREG41 - A15 configuration register 0 (Default 0x33330c80)
+ ; [29:28] SPNIDEN
+ ; [25:24] SPIDEN
+ ; [21:20] NIDEN
+ ; [17:16] DBGEN
+ ; [13:12] CFGTE
+ ; [9:8] VINITHI_CORE
+ ; [7] IMINLN
+ ; [3:0] CLUSTER_ID
+
;Set the CPU clock PLLs
SCC: 0x120 0x022F1010 ;CFGRW19 - CA15_0 PLL control - 20:1 (lock OFF)
SCC: 0x124 0x0011710D ;CFGRW20 - CA15_0 PLL value
|