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authorRyan Harkin <ryan.harkin@linaro.org>2013-06-14 13:50:38 +0100
committerRyan Harkin <ryan.harkin@linaro.org>2013-06-14 13:50:38 +0100
commitaa495330fac68d9e2220510cc25040ab92500f6d (patch)
tree24ac3b8c02458d09983e3ab32a23b12ed367063a
parent75bef16f29442eda1f3de3e268fd17f992d253a0 (diff)
parent4b09e17342c99b7bf8f9f3dbe3abf362c3008de8 (diff)
downloadvexpress-firmware-aa495330fac68d9e2220510cc25040ab92500f6d.tar.gz
Merge branch 'arm-releases'
-rw-r--r--MB/HBI0190D/board.txt18
-rw-r--r--MB/HBI0190D/io_b107.bitbin1414696 -> 0 bytes
-rw-r--r--MB/HBI0190D/io_b108.bitbin0 -> 1414696 bytes
-rw-r--r--MB/HBI0190D/io_b115.bitbin1414696 -> 0 bytes
-rw-r--r--MB/HBI0190D/io_b116.bitbin0 -> 1414696 bytes
-rw-r--r--MB/HBI0190D/io_b207.bitbin1414702 -> 0 bytes
-rw-r--r--MB/HBI0190D/io_b208.bitbin0 -> 1414702 bytes
-rw-r--r--MB/HBI0190D/io_b215.bitbin1414702 -> 0 bytes
-rw-r--r--MB/HBI0190D/io_b216.bitbin0 -> 1414702 bytes
-rw-r--r--MB/HBI0190D/mbb_v234.ebfbin187284 -> 0 bytes
-rw-r--r--MB/HBI0190D/mbb_v311.ebfbin0 -> 186772 bytes
-rw-r--r--MB/HBI0190D/tapid.arm4
-rw-r--r--SITE1/HBI0191B/board.txt4
-rw-r--r--SITE1/HBI0191B/dbb_v112.ebfbin20996 -> 0 bytes
-rw-r--r--SITE1/HBI0191B/dbb_v114.ebfbin0 -> 20548 bytes
-rw-r--r--SITE1/HBI0191B/images.txt21
-rw-r--r--SITE1/HBI0225B/images.txt22
-rw-r--r--SITE1/HBI0237A/board.txt11
-rw-r--r--SITE1/HBI0237A/dbb_v102.ebfbin21892 -> 0 bytes
-rw-r--r--SITE1/HBI0237A/dbb_v107.ebfbin0 -> 23092 bytes
-rw-r--r--SITE1/HBI0237A/images.txt16
-rw-r--r--SITE1/HBI0249A/board.txt80
-rw-r--r--SITE1/HBI0249A/dbb_v110.ebfbin0 -> 31284 bytes
-rw-r--r--SITE1/HBI0249A/images.txt36
-rw-r--r--SITE2/HBI0192B/board.txt4
-rw-r--r--SITE2/HBI0192C/board.txt4
-rw-r--r--SITE2/HBI0217B/AN305/f550r0p0.bitbin0 -> 18011652 bytes
-rw-r--r--SITE2/HBI0217B/AN305/f550r0p0.txt22
-rw-r--r--SITE2/HBI0217B/AN305/f760r0p0.bitbin0 -> 23102986 bytes
-rw-r--r--SITE2/HBI0217B/AN305/f760r0p0.txt16
-rw-r--r--SITE2/HBI0217B/board.txt12
-rw-r--r--SITE2/HBI0217B/board_1.txt8
-rw-r--r--SITE2/HBI0217B/dbb_v112.ebfbin29492 -> 0 bytes
-rw-r--r--SITE2/HBI0217B/dbb_v115.ebfbin0 -> 28132 bytes
-rw-r--r--SITE2/HBI0217B/dbb_v213.ebfbin27060 -> 0 bytes
-rw-r--r--SITE2/HBI0217B/dbb_v215.ebfbin0 -> 25604 bytes
-rw-r--r--SITE2/HBI0247B/AN307/a307r0p0.bitbin0 -> 55917254 bytes
-rw-r--r--SITE2/HBI0247B/AN307/a307r0p0.txt27
-rw-r--r--SITE2/HBI0247B/board.txt13
-rw-r--r--SITE2/HBI0247B/board_1.txt11
-rw-r--r--SITE2/HBI0247B/dbb_v108.ebfbin0 -> 32164 bytes
-rw-r--r--SITE2/HBI0247C/AN307/a307r0p0.bitbin0 -> 55917254 bytes
-rw-r--r--SITE2/HBI0247C/AN307/a307r0p0.txt27
-rw-r--r--SITE2/HBI0247C/board.txt13
-rw-r--r--SITE2/HBI0247C/board_1.txt11
-rw-r--r--SITE2/HBI0247C/dbb_v108.ebfbin0 -> 32164 bytes
-rw-r--r--SOFTWARE/bm_v500l.axfbin178580 -> 0 bytes
-rw-r--r--SOFTWARE/bm_v500r.axfbin175148 -> 0 bytes
-rw-r--r--SOFTWARE/bm_v517l.axfbin0 -> 190704 bytes
-rw-r--r--SOFTWARE/bm_v519r.axfbin0 -> 199000 bytes
-rw-r--r--SOFTWARE/booscr15.txt3
-rw-r--r--SOFTWARE/booscr5s.txt2
-rw-r--r--SOFTWARE/booscr9.txt1
-rw-r--r--SOFTWARE/booscr_l.txt1
-rw-r--r--SOFTWARE/booscr_r.txt1
-rw-r--r--SOFTWARE/ca15a7.dtbbin0 -> 8401 bytes
-rw-r--r--SOFTWARE/ca5s.dtbbin0 -> 6539 bytes
-rw-r--r--SOFTWARE/cramfs.binbin37285888 -> 0 bytes
-rw-r--r--SOFTWARE/deb_i_l.binbin4648444 -> 0 bytes
-rw-r--r--SOFTWARE/deb_i_r.binbin4648856 -> 0 bytes
-rw-r--r--SOFTWARE/kernel.binbin0 -> 4105752 bytes
-rw-r--r--SOFTWARE/kernel15.binbin2053420 -> 0 bytes
-rw-r--r--SOFTWARE/kernel_l.binbin1947864 -> 0 bytes
-rw-r--r--SOFTWARE/kernel_r.binbin1947084 -> 0 bytes
-rw-r--r--readme.txt161
65 files changed, 461 insertions, 88 deletions
diff --git a/MB/HBI0190D/board.txt b/MB/HBI0190D/board.txt
index 5ddcdb1..6911210 100644
--- a/MB/HBI0190D/board.txt
+++ b/MB/HBI0190D/board.txt
@@ -1,16 +1,15 @@
-
BOARD: HBI0190
TITLE: MotherBoard Configuration File
[MCCS]
-MBBIOS: mbb_v234.ebf ;MB BIOS IMAGE
+MBBIOS: mbb_v311.ebf ;MB BIOS IMAGE
[FPGAS]
-MBIOFPGA: io_b107.bit ;REQUIRED TO ALLOW UPDATE FROM VECD v1.x
-MBIOFPGA1: io_b107.bit ;MB LEGACY IOFPGA IMAGE FOR SITE 1 BOOT MASTER
-MBIOFPGA2: io_b207.bit ;MB LEGACY IOFPGA IMAGE FOR SITE 2 BOOT MASTER
-MBIOFPGA3: io_b115.bit ;MB A SERIES IOFPGA IMAGE FOR SITE 1 BOOT MASTER
-MBIOFPGA4: io_b215.bit ;MB A SERIES IOFPGA IMAGE FOR SITE 2 BOOT MASTER
+MBIOFPGA: io_b108.bit ;REQUIRED TO ALLOW UPDATE FROM VECD v1.x
+MBIOFPGA1: io_b108.bit ;MB LEGACY IOFPGA IMAGE FOR SITE 1 BOOT MASTER
+MBIOFPGA2: io_b208.bit ;MB LEGACY IOFPGA IMAGE FOR SITE 2 BOOT MASTER
+MBIOFPGA3: io_b116.bit ;MB A SERIES IOFPGA IMAGE FOR SITE 1 BOOT MASTER
+MBIOFPGA4: io_b216.bit ;MB A SERIES IOFPGA IMAGE FOR SITE 2 BOOT MASTER
MBMUXFPGA: mux_b1c.bit ;MB MUXFPGA IMAGE
[OSCCLKS]
@@ -21,8 +20,3 @@ OSC2: 24.0 ;OSC2 IOFPGA REFCLK in MHz
OSC3: 24.0 ;OSC3 Reserved
OSC4: 24.0 ;OSC4 SB_GCLK in MHz
OSC5: 24.0 ;OSC5 Reserved
-
-
-
-
-
diff --git a/MB/HBI0190D/io_b107.bit b/MB/HBI0190D/io_b107.bit
deleted file mode 100644
index 6d9cdc8..0000000
--- a/MB/HBI0190D/io_b107.bit
+++ /dev/null
Binary files differ
diff --git a/MB/HBI0190D/io_b108.bit b/MB/HBI0190D/io_b108.bit
new file mode 100644
index 0000000..e9f1914
--- /dev/null
+++ b/MB/HBI0190D/io_b108.bit
Binary files differ
diff --git a/MB/HBI0190D/io_b115.bit b/MB/HBI0190D/io_b115.bit
deleted file mode 100644
index 9a1a465..0000000
--- a/MB/HBI0190D/io_b115.bit
+++ /dev/null
Binary files differ
diff --git a/MB/HBI0190D/io_b116.bit b/MB/HBI0190D/io_b116.bit
new file mode 100644
index 0000000..7b8362d
--- /dev/null
+++ b/MB/HBI0190D/io_b116.bit
Binary files differ
diff --git a/MB/HBI0190D/io_b207.bit b/MB/HBI0190D/io_b207.bit
deleted file mode 100644
index a2bf22e..0000000
--- a/MB/HBI0190D/io_b207.bit
+++ /dev/null
Binary files differ
diff --git a/MB/HBI0190D/io_b208.bit b/MB/HBI0190D/io_b208.bit
new file mode 100644
index 0000000..3657dc7
--- /dev/null
+++ b/MB/HBI0190D/io_b208.bit
Binary files differ
diff --git a/MB/HBI0190D/io_b215.bit b/MB/HBI0190D/io_b215.bit
deleted file mode 100644
index f38e754..0000000
--- a/MB/HBI0190D/io_b215.bit
+++ /dev/null
Binary files differ
diff --git a/MB/HBI0190D/io_b216.bit b/MB/HBI0190D/io_b216.bit
new file mode 100644
index 0000000..165c8ba
--- /dev/null
+++ b/MB/HBI0190D/io_b216.bit
Binary files differ
diff --git a/MB/HBI0190D/mbb_v234.ebf b/MB/HBI0190D/mbb_v234.ebf
deleted file mode 100644
index b3564bc..0000000
--- a/MB/HBI0190D/mbb_v234.ebf
+++ /dev/null
Binary files differ
diff --git a/MB/HBI0190D/mbb_v311.ebf b/MB/HBI0190D/mbb_v311.ebf
new file mode 100644
index 0000000..d13470a
--- /dev/null
+++ b/MB/HBI0190D/mbb_v311.ebf
Binary files differ
diff --git a/MB/HBI0190D/tapid.arm b/MB/HBI0190D/tapid.arm
index d18c05f..653e477 100644
--- a/MB/HBI0190D/tapid.arm
+++ b/MB/HBI0190D/tapid.arm
@@ -2,8 +2,6 @@
#
# Copyright (C) 2008 ARM Limited. All rights reserved.
#
-# Revision: 2.03
-#
# This file contains a definition of the devices names, ID codes, ID code mask
# and IR lengths for devices used on ARM boards. This file is read by the
# progcards_usb.exe program and used to determine if a device ID is valid and
@@ -91,7 +89,7 @@ PLX8518 0x1214639B 0xFFFFFFFF 5
PLX8518 0x4214639B 0xFFFFFFFF 5
STM32TMC 0x16410041 0x0FFF0FFF 5
-STM32CM3 0x3BA00477 0xFFFFFFFF 4
+STM32CM3 0x3BA00477 0x0FFFFFFF 4
IDT89HPES32H8 0x08035067 0xFFFFFFFF 6
NX5000_BYPASS 0x14951185 0xFFFFFFFF 4
NX5000_FC1152 0x03387589 0xFFFFFFFF 4
diff --git a/SITE1/HBI0191B/board.txt b/SITE1/HBI0191B/board.txt
index 4194e2b..2c307ff 100644
--- a/SITE1/HBI0191B/board.txt
+++ b/SITE1/HBI0191B/board.txt
@@ -5,7 +5,7 @@ TITLE: V2P-CA9 Configuration File
[DCCS]
TOTALDCCS: 1 ;(1) Total Number of DCCS - Do not change this value
-M0FILE: dbb_v112.ebf ;DCC0 Filename
+M0FILE: dbb_v114.ebf ;DCC0 Filename
M0MODE: MICRO ;DCC0 Programming Mode
[FPGAS]
@@ -48,7 +48,7 @@ SCC: 0x008 0x00000000 ;CFGRW2 Power up settings - Misc, A9 static sign
; Alternative Clock options
-;
+;
; To use these values, copy the SCC: line and replace the lines in the [SCC REGISTERS] section above.
; Do not place comments between the [SCC REGISTERS] and the last SCC: line.
diff --git a/SITE1/HBI0191B/dbb_v112.ebf b/SITE1/HBI0191B/dbb_v112.ebf
deleted file mode 100644
index 4c577dd..0000000
--- a/SITE1/HBI0191B/dbb_v112.ebf
+++ /dev/null
Binary files differ
diff --git a/SITE1/HBI0191B/dbb_v114.ebf b/SITE1/HBI0191B/dbb_v114.ebf
new file mode 100644
index 0000000..a2ea329
--- /dev/null
+++ b/SITE1/HBI0191B/dbb_v114.ebf
Binary files differ
diff --git a/SITE1/HBI0191B/images.txt b/SITE1/HBI0191B/images.txt
index 4077850..fc0f25d 100644
--- a/SITE1/HBI0191B/images.txt
+++ b/SITE1/HBI0191B/images.txt
@@ -1,9 +1,18 @@
TITLE: Versatile Express Images Configuration File
[IMAGES]
-TOTALIMAGES: 1 ;Number of Images (Max : 32)
-NOR0UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
-NOR0ADDRESS: 44000000 ;Image Flash Address
-NOR0FILE: \SOFTWARE\A9\uefi.bin ;Image File Name
-NOR0LOAD: 44000000 ;Image Load Address
-NOR0ENTRY: 44000000 ;Image Entry Point
+TOTALIMAGES: 3 ;Number of Images (Max : 32)
+NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR0ADDRESS: BOOT ;Image Flash Address
+NOR0FILE: \SOFTWARE\bm_v517l.axf ;Image File Name
+
+NOR1UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR1ADDRESS: 41000000 ;Image Flash Address
+NOR1FILE: \SOFTWARE\kernel.bin ;Image File Name
+NOR1LOAD: 60008000 ;Image Load Address
+NOR1ENTRY: 60008000 ;Image Entry Point
+
+NOR2UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR2ADDRESS: 40000000 ;Image Flash Address
+NOR2NAME: BOOTSCRIPT ;Image Name
+NOR2FILE: \SOFTWARE\booscr9.txt ;Image File Name
diff --git a/SITE1/HBI0225B/images.txt b/SITE1/HBI0225B/images.txt
index 90d9bd5..a802070 100644
--- a/SITE1/HBI0225B/images.txt
+++ b/SITE1/HBI0225B/images.txt
@@ -4,15 +4,21 @@ TITLE: Versatile Express Images Configuration File
TOTALIMAGES: 3 ;Number of Images (Max : 32)
NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
NOR0ADDRESS: BOOT ;Image Flash Address
-NOR0FILE: \SOFTWARE\bm_v513r.axf ;Image File Name
+NOR0FILE: \SOFTWARE\bm_v517r.axf ;Image File Name
NOR1UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
NOR1ADDRESS: 00000000 ;Image Flash Address
NOR1NAME: BOOTSCRIPT ;Image Name
-NOR1FILE: \SOFTWARE\bootscr.txt ;Image File Name
-
-NOR2UPDATE: AUTO
-NOR2ADDRESS: 0d000000
-NOR2FILE: \SOFTWARE\A5\u-boot.bin
-NOR2LOAD: 80800000
-NOR2ENTRY: 80800000
+NOR1FILE: \SOFTWARE\booscr5s.txt ;Image File Name
+
+NOR2UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR2ADDRESS: 00000000 ;Image Flash Address
+NOR2FILE: \SOFTWARE\ca5s.dtb ;Image File Name
+NOR2LOAD: 88000000 ;Image Load Address
+NOR2ENTRY: 00000000 ;Image Entry Point
+
+NOR3UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR3ADDRESS: 01000000 ;Image Flash Address
+NOR3FILE: \SOFTWARE\kernel.bin ;Image File Name
+NOR3LOAD: 80008000 ;Image Load Address
+NOR3ENTRY: 80008000 ;Image Entry Point
diff --git a/SITE1/HBI0237A/board.txt b/SITE1/HBI0237A/board.txt
index a805b6f..5d17f8d 100644
--- a/SITE1/HBI0237A/board.txt
+++ b/SITE1/HBI0237A/board.txt
@@ -3,7 +3,7 @@ TITLE: V2P-CA15 Configuration File
[DCCS]
TOTALDCCS: 1 ;Total Number of DCCS
-M0FILE: dbb_v102.ebf ;DCC0 Filename
+M0FILE: dbb_v107.ebf ;DCC0 Filename
M0MODE: MICRO ;DCC0 Programming Mode
[FPGAS]
@@ -23,17 +23,18 @@ T2MODE: NONE ;TAP2 Programming Mode
[OSCCLKS]
TOTALOSCCLKS: 9 ;Total Number of OSCCLKS
-OSC0: 60.0 ;CPUREFCLK0 A15 CPU (20:1 - 1.2GHz)
+OSC0: 24.0 ;CPUREFCLK0 A15 CPU (20:1 not used in CPU/AXI sync mode)
OSC1: 24.0 ;N/U
OSC2: 24.0 ;N/U
OSC3: 24.0 ;N/U
OSC4: 40.0 ;HSBM AXI (40MHz)
OSC5: 63.5 ;HDLCD (63.5MHz - TC PLL is in bypass)
OSC6: 50.0 ;SMB (50MHz)
-OSC7: 60.0 ;SYSREFCLK (20:1 - 1.2GHz, ACLK - 600MHz)
-OSC8: 40.0 ;DDR2 (8:1 - 320MHz)
+OSC7: 60.0 ;SYSREFCLK (20:1 - 1.2GHz CPU, /2 - 600MHz AXI - sync mode)
+OSC8: 50.0 ;DDR2 (8:1 - 400MHz - async mode)
[SCC REGISTERS]
-TOTALSCCS: 2 ;Total Number of SCC registers
+TOTALSCCS: 3 ;Total Number of SCC registers
SCC: 0x01C 0xFF00FF00 ;CFGRW5 - SMC CS6/7 N/U
+SCC: 0x19C 0xFF201930 ;CFGRW9 - CPU/AXI 2:1 sync mode, DDR async mode
SCC: 0x1B0 0x01CD1011 ;CFGRW14 - HDLCD PLL external bypass
diff --git a/SITE1/HBI0237A/dbb_v102.ebf b/SITE1/HBI0237A/dbb_v102.ebf
deleted file mode 100644
index 7a4cc75..0000000
--- a/SITE1/HBI0237A/dbb_v102.ebf
+++ /dev/null
Binary files differ
diff --git a/SITE1/HBI0237A/dbb_v107.ebf b/SITE1/HBI0237A/dbb_v107.ebf
new file mode 100644
index 0000000..b415ec8
--- /dev/null
+++ b/SITE1/HBI0237A/dbb_v107.ebf
Binary files differ
diff --git a/SITE1/HBI0237A/images.txt b/SITE1/HBI0237A/images.txt
index 3937cb9..2f538b4 100644
--- a/SITE1/HBI0237A/images.txt
+++ b/SITE1/HBI0237A/images.txt
@@ -1,19 +1,7 @@
TITLE: Versatile Express Images Configuration File
[IMAGES]
-TOTALIMAGES: 3 ;Number of Images (Max : 32)
+TOTALIMAGES: 1 ;Number of Images (Max : 32)
NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
NOR0ADDRESS: BOOT ;Image Flash Address
-NOR0FILE: \SOFTWARE\bm_v513r.axf ;Image File Name
-
-NOR1UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
-NOR1ADDRESS: 00000000 ;Image Flash Address
-NOR1NAME: BOOTSCRIPT ;Image Name
-NOR1FILE: \SOFTWARE\bootscr.txt ;Image File Name
-
-NOR2UPDATE: AUTO
-NOR2ADDRESS: 0d000000
-NOR2FILE: \SOFTWARE\TC1\u-boot.bin
-NOR2LOAD: 80800000
-NOR2ENTRY: 80800000
-
+NOR0FILE: \SOFTWARE\bm_v517r.axf ;Image File Name
diff --git a/SITE1/HBI0249A/board.txt b/SITE1/HBI0249A/board.txt
new file mode 100644
index 0000000..48e17f2
--- /dev/null
+++ b/SITE1/HBI0249A/board.txt
@@ -0,0 +1,80 @@
+BOARD: HBI0249
+TITLE: V2P-CA15_A7 Configuration File
+
+[DCCS]
+TOTALDCCS: 1 ;Total Number of DCCS
+M0FILE: dbb_v110.ebf ;DCC0 Filename
+M0MODE: MICRO ;DCC0 Programming Mode
+
+[FPGAS]
+TOTALFPGAS: 0 ;Total Number of FPGAs
+
+[TAPS]
+TOTALTAPS: 3 ;Total Number of TAPs
+T0NAME: STM32TMC ;TAP0 Device Name
+T0FILE: NONE ;TAP0 Filename
+T0MODE: NONE ;TAP0 Programming Mode
+T1NAME: STM32CM3 ;TAP1 Device Name
+T1FILE: NONE ;TAP1 Filename
+T1MODE: NONE ;TAP1 Programming Mode
+T2NAME: CORTEXA15 ;TAP2 Device Name
+T2FILE: NONE ;TAP2 Filename
+T2MODE: NONE ;TAP2 Programming Mode
+
+[OSCCLKS]
+TOTALOSCCLKS: 9 ;Total Number of OSCCLKS
+OSC0: 50.0 ;CPUREFCLK0 A15 CPU (20:1 - 1.0GHz)
+OSC1: 50.0 ;CPUREFCLK1 A15 CPU (20:1 - 1.0GHz)
+OSC2: 40.0 ;CPUREFCLK0 A7 CPU (20:1 - 800MHz)
+OSC3: 40.0 ;CPUREFCLK1 A7 CPU (20:1 - 800MHz)
+OSC4: 40.0 ;HSBM AXI (40MHz)
+OSC5: 23.75 ;HDLCD (23.75MHz - TC PLL is in bypass)
+OSC6: 50.0 ;SMB (50MHz)
+OSC7: 50.0 ;SYSREFCLK (20:1 - 1.0GHz, ACLK - 500MHz)
+OSC8: 50.0 ;DDR2 (8:1 - 400MHz)
+
+[SCC REGISTERS]
+TOTALSCCS: 32 ;Total Number of SCC registers
+SCC: 0x018 0x1FFFFFFF ;Reset control (CA7s running, CA15s running) - uncomment this for normal operation
+;SCC: 0x018 0x1FFFF000 ;Reset control - (CA7s running, CA15s reset) - uncomment this to hold A15 cluster in reset
+;SCC: 0x018 0x00001FFF ;Reset control - (CA7s reset, CA15s running) - uncomment this to hold A7 cluster in reset
+SCC: 0x01C 0xFF00FF00 ;CFGRW3 - SMC CS6/7 N/U
+SCC: 0x118 0x01CD1011 ;CFGRW17 - HDLCD PLL external bypass
+SCC: 0x700 0x00320003 ;CFGRW48 - Boot cluster and CPU (CA15[0]) - uncomment this to boot on A15 cluster
+;SCC: 0x700 0x10320003 ;CFGRW48 - Boot cluster and CPU (CA7[0]) - uncomment this to boot on A7 cluster
+
+ ;Set the CPU clock PLLs
+SCC: 0x120 0x022F1010 ;CFGRW19 - CA15_0 PLL control - 20:1 (lock OFF)
+SCC: 0x124 0x0011710D ;CFGRW20 - CA15_0 PLL value
+SCC: 0x128 0x022F1010 ;CFGRW21 - CA15_1 PLL control - 20:1 (lock OFF)
+SCC: 0x12C 0x0011710D ;CFGRW22 - CA15_1 PLL value
+SCC: 0x130 0x022F1010 ;CFGRW23 - CA7_0 PLL control - 20:1 (lock OFF)
+SCC: 0x134 0x0011710D ;CFGRW24 - CA7_0 PLL value
+SCC: 0x138 0x022F1010 ;CFGRW25 - CA7_1 PLL control - 20:1 (lock OFF)
+SCC: 0x13C 0x0011710D ;CFGRW26 - CA7_1 PLL value
+
+ ;Power management interface
+SCC: 0xC00 0x00000003 ;Control (enable power management)
+SCC: 0xC04 0x000005DC ;Latency in uS
+SCC: 0xC08 0x00000000 ;Reserved
+SCC: 0xC0C 0x00000000 ;Reserved
+
+ ;CA15 performance values: 0xVVVFFFFF
+SCC: 0xC10 0x384061A8 ;CA15 PERFVAL0, 900mV, 20,000*20= 500MHz
+SCC: 0xC14 0x38407530 ;CA15 PERFVAL1, 900mV, 25,000*20= 600MHz
+SCC: 0xC18 0x384088B8 ;CA15 PERFVAL2, 900mV, 30,000*20= 700MHz
+SCC: 0xC1C 0x38409C40 ;CA15 PERFVAL3, 900mV, 35,000*20= 800MHz
+SCC: 0xC20 0x3840AFC8 ;CA15 PERFVAL4, 900mV, 40,000*20= 900MHz
+SCC: 0xC24 0x3840C350 ;CA15 PERFVAL5, 900mV, 45,000*20=1000MHz
+SCC: 0xC28 0x3CF0D6D8 ;CA15 PERFVAL6, 975mV, 50,000*20=1100MHz
+SCC: 0xC2C 0x41A0EA60 ;CA15 PERFVAL7, 1050mV, 55,000*20=1200MHz
+
+ ;CA7 performance values: 0xVVVFFFFF
+SCC: 0xC30 0x3840445C ;CA7 PERFVAL0, 900mV, 10,000*20= 350MHz
+SCC: 0xC34 0x38404E20 ;CA7 PERFVAL1, 900mV, 15,000*20= 400MHz
+SCC: 0xC38 0x384061A8 ;CA7 PERFVAL2, 900mV, 20,000*20= 500MHz
+SCC: 0xC3C 0x38407530 ;CA7 PERFVAL3, 900mV, 25,000*20= 600MHz
+SCC: 0xC40 0x384088B8 ;CA7 PERFVAL4, 900mV, 30,000*20= 700MHz
+SCC: 0xC44 0x38409C40 ;CA7 PERFVAL5, 900mV, 35,000*20= 800MHz
+SCC: 0xC48 0x3CF0AFC8 ;CA7 PERFVAL6, 975mV, 40,000*20= 900MHz
+SCC: 0xC4C 0x41A0C350 ;CA7 PERFVAL7, 1050mV, 45,000*20=1000MHz
diff --git a/SITE1/HBI0249A/dbb_v110.ebf b/SITE1/HBI0249A/dbb_v110.ebf
new file mode 100644
index 0000000..0635c9a
--- /dev/null
+++ b/SITE1/HBI0249A/dbb_v110.ebf
Binary files differ
diff --git a/SITE1/HBI0249A/images.txt b/SITE1/HBI0249A/images.txt
index f3aaabf..d03cf9f 100644
--- a/SITE1/HBI0249A/images.txt
+++ b/SITE1/HBI0249A/images.txt
@@ -1,32 +1,26 @@
TITLE: Versatile Express Images Configuration File
[IMAGES]
-TOTALIMAGES: 5 ;Number of Images (Max : 32)
+TOTALIMAGES: 4 ;Number of Images (Max: 32)
+
NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
NOR0ADDRESS: BOOT ;Image Flash Address
-NOR0FILE: \SOFTWARE\bm_v513r.axf ;Image File Name
+NOR0FILE: \SOFTWARE\bm_v519r.axf ;Image File Name
NOR1UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
-NOR1ADDRESS: 0c000000 ;Image Flash Address
-NOR1FILE: \SOFTWARE\TC2\zimage.bin ;Image File Name
-NOR1LOAD: 80008000 ;Image Load Address
-NOR1ENTRY: 80008000 ;Image Entry Point
+NOR1ADDRESS: 00000000 ;Image Flash Address
+NOR1NAME: BOOTSCRIPT ;Image Flash Name
+NOR1FILE: \SOFTWARE\booscr15.txt ;Image File Name
NOR2UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
-NOR2ADDRESS: 00400000 ;Image Flash Address
-NOR2FILE: \SOFTWARE\TC2\tc2_dtb.bin ;Image File Name
-NOR2LOAD: a0000000 ;Image Load Address
-NOR2ENTRY: a0000000 ;Image Load Address
+NOR2ADDRESS: 00000000 ;Image Flash Address
+NOR2FILE: \SOFTWARE\ca15a7.dtb ;Image File Name
+NOR2LOAD: 88000000 ;Image Load Address
+NOR2ENTRY: 00000000 ;Image Entry Point
NOR3UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
-NOR3ADDRESS: 0d000000 ;Image Flash Address
-NOR3FILE: \SOFTWARE\TC2\initrd.bin ;Image File Name
-NOR3LOAD: a0100000 ;Image Load Address
-NOR3ENTRY: a0100000 ;Image Entry Point
-
-NOR4UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
-NOR4ADDRESS: 00000000 ;Image Flash Address
-NOR4NAME: BOOTSCRIPT ;Image Flash Name
-NOR4FILE: \SOFTWARE\TC2\bootscr.txt ;Image File Name
-
-
+NOR3ADDRESS: 00000000 ;Image Flash Address
+NOR3NAME: kernel ;Image Flash Name
+NOR3FILE: \SOFTWARE\kernel.bin ;Image File Name
+NOR3LOAD: 80008000 ;Image Load Address
+NOR3ENTRY: 80008000 ;Image Entry Point
diff --git a/SITE2/HBI0192B/board.txt b/SITE2/HBI0192B/board.txt
index 508823e..724722c 100644
--- a/SITE2/HBI0192B/board.txt
+++ b/SITE2/HBI0192B/board.txt
@@ -4,12 +4,10 @@ TITLE: FPGA V2F-1XV5
[APPLICATION NOTE]
APPNOTE: ANxxx\axxxrxpx.txt ;Please select the required application note
;APPNOTE: AN224\a224r0p1.txt
-;APPNOTE: AN243\a243r0p0.txt
+;APPNOTE: AN243\a243r0p1.txt
;APPNOTE: AN283\a283r0p0.txt
[DCCS]
TOTALDCCS: 1 ;Total Number of DCCS (Max:8)
M0FILE: dbb_v135.ebf ;DCC0 Filename
M0MODE: MICRO ;DCC0 Programming Mode
-
-
diff --git a/SITE2/HBI0192C/board.txt b/SITE2/HBI0192C/board.txt
index 508823e..724722c 100644
--- a/SITE2/HBI0192C/board.txt
+++ b/SITE2/HBI0192C/board.txt
@@ -4,12 +4,10 @@ TITLE: FPGA V2F-1XV5
[APPLICATION NOTE]
APPNOTE: ANxxx\axxxrxpx.txt ;Please select the required application note
;APPNOTE: AN224\a224r0p1.txt
-;APPNOTE: AN243\a243r0p0.txt
+;APPNOTE: AN243\a243r0p1.txt
;APPNOTE: AN283\a283r0p0.txt
[DCCS]
TOTALDCCS: 1 ;Total Number of DCCS (Max:8)
M0FILE: dbb_v135.ebf ;DCC0 Filename
M0MODE: MICRO ;DCC0 Programming Mode
-
-
diff --git a/SITE2/HBI0217B/AN305/f550r0p0.bit b/SITE2/HBI0217B/AN305/f550r0p0.bit
new file mode 100644
index 0000000..4616389
--- /dev/null
+++ b/SITE2/HBI0217B/AN305/f550r0p0.bit
Binary files differ
diff --git a/SITE2/HBI0217B/AN305/f550r0p0.txt b/SITE2/HBI0217B/AN305/f550r0p0.txt
new file mode 100644
index 0000000..5048ca4
--- /dev/null
+++ b/SITE2/HBI0217B/AN305/f550r0p0.txt
@@ -0,0 +1,22 @@
+BOARD: HBI0217
+TITLE: AN305
+
+[FPGAS]
+TOTALFPGAS: 1 ;Total Number of FPGAS (Max:8)
+F0FILE: f550r0p0.bit ;FPGA0 Filename
+F0MODE: FPGA_PCM ;FPGA0 Programming Mode
+
+[OSCCLKS]
+TOTALOSCCLKS: 6 ;Total Number of OSCCLKS (Max:8)
+OSC0: 80 ;OSC1 Frequency in MHz (550T ACLK)
+OSC1: 120 ;OSC2 Frequency in MHz (550T MCLK REF)
+OSC2: 23.75 ;OSC3 Frequency in MHz (550T CLCD)
+OSC3: 40 ;OSC4 Frequency in MHz (760 ACLK_LINK & ACLK(ACLK_LINKx2))
+OSC4: 33 ;OSC5 Frequency in MHz
+OSC5: 24 ;OSC6 Not used
+
+
+[SCC REGISTERS]
+TOTALSCCS: 2 ;Total Number of SCC registers defined
+SCC: 0x000 0x01234567 ;SCC gereral read/write regsiter address/value
+SCC: 0x004 0x89ABCDEF ;SCC gereral read/write register address/value
diff --git a/SITE2/HBI0217B/AN305/f760r0p0.bit b/SITE2/HBI0217B/AN305/f760r0p0.bit
new file mode 100644
index 0000000..f731593
--- /dev/null
+++ b/SITE2/HBI0217B/AN305/f760r0p0.bit
Binary files differ
diff --git a/SITE2/HBI0217B/AN305/f760r0p0.txt b/SITE2/HBI0217B/AN305/f760r0p0.txt
new file mode 100644
index 0000000..6375264
--- /dev/null
+++ b/SITE2/HBI0217B/AN305/f760r0p0.txt
@@ -0,0 +1,16 @@
+BOARD: HBI0217
+TITLE: AN305
+
+[FPGAS]
+TOTALFPGAS: 1 ;Total Number of FPGAS (Max:8)
+F0FILE: f760r0p0.bit ;FPGA0 Filename
+F0MODE: FPGA_PCM ;FPGA0 Programming Mode
+
+[VOLTAGES]
+TOTALVOLTAGES: 1 ;Total Number of VOLTAGES to set (Max:4)
+VOLT0: 1.8 ;VIO_UP maximum voltage (0.8 to 2.5)
+
+[SCC REGISTERS]
+TOTALSCCS: 2 ;Total Number of SCC registers defined
+SCC: 0x000 0x01234567 ;SCC gereral read/write regsiter address/value
+SCC: 0x004 0x89ABCDEF ;SCC gereral read/write register address/value
diff --git a/SITE2/HBI0217B/board.txt b/SITE2/HBI0217B/board.txt
index 332f2e7..3a3baf6 100644
--- a/SITE2/HBI0217B/board.txt
+++ b/SITE2/HBI0217B/board.txt
@@ -3,12 +3,16 @@ TITLE: V2F 2XV6 FPGA
[APPLICATION NOTE]
TOTALAPP: 2 ;Total Number of Application notes (Max:8)
-A0FILE: AN233\f550r0p1.txt ;Application note board file for XC6VLX550T
-A1FILE: AN233\f760r0p1.txt ;Application note board file for XC6VLX760
+A0FILE: ANxxx\axxxrxpx.txt ;Please select the required application note
+A1FILE: ANxxx\axxxrxpx.txt ;
+;A0FILE: AN233\f550r0p1.txt ;Application note board file for XC6VLX550T
+;A1FILE: AN233\f760r0p1.txt ;Application note board file for XC6VLX760
+;A0FILE: AN305\f550r0p0.txt ;Application note board file for XC6VLX550T
+;A1FILE: AN305\f760r0p0.txt ;Application note board file for XC6VLX760
[DCC]
TOTALDCC: 2 ;Total Number of DCC (Max:8)
-M0FILE: dbb_v112.ebf ;Filename for XC6VLX240T DCC
+M0FILE: dbb_v115.ebf ;Filename for XC6VLX550T DCC
M0MODE: MICRO ;Programming Mode
-M1FILE: dbb_v213.ebf ;Filename for XC6VLX760 DCC
+M1FILE: dbb_v215.ebf ;Filename for XC6VLX760 DCC
M1MODE: MICRO ;Programming Mode
diff --git a/SITE2/HBI0217B/board_1.txt b/SITE2/HBI0217B/board_1.txt
index 5dc2aaa..b916c22 100644
--- a/SITE2/HBI0217B/board_1.txt
+++ b/SITE2/HBI0217B/board_1.txt
@@ -3,12 +3,12 @@ TITLE: V2F 2XV6 FPGA
[APPLICATION NOTE]
TOTALAPP: 2 ;Total Number of Application notes (Max:8)
-A0FILE: AN233\f550r0p1.txt ;Application note board file for XC6VLX550T
-A1FILE: AN233\f760r0p1.txt ;Application note board file for XC6VLX760
+A0FILE: ANxxx\axxxrxpx.txt ;Please specify the required application note
+A1FILE: ANxxx\axxxrxpx.txt ;
[DCC]
TOTALDCC: 2 ;Total Number of DCC (Max:8)
-M0FILE: dbb_v112.ebf ;Filename for XC6VLX240T DCC
+M0FILE: dbb_v115.ebf ;Filename for XC6VLX550T DCC
M0MODE: MICRO ;Programming Mode
-M1FILE: dbb_v213.ebf ;Filename for XC6VLX760 DCC
+M1FILE: dbb_v215.ebf ;Filename for XC6VLX760 DCC
M1MODE: MICRO ;Programming Mode
diff --git a/SITE2/HBI0217B/dbb_v112.ebf b/SITE2/HBI0217B/dbb_v112.ebf
deleted file mode 100644
index 2dbe31a..0000000
--- a/SITE2/HBI0217B/dbb_v112.ebf
+++ /dev/null
Binary files differ
diff --git a/SITE2/HBI0217B/dbb_v115.ebf b/SITE2/HBI0217B/dbb_v115.ebf
new file mode 100644
index 0000000..77b4ed1
--- /dev/null
+++ b/SITE2/HBI0217B/dbb_v115.ebf
Binary files differ
diff --git a/SITE2/HBI0217B/dbb_v213.ebf b/SITE2/HBI0217B/dbb_v213.ebf
deleted file mode 100644
index 77862b6..0000000
--- a/SITE2/HBI0217B/dbb_v213.ebf
+++ /dev/null
Binary files differ
diff --git a/SITE2/HBI0217B/dbb_v215.ebf b/SITE2/HBI0217B/dbb_v215.ebf
new file mode 100644
index 0000000..53f4a0f
--- /dev/null
+++ b/SITE2/HBI0217B/dbb_v215.ebf
Binary files differ
diff --git a/SITE2/HBI0247B/AN307/a307r0p0.bit b/SITE2/HBI0247B/AN307/a307r0p0.bit
new file mode 100644
index 0000000..186908d
--- /dev/null
+++ b/SITE2/HBI0247B/AN307/a307r0p0.bit
Binary files differ
diff --git a/SITE2/HBI0247B/AN307/a307r0p0.txt b/SITE2/HBI0247B/AN307/a307r0p0.txt
new file mode 100644
index 0000000..356838e
--- /dev/null
+++ b/SITE2/HBI0247B/AN307/a307r0p0.txt
@@ -0,0 +1,27 @@
+BOARD: HBI0247
+TITLE: AN307
+
+[FPGAS]
+TOTALFPGAS: 1 ;Total Number of FPGAS (Max:8)
+F0FILE: a307r0p0.bit ;FPGA0 Filename
+;F0MODE: FPGA_STREAM ;FPGA0 Programming Mode
+F0MODE: FPGA ;FPGA0 Programming Mode
+
+[VOLTAGES]
+TOTALVOLTAGES: 1 ;Total Number of VOLTAGES to set (Max:4)
+VOLT0: 1.8 ;VIO_UP maximum voltage (0.8 to 2.5)
+
+[OSCCLKS]
+TOTALOSCCLKS: 7 ;Total Number of OSCCLKS (Max:8)
+OSC0: 80.0 ;OSC0 Frequency in MHz (ACLK, MCLK, MCLK_90)
+OSC1: 23.75 ;OSC1 Frequency in MHz (CLCD)
+OSC2: 24.0 ;OSC2 Frequency in MHz (for 1Hz clk)
+OSC3: 30.0 ;OSC3 Frequency in MHz (ExtS ACLK)
+OSC4: 50.0 ;OSC4 Frequency in MHz (SMB)
+OSC5: 70.0 ;OSC5 Frequency in MHz (Not used)
+OSC6: 100.0 ;OSC6 Frequency in MHz (DDR) must be 100.0 or 200.0
+
+[SCC REGISTERS]
+TOTALSCCS: 2 ;Total Number of SCC registers defined
+SCC: 0x000 0x01234567 ;SCC gereral read/write regsiter address/value
+SCC: 0x004 0x89ABCDEF ;SCC gereral read/write register address/value
diff --git a/SITE2/HBI0247B/board.txt b/SITE2/HBI0247B/board.txt
new file mode 100644
index 0000000..c63f74f
--- /dev/null
+++ b/SITE2/HBI0247B/board.txt
@@ -0,0 +1,13 @@
+BOARD: HBI0247
+TITLE: FPGA V2F-1XV7
+
+[APPLICATION NOTE]
+TOTALAPP: 1 ;Total Number of Application notes (Max:8)
+APPNOTE: ANxxx\axxxrxpx.txt ;Please select the required application note
+;APPNOTE: AN306\a306r0p0.txt
+;APPNOTE: AN307\a307r0p0.txt
+
+[DCCS]
+TOTALDCCS: 1 ;Total Number of DCCS (Max:8)
+M0FILE: dbb_v108.ebf ;DCC0 Filename
+M0MODE: MICRO ;DCC0 Programming Mode
diff --git a/SITE2/HBI0247B/board_1.txt b/SITE2/HBI0247B/board_1.txt
new file mode 100644
index 0000000..1f927ca
--- /dev/null
+++ b/SITE2/HBI0247B/board_1.txt
@@ -0,0 +1,11 @@
+BOARD: HBI0247
+TITLE: FPGA V2F-1XV7
+
+[APPLICATION NOTE]
+TOTALAPP: 1 ;Total Number of Application notes (Max:8)
+APPNOTE: ANxxx\axxxrxpx.txt ;Please specify the required application note
+
+[DCCS]
+TOTALDCCS: 1 ;Total Number of DCCS (Max:8)
+M0FILE: dbb_v108.ebf ;DCC0 Filename
+M0MODE: MICRO ;DCC0 Programming Mode
diff --git a/SITE2/HBI0247B/dbb_v108.ebf b/SITE2/HBI0247B/dbb_v108.ebf
new file mode 100644
index 0000000..06ed963
--- /dev/null
+++ b/SITE2/HBI0247B/dbb_v108.ebf
Binary files differ
diff --git a/SITE2/HBI0247C/AN307/a307r0p0.bit b/SITE2/HBI0247C/AN307/a307r0p0.bit
new file mode 100644
index 0000000..186908d
--- /dev/null
+++ b/SITE2/HBI0247C/AN307/a307r0p0.bit
Binary files differ
diff --git a/SITE2/HBI0247C/AN307/a307r0p0.txt b/SITE2/HBI0247C/AN307/a307r0p0.txt
new file mode 100644
index 0000000..356838e
--- /dev/null
+++ b/SITE2/HBI0247C/AN307/a307r0p0.txt
@@ -0,0 +1,27 @@
+BOARD: HBI0247
+TITLE: AN307
+
+[FPGAS]
+TOTALFPGAS: 1 ;Total Number of FPGAS (Max:8)
+F0FILE: a307r0p0.bit ;FPGA0 Filename
+;F0MODE: FPGA_STREAM ;FPGA0 Programming Mode
+F0MODE: FPGA ;FPGA0 Programming Mode
+
+[VOLTAGES]
+TOTALVOLTAGES: 1 ;Total Number of VOLTAGES to set (Max:4)
+VOLT0: 1.8 ;VIO_UP maximum voltage (0.8 to 2.5)
+
+[OSCCLKS]
+TOTALOSCCLKS: 7 ;Total Number of OSCCLKS (Max:8)
+OSC0: 80.0 ;OSC0 Frequency in MHz (ACLK, MCLK, MCLK_90)
+OSC1: 23.75 ;OSC1 Frequency in MHz (CLCD)
+OSC2: 24.0 ;OSC2 Frequency in MHz (for 1Hz clk)
+OSC3: 30.0 ;OSC3 Frequency in MHz (ExtS ACLK)
+OSC4: 50.0 ;OSC4 Frequency in MHz (SMB)
+OSC5: 70.0 ;OSC5 Frequency in MHz (Not used)
+OSC6: 100.0 ;OSC6 Frequency in MHz (DDR) must be 100.0 or 200.0
+
+[SCC REGISTERS]
+TOTALSCCS: 2 ;Total Number of SCC registers defined
+SCC: 0x000 0x01234567 ;SCC gereral read/write regsiter address/value
+SCC: 0x004 0x89ABCDEF ;SCC gereral read/write register address/value
diff --git a/SITE2/HBI0247C/board.txt b/SITE2/HBI0247C/board.txt
new file mode 100644
index 0000000..c63f74f
--- /dev/null
+++ b/SITE2/HBI0247C/board.txt
@@ -0,0 +1,13 @@
+BOARD: HBI0247
+TITLE: FPGA V2F-1XV7
+
+[APPLICATION NOTE]
+TOTALAPP: 1 ;Total Number of Application notes (Max:8)
+APPNOTE: ANxxx\axxxrxpx.txt ;Please select the required application note
+;APPNOTE: AN306\a306r0p0.txt
+;APPNOTE: AN307\a307r0p0.txt
+
+[DCCS]
+TOTALDCCS: 1 ;Total Number of DCCS (Max:8)
+M0FILE: dbb_v108.ebf ;DCC0 Filename
+M0MODE: MICRO ;DCC0 Programming Mode
diff --git a/SITE2/HBI0247C/board_1.txt b/SITE2/HBI0247C/board_1.txt
new file mode 100644
index 0000000..1f927ca
--- /dev/null
+++ b/SITE2/HBI0247C/board_1.txt
@@ -0,0 +1,11 @@
+BOARD: HBI0247
+TITLE: FPGA V2F-1XV7
+
+[APPLICATION NOTE]
+TOTALAPP: 1 ;Total Number of Application notes (Max:8)
+APPNOTE: ANxxx\axxxrxpx.txt ;Please specify the required application note
+
+[DCCS]
+TOTALDCCS: 1 ;Total Number of DCCS (Max:8)
+M0FILE: dbb_v108.ebf ;DCC0 Filename
+M0MODE: MICRO ;DCC0 Programming Mode
diff --git a/SITE2/HBI0247C/dbb_v108.ebf b/SITE2/HBI0247C/dbb_v108.ebf
new file mode 100644
index 0000000..06ed963
--- /dev/null
+++ b/SITE2/HBI0247C/dbb_v108.ebf
Binary files differ
diff --git a/SOFTWARE/bm_v500l.axf b/SOFTWARE/bm_v500l.axf
deleted file mode 100644
index fc58e1b..0000000
--- a/SOFTWARE/bm_v500l.axf
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/bm_v500r.axf b/SOFTWARE/bm_v500r.axf
deleted file mode 100644
index 00068d1..0000000
--- a/SOFTWARE/bm_v500r.axf
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/bm_v517l.axf b/SOFTWARE/bm_v517l.axf
new file mode 100644
index 0000000..3b9a647
--- /dev/null
+++ b/SOFTWARE/bm_v517l.axf
Binary files differ
diff --git a/SOFTWARE/bm_v519r.axf b/SOFTWARE/bm_v519r.axf
new file mode 100644
index 0000000..8956ab1
--- /dev/null
+++ b/SOFTWARE/bm_v519r.axf
Binary files differ
diff --git a/SOFTWARE/booscr15.txt b/SOFTWARE/booscr15.txt
index 997b62e..cce1fc0 100644
--- a/SOFTWARE/booscr15.txt
+++ b/SOFTWARE/booscr15.txt
@@ -1 +1,2 @@
-flash linux kernel15
+flash linux fdt ca15a7
+flash linux boot kernel root=/dev/sda2 rw rootwait console=ttyAMA0,38400
diff --git a/SOFTWARE/booscr5s.txt b/SOFTWARE/booscr5s.txt
new file mode 100644
index 0000000..127e5dd
--- /dev/null
+++ b/SOFTWARE/booscr5s.txt
@@ -0,0 +1,2 @@
+flash linux fdt ca5s
+flash linux boot kernel root=/dev/sda2 rw rootwait console=ttyAMA0,38400
diff --git a/SOFTWARE/booscr9.txt b/SOFTWARE/booscr9.txt
new file mode 100644
index 0000000..d8a8182
--- /dev/null
+++ b/SOFTWARE/booscr9.txt
@@ -0,0 +1 @@
+fl linux boot kernel console=ttyAMA0,38400 root=/dev/sda2 rw rootwait
diff --git a/SOFTWARE/booscr_l.txt b/SOFTWARE/booscr_l.txt
deleted file mode 100644
index 8f8aae3..0000000
--- a/SOFTWARE/booscr_l.txt
+++ /dev/null
@@ -1 +0,0 @@
-fl linux kernel_l root=/dev/sda1 ro console=ttyAMA0 mem=1024M ip=dhcp clcd=xvga rootwait
diff --git a/SOFTWARE/booscr_r.txt b/SOFTWARE/booscr_r.txt
deleted file mode 100644
index 4ee201d..0000000
--- a/SOFTWARE/booscr_r.txt
+++ /dev/null
@@ -1 +0,0 @@
-fl linux kernel_r root=/dev/sda1 ro console=ttyAMA0 mem=1024M ip=dhcp rootwait
diff --git a/SOFTWARE/ca15a7.dtb b/SOFTWARE/ca15a7.dtb
new file mode 100644
index 0000000..8133a21
--- /dev/null
+++ b/SOFTWARE/ca15a7.dtb
Binary files differ
diff --git a/SOFTWARE/ca5s.dtb b/SOFTWARE/ca5s.dtb
new file mode 100644
index 0000000..9b8a6a8
--- /dev/null
+++ b/SOFTWARE/ca5s.dtb
Binary files differ
diff --git a/SOFTWARE/cramfs.bin b/SOFTWARE/cramfs.bin
deleted file mode 100644
index 201fe14..0000000
--- a/SOFTWARE/cramfs.bin
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/deb_i_l.bin b/SOFTWARE/deb_i_l.bin
deleted file mode 100644
index 25e7435..0000000
--- a/SOFTWARE/deb_i_l.bin
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/deb_i_r.bin b/SOFTWARE/deb_i_r.bin
deleted file mode 100644
index 34ab587..0000000
--- a/SOFTWARE/deb_i_r.bin
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/kernel.bin b/SOFTWARE/kernel.bin
new file mode 100644
index 0000000..e011e70
--- /dev/null
+++ b/SOFTWARE/kernel.bin
Binary files differ
diff --git a/SOFTWARE/kernel15.bin b/SOFTWARE/kernel15.bin
deleted file mode 100644
index 2e35ba3..0000000
--- a/SOFTWARE/kernel15.bin
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/kernel_l.bin b/SOFTWARE/kernel_l.bin
deleted file mode 100644
index 2a20c03..0000000
--- a/SOFTWARE/kernel_l.bin
+++ /dev/null
Binary files differ
diff --git a/SOFTWARE/kernel_r.bin b/SOFTWARE/kernel_r.bin
deleted file mode 100644
index 19b445e..0000000
--- a/SOFTWARE/kernel_r.bin
+++ /dev/null
Binary files differ
diff --git a/readme.txt b/readme.txt
new file mode 100644
index 0000000..9569a32
--- /dev/null
+++ b/readme.txt
@@ -0,0 +1,161 @@
+This patch to Versatile Express DVD version 5.0 provides
+an updated Boot Monitor as well as updated DCC firmware
+for the CoreTile Express A15x2 A7x3 (V2P-CA15-A7) processor
+board.
+
+The updates are mandatory to be able to use the unified power
+management support for the big.LITTLE MP & CPU migration mode
+of operation in the Linaro Linux kernel. These changes will be
+introduced in version 13.01 of the kernel.
+
+The patch contains the following files:
+
+bm_v519r.axf - Boot Monitor
+dbb_v110.ebf - DCC firmware
+readme.txt - the text file you are reading now
+
+------------
+DCC Firmware
+------------
+
+This release of the DCC firmware is not compatible with pre-13.01
+kernels (i.e. existing releases of the Linaro Linux kernel).
+However, the previous version of the DCC firmware (dbb_v107.ebf)
+and pre-13.01 releases of the kernel may be used with this release
+of the Boot Monitor as mentioned below.
+
+------------
+Boot Monitor
+------------
+
+1. Compatibility with Linaro Linux kernel releases.
+
+ Power management support for the TC2 coretile has been reworked for the
+ 13.01 kernel release. Broadly, this means that per-cpu mailbox registers
+ are used to a) bringup secondary cpus during smp bringup & b) implement
+ warm resets. Linux kernel releases prior to 13.01 used the sys_flags
+ registers (part of the versatile express motherboard memory map) to do
+ the same.
+
+ The Bootmon firmware is compatible with both 13.01 and the releases
+ preceding it. Comptability with pre 13.01 Linaro Linux kernels is
+ referred to as 'backward compatibility'. The mode of operation of
+ bootmon can be configured by manipulating bit[12] in the SCC register
+ offset 0x700 (SCC System Information Register) in the board.txt file.
+
+ a. bit[12]=1: Bootmon is compatible with the 13.01 release of the
+ Linaro linux kernel. It uses per-cpu mailboxes to
+ implement warm resets & for secondary cpu bringup.
+
+ b. bit[12]=0: Bootmon is compatible with pre 13.01 releases of the
+ Linaro linux kernel. It uses sys_flags register to
+ implement warm resets for secondary cpu bringup.
+
+ This bit should be set to 0 if power management support
+ has been disabled in the Linux kernel configuration.
+
+ To summarize, the following combinations of the firmware and the
+ linux kernel are expected to be compatible:
+
+ a. dbb_v107.ebf (dcc fw) + bm_v519r.axf (bootmon fw) + pre-13.01
+ release of the Linaro linux kernel + board.txt which has bit[12]
+ of SCC register offset 0x700 unset.
+
+ b. dbb_v110.ebf (dcc fw) + bm_v519r.axf (bootmon fw) + 13.01 release
+ of the Linaro linux kernel + board.txt which has bit[12] of SCC
+ register offset 0x700 set.
+
+2. Support for TC2 coretile event propagation errata
+
+ The TC2 coretile has a bug in the implementation of the logic
+ that's responsible for delivering events (e.g. generated by the
+ 'sev' instruction) across the A15 and A7 clusters. Inter-cluster
+ events can be lost if the two clusters are operating at certain
+ OPP (operating point) combinations. This can cause a CPU to wait
+ for an event ('wfe' instruction) indefinitely e.g. while trying to
+ acquire a spin lock in the linux kernel.
+
+ Bootmon can be configured to work around this issue. This is done
+ by generating a periodic event stream (every 32K cycles) on each CPU
+ to make up for any lost events. Configuration is done by manipulating
+ the following bits of the SCC register offset 0x700 (SCC System
+ information register) in the board.txt as follows:
+
+ a. bit[14]=1: Each A15 cpu generates an event stream every 32K cycles.
+
+ b. bit[14]=0: Event stream generation is not configured on the A15 cpus.
+
+ c. bit[15]=1: Each A7 cpu generates an event stream every 32K cycles.
+
+ f. bit[15]=0: Event stream generation is not configured on the A7 cpus.
+
+ Setting both the bits in the SCC register is expected to provide a reliable
+ workaround of the errata.
+
+3. Support for powering down the non-boot cluster.
+
+ To save power it might be desirable to keep the non-boot cluster powered
+ down till the operating system (Linux) does not explicitly bringup cpus
+ in that cluster either as a part of smp bringup or through a hotplug request.
+
+ Bootmon can be configured to power down the non-boot cluster by manipulating
+ the SCC register offset 0x700 (SCC System information register) in the
+ board.txt as follows:
+
+ a. bit[13]=1: Bootmon powers down the non-boot cluster.
+
+ b. bit[13]=0: Bootmon does not power down the non-boot cluster.
+
+
+------------
+Installation
+------------
+
+There is no automatic installation method for this patch.
+To install the patch you must manually copy the files on
+to the Micro-SD card of your Versatile Express motherboard,
+and then update the relevant image.txt and board.txt files
+so that they point to the updated firmware and Boot Monitor.
+
+Proceed as follows:
+
+1) copy bm_v519r.axf to the motherboard in this location:
+
+ \SOFTWARE\bm_v519r.axf
+
+
+2) copy dbb_v110.ebf to the motherboard in this location:
+
+ \SITE1\HBI0249A\dbb_v110.ebf
+
+
+3) edit the file on the motherboard:
+
+ \SITE1\HBI0249A\board.txt
+
+ to change the line:
+
+ M0FILE: dbb_v107.ebf ;DCC0 Filename
+
+ so that it becomes:
+
+ M0FILE: dbb_v110.ebf ;DCC0 Filename
+
+
+4) edit the file on the motherboard:
+
+ \SITE1\HBI0249A\images.txt
+
+ to change the line:
+
+ NOR0FILE: \SOFTWARE\bm_v517r.axf ;Image File Name
+
+ so that it becomes:
+
+ NOR0FILE: \SOFTWARE\bm_v519r.axf ;Image File Name
+
+
+It is possible that additional changes to these text
+files will be needed - please see the instructions that
+come with the Linaro kernel for details of any further
+changes that are necessary.