diff options
Diffstat (limited to 'ArmPkg/Drivers/AcpiTables/rtsm_ve-aemv8a/Facp.aslc')
-rw-r--r-- | ArmPkg/Drivers/AcpiTables/rtsm_ve-aemv8a/Facp.aslc | 175 |
1 files changed, 175 insertions, 0 deletions
diff --git a/ArmPkg/Drivers/AcpiTables/rtsm_ve-aemv8a/Facp.aslc b/ArmPkg/Drivers/AcpiTables/rtsm_ve-aemv8a/Facp.aslc new file mode 100644 index 000000000..729c5bc38 --- /dev/null +++ b/ArmPkg/Drivers/AcpiTables/rtsm_ve-aemv8a/Facp.aslc @@ -0,0 +1,175 @@ +/** @file + FACP Table + + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org +*/ + +#include "Platform.h" + +EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Facp = { + { + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // to make sum of entire table == 0 + {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + 0x00, // OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0, // Physical addesss of FACS + 0x00000010, // Physical address of DSDT + 0x0, // System Interrupt Model + 0x4, // PM Profile + SCI_INT_VECTOR, // System vector of SCI interrupt + SMI_CMD_IO_PORT, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + 0, // PState control + PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk + PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk + GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk + GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // offset in gpe model where gpe1 events start + 0, // _CST support + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM + CENTURY, // index to century in RTC CMOS RAM + 0x0000, // Boot architecture flag + 0x00, // reserved + FLAG, + + { + 0x01, //Space ID + 0x8, //Bit Width + 0x0, //Bit Offset + 0x1, //Encoded Access Width + 0x0000000000000001,//Address + }, + + 0x0, //Value to cause reset + {0,0,0}, //Reserved + 0x0000000000000000,//FACS Address + 0x0000000000000010,//DSDT Address + + + /*PM1A Event Block*/ + 0x1, //Space ID:SystemIO + 0x20, //Bit Width + 0x0, //Bit Offset + 0x2, //Encoded Access Width + 0x0000000000000001, //Address + + /*PM1B Event Block*/ + 0x1, //Space ID:SystemIO + 0x0, //Bit Width + 0x0, //Bit Offset + 0x0, //Encoded Access Width + 0x0000000000000000, //Address + + /*PM1A Control Block*/ + 0x1, //Space ID:SystemIO + 0x10, //Bit Width + 0x0, //Bit Offset + 0x02, //Encoded Access Width + 0000000000000001, //Address + + /*PM1B Control Block*/ + 0x1, //Space ID:SystemIO + 0x00, //Bit Width + 0x0, //Bit Offset + 0x0, //Encoded Access Width + 0x0000000000000000, //Address + + /*PM2 Control Block*/ + 0x1, //Space ID:SystemIO + 0x08, //Bit Width + 0x0, //Bit Offset + 0x0, //Encoded Access Width + 0x0000000000000001, //Address + + /*PM Timer Block*/ + 0x1, //Space ID:SystemIO + 0x20, //Bit Width + 0x0, //Bit Offset + 0x3, //Encoded Access Width + 0x0000000000000001, //Address + + /*GPE0 Block*/ + 0x1, //Space ID:SystemIO + 0x80, //Bit Width + 0x0, //Bit Offset + 0x1, //Encoded Access Width + 0x0000000000000001, //Address + + /*GPE1 Block*/ + 0x1, //Space ID:SystemIO + 0x00, //Bit Width + 0x0, //Bit Offset + 0x0, //Encoded Access Width + 0x0000000000000000, //Address + + /*Sleep Control Register*/ + 0x1, //Space ID:SystemIO + 0x08, //Bit Width + 0x0, //Bit Offset + 0x1, //Encoded Access Width + 0x0000000000000000, //Address + + /*Sleep Status Register*/ + 0x1, //Space ID:SystemIO + 0x08, //Bit Width + 0x0, //Bit Offset + 0x1, //Encoded Access Width + 0x0000000000000000, //Address + +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Facp; +} |