diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2012-10-22 08:35:15 +0100 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2014-01-24 15:44:22 +0000 |
| commit | 3f7bd720462204fb9a5fa5bf64a42da4b58f1d9a (patch) | |
| tree | 3ce3f8d1ee97c344561f8cf9c2409d8179e2896d | |
| parent | 4f02edd1eddc35fabf7afe1b703c52dec64d0d3f (diff) | |
TC1: set refresh period
This patch fixes TC1 instablility. Setting the DRAM refresh period seems to be the cure.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
| -rw-r--r-- | ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S index 2bd678be9..d865d6701 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S @@ -158,6 +158,13 @@ smc_init2: LDR r1, = 0x03C00000 STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + // Set refresh period + LDR r1, = 0x1 + STR r1, [r0, #0x20] + + LDR r1, = 0x1 + STR r1, [r0, #0x24] + // page mode setup for VRAM LDR r0, = 0x00FFFFFC ADD r0, r0, r2 |