diff options
| author | Steven Kinney <steven.kinney@linaro.org> | 2013-10-02 16:34:29 -0500 |
|---|---|---|
| committer | Steven Kinney <steven.kinney@linaro.org> | 2013-10-02 16:34:29 -0500 |
| commit | 5ccbbee4cc6fe42e4f344bdc29b1c188186a5dca (patch) | |
| tree | cd6e3b4e7274b14f9eaf04b9cfe4b452c7beb446 | |
| parent | 9af4254e1dc5b354820b31c9bcc69c8a08f15dd6 (diff) | |
| parent | 8baab609fd1d00543af012a5a01479d34dbe04fd (diff) | |
Merge branch 'linaro-topic-panda' into x-integ
108 files changed, 14943 insertions, 0 deletions
diff --git a/Omap44xxPkg/Gpio/Gpio.c b/Omap44xxPkg/Gpio/Gpio.c new file mode 100644 index 000000000..282722268 --- /dev/null +++ b/Omap44xxPkg/Gpio/Gpio.c @@ -0,0 +1,135 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> + +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/EmbeddedGpio.h> + +#include <Omap4430/Omap4430.h> + +EFI_STATUS +Get ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT UINTN *Value + ) +{ + UINTN Port; + UINTN Pin; + UINT32 DataInRegister; + + if (Value == NULL) + { + return EFI_UNSUPPORTED; + } + + Port = GPIO_PORT(Gpio); + Pin = GPIO_PIN(Gpio); + + DataInRegister = GpioBase(Port) + GPIO_DATAIN; + + if (MmioRead32 (DataInRegister) & GPIO_DATAIN_MASK(Pin)) { + *Value = 1; + } else { + *Value = 0; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +Set ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_MODE Mode + ) +{ + UINTN Port; + UINTN Pin; + UINT32 OutputEnableRegister; + UINT32 SetDataOutRegister; + UINT32 ClearDataOutRegister; + + Port = GPIO_PORT(Gpio); + Pin = GPIO_PIN(Gpio); + + OutputEnableRegister = GpioBase(Port) + GPIO_OE; + SetDataOutRegister = GpioBase(Port) + GPIO_SETDATAOUT; + ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT; + + switch (Mode) + { + case GPIO_MODE_INPUT: + MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin)); + break; + + case GPIO_MODE_OUTPUT_0: + MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin)); + MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin)); + break; + + case GPIO_MODE_OUTPUT_1: + MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin)); + MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin)); + break; + + default: + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +GetMode ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT EMBEDDED_GPIO_MODE *Mode + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +SetPull ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_PULL Direction + ) +{ + return EFI_UNSUPPORTED; +} + +EMBEDDED_GPIO Gpio = { + Get, + Set, + GetMode, + SetPull +}; + +EFI_STATUS +GpioInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL); + return Status; +} diff --git a/Omap44xxPkg/Gpio/Gpio.inf b/Omap44xxPkg/Gpio/Gpio.inf new file mode 100644 index 000000000..89ab02167 --- /dev/null +++ b/Omap44xxPkg/Gpio/Gpio.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Gpio + FILE_GUID = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = GpioInitialize + + +[Sources.common] + Gpio.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + IoLib + UefiDriverEntryPoint + OmapLib + +[Guids] + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Pcd] + +[depex] + TRUE
\ No newline at end of file diff --git a/Omap44xxPkg/Include/Library/OmapDmaLib.h b/Omap44xxPkg/Include/Library/OmapDmaLib.h new file mode 100755 index 000000000..9d81d5049 --- /dev/null +++ b/Omap44xxPkg/Include/Library/OmapDmaLib.h @@ -0,0 +1,90 @@ +/** @file + + Abstractions for simple OMAP DMA. + OMAP_DMA4 structure elements are described in the OMAP44xx TRM. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP_DMA_LIB_H__ +#define __OMAP_DMA_LIB_H__ + + +// Example from DMA chapter of the OMAP44xx spec +typedef struct { + UINT8 DataType; // DMA4_CSDPi[1:0] + UINT8 ReadPortAccessType; // DMA4_CSDPi[8:7] + UINT8 WritePortAccessType; // DMA4_CSDPi[15:14] + UINT8 SourceEndiansim; // DMA4_CSDPi[21] + UINT8 DestinationEndianism; // DMA4_CSDPi[19] + UINT8 WriteMode; // DMA4_CSDPi[17:16] + UINT8 SourcePacked; // DMA4_CSDPi[6] + UINT8 DestinationPacked; // DMA4_CSDPi[13] + UINT32 NumberOfElementPerFrame; // DMA4_CENi + UINT32 NumberOfFramePerTransferBlock; // DMA4_CFNi + UINT32 SourceStartAddress; // DMA4_CSSAi + UINT32 DestinationStartAddress; // DMA4_CDSAi + UINT32 SourceElementIndex; // DMA4_CSEi + UINT32 SourceFrameIndex; // DMA4_CSFi + UINT32 DestinationElementIndex; // DMA4_CDEi + UINT32 DestinationFrameIndex; // DMA4_CDFi + UINT8 ReadPortAccessMode; // DMA4_CCRi[13:12] + UINT8 WritePortAccessMode; // DMA4_CCRi[15:14] + UINT8 ReadPriority; // DMA4_CCRi[6] + UINT8 WritePriority; // DMA4_CCRi[23] + UINT8 ReadRequestNumber; // DMA4_CCRi[4:0] + UINT8 WriteRequestNumber; // DMA4_CCRi[20:19] +} OMAP_DMA4; + + +/** + Configure OMAP DMA Channel + + @param Channel DMA Channel to configure + @param Dma4 Pointer to structure used to initialize DMA registers for the Channel + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +EnableDmaChannel ( + IN UINTN Channel, + IN OMAP_DMA4 *Dma4 + ); + +/** + Turn of DMA channel configured by EnableDma(). + + @param Channel DMA Channel to configure + @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS + @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR + + @retval EFI_SUCCESS DMA hardware disabled + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +DisableDmaChannel ( + IN UINTN Channel, + IN UINT32 SuccessMask, + IN UINT32 ErrorMask + ); + + + +#endif + diff --git a/Omap44xxPkg/Include/Library/OmapLib.h b/Omap44xxPkg/Include/Library/OmapLib.h new file mode 100644 index 000000000..419227515 --- /dev/null +++ b/Omap44xxPkg/Include/Library/OmapLib.h @@ -0,0 +1,44 @@ +/** @file + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAPLIB_H__ +#define __OMAPLIB_H__ + +UINT32 +EFIAPI +GpioBase ( + IN UINTN Port + ); + +UINT32 +EFIAPI +TimerBase ( + IN UINTN Timer + ); + +UINTN +EFIAPI +InterruptVectorForTimer ( + IN UINTN TImer + ); + +UINT32 +EFIAPI +UartBase ( + IN UINTN Uart + ); + + +#endif // __OMAPLIB_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430.h b/Omap44xxPkg/Include/Omap4430/Omap4430.h new file mode 100644 index 000000000..f59eec4dc --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430.h @@ -0,0 +1,31 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430_H__ +#define __OMAP4430_H__ + +#include "Omap4430Gpio.h" +#include "Omap4430Interrupt.h" +#include "Omap4430Prcm.h" +#include "Omap4430Timer.h" +#include "Omap4430Uart.h" +#include "Omap4430Usb.h" +#include "Omap4430MMCHS.h" +#include "Omap4430I2c.h" +#include "Omap4430PadConfiguration.h" +#include "Omap4430Gpmc.h" +#include "Omap4430Dma.h" + +#endif // __OMAP4430_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Dma.h b/Omap44xxPkg/Include/Omap4430/Omap4430Dma.h new file mode 100755 index 000000000..cf27e2719 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Dma.h @@ -0,0 +1,130 @@ +/** @file + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430DMA_H__ +#define __OMAP4430DMA_H__ + + +#define DMA4_MAX_CHANNEL 31 + +#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i))) + +#define DMA4_CCR(_i) (0x48056080 + (0x60*(_i))) +#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i))) +#define DMA4_CSR(_i) (0x4805608c + (0x60*(_i))) +#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i))) +#define DMA4_CEN(_i) (0x48056094 + (0x60*(_i))) +#define DMA4_CFN(_i) (0x48056098 + (0x60*(_i))) +#define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i))) +#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i))) +#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i))) +#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i))) +#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i))) +#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i))) + +#define DMA4_GCR (0x48056078) + +// Channel Source Destination parameters +#define DMA4_CSDP_DATA_TYPE8 0 +#define DMA4_CSDP_DATA_TYPE16 1 +#define DMA4_CSDP_DATA_TYPE32 2 + +#define DMA4_CSDP_SRC_PACKED BIT6 +#define DMA4_CSDP_SRC_NONPACKED 0 + +#define DMA4_CSDP_SRC_BURST_EN (0x0 << 7) +#define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7) +#define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7) +#define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7) + +#define DMA4_CSDP_DST_PACKED BIT13 +#define DMA4_CSDP_DST_NONPACKED 0 + +#define DMA4_CSDP_BURST_EN (0x0 << 14) +#define DMA4_CSDP_BURST_EN16 (0x1 << 14) +#define DMA4_CSDP_BURST_EN32 (0x2 << 14) +#define DMA4_CSDP_BURST_EN64 (0x3 << 14) + +#define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16) +#define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16) +#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16) + +#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18 +#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0 + +#define DMA4_CSDP_DST_ENDIAN_BIG BIT19 +#define DMA4_CSDP_DST_ENDIAN_LITTLE 0 + +#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20 +#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0 + +#define DMA4_CSDP_SRC_ENDIAN_BIG BIT21 +#define DMA4_CSDP_SRC_ENDIAN_LITTLE 0 + +// Channel Control +#define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f + +#define DMA4_CCR_FS_ELEMENT (0 | 0) +#define DMA4_CCR_FS_BLOCK (0 | BIT18) +#define DMA4_CCR_FS_FRAME (BIT5 | 0) +#define DMA4_CCR_FS_PACKET (BIT5 | BIT18) + +#define DMA4_CCR_READ_PRIORITY_HIGH BIT6 +#define DMA4_CCR_READ_PRIORITY_LOW 0 + +#define DMA4_CCR_ENABLE BIT7 +#define DMA4_CCR_DISABLE 0 + +#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8 +#define DMA4_CCR_SUSPEND_SENSITIVE 0 + +#define DMA4_CCR_RD_ACTIVE BIT9 +#define DMA4_CCR_WR_ACTIVE BIT10 + +#define DMA4_CCR_SRC_AMODE (0 | 0) +#define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12) +#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0) +#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12) + +#define DMA4_CCR_DST_AMODE (0 | 0) +#define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14) +#define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0) +#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14) + +#define DMA4_CCR_CONST_FILL_ENABLE BIT16 +#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17 + +#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24 + +#define DMA4_CSR_DROP BIT1 +#define DMA4_CSR_HALF BIT2 +#define DMA4_CSR_FRAME BIT3 +#define DMA4_CSR_LAST BIT4 +#define DMA4_CSR_BLOCK BIT5 +#define DMA4_CSR_SYNC BIT6 +#define DMA4_CSR_PKT BIT7 +#define DMA4_CSR_TRANS_ERR BIT8 +#define DMA4_CSR_SECURE_ERR BIT9 +#define DMA4_CSR_SUPERVISOR_ERR BIT10 +#define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11 +#define DMA4_CSR_DRAIN_END BIT12 +#define DMA4_CSR_RESET 0x1FE +#define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR) + +// same mapping as CSR except for SYNC. Enable all since we are polling +#define DMA4_CICR_ENABLE_ALL 0x1FBE + + +#endif + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Gpio.h b/Omap44xxPkg/Include/Omap4430/Omap4430Gpio.h new file mode 100644 index 000000000..dcaa74cce --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Gpio.h @@ -0,0 +1,132 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430GPIO_H__ +#define __OMAP4430GPIO_H__ + +#define GPIO1_BASE (0x4A310000) +#define GPIO2_BASE (0x48055000) +#define GPIO3_BASE (0x48057000) +#define GPIO4_BASE (0x48059000) +#define GPIO5_BASE (0x4805B000) +#define GPIO6_BASE (0x4805D000) + +// TODO: review below defines, offsets changed from omap3 to omap4 +#define GPIO_SYSCONFIG (0x0010) +#define GPIO_SYSSTATUS (0x0014) +#define GPIO_IRQSTATUS1 (0x0018) +#define GPIO_IRQENABLE1 (0x001C) +#define GPIO_WAKEUPENABLE (0x0020) +#define GPIO_IRQSTATUS2 (0x0028) +#define GPIO_IRQENABLE2 (0x002C) +#define GPIO_CTRL (0x0030) +#define GPIO_OE (0x0134) +#define GPIO_DATAIN (0x0138) +#define GPIO_DATAOUT (0x003C) +#define GPIO_LEVELDETECT0 (0x0040) +#define GPIO_LEVELDETECT1 (0x0044) +#define GPIO_RISINGDETECT (0x0048) +#define GPIO_FALLINGDETECT (0x004C) +#define GPIO_DEBOUNCENABLE (0x0050) +#define GPIO_DEBOUNCINGTIME (0x0054) +#define GPIO_CLEARIRQENABLE1 (0x0060) +#define GPIO_SETIRQENABLE1 (0x0064) +#define GPIO_CLEARIRQENABLE2 (0x0070) +#define GPIO_SETIRQENABLE2 (0x0074) +#define GPIO_CLEARWKUENA (0x0080) +#define GPIO_SETWKUENA (0x0084) +#define GPIO_CLEARDATAOUT (0x0190) +#define GPIO_SETDATAOUT (0x0194) + +#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3) +#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3) +#define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3 +#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3) +#define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2 +#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2) +#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2 +#define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1 +#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1) +#define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1 +#define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0 +#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0) +#define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0 + +#define GPIO_SYSSTATUS_RESETDONE_MASK BIT0 +#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0) +#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0 + +#define GPIO_IRQSTATUS_MASK(x) (1UL << (x)) +#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x)) +#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x)) +#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x)) + +#define GPIO_IRQENABLE_MASK(x) (1UL << (x)) +#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x)) +#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x)) + +#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x)) +#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x)) +#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x)) + +#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1) +#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1) +#define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1 +#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1) +#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1) +#define GPIO_CTRL_DISABLEMODULE_MASK BIT0 +#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0) +#define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0 + +#define GPIO_OE_MASK(x) (1UL << (x)) +#define GPIO_OE_OUTPUT(x) (0UL << (x)) +#define GPIO_OE_INPUT(x) (1UL << (x)) + +#define GPIO_DATAIN_MASK(x) (1UL << (x)) + +#define GPIO_DATAOUT_MASK(x) (1UL << (x)) + +#define GPIO_LEVELDETECT_MASK(x) (1UL << (x)) +#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x)) +#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x)) + +#define GPIO_RISINGDETECT_MASK(x) (1UL << (x)) +#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x)) +#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x)) + +#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x)) +#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x)) +#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x)) + +#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x)) +#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x)) +#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x)) + +#define GPIO_DEBOUNCINGTIME_MASK (0xFF) +#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK) + +#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x)) + +#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x)) + +#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x)) + +#define GPIO_SETWKUENA_BIT(x) (1UL << (x)) + +#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x)) + +#define GPIO_SETDATAOUT_BIT(x) (1UL << (x)) + +#endif // __OMAP4430GPIO_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Gpmc.h b/Omap44xxPkg/Include/Omap4430/Omap4430Gpmc.h new file mode 100644 index 000000000..7d105cea4 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Gpmc.h @@ -0,0 +1,107 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430GPMC_H__ +#define __OMAP4430GPMC_H__ + +#define GPMC_BASE (0x50000000) + +//GPMC NAND definitions. +#define GPMC_SYSCONFIG (GPMC_BASE + 0x10) +#define SMARTIDLEMODE (0x2UL << 3) + +#define GPMC_SYSSTATUS (GPMC_BASE + 0x14) +#define GPMC_IRQSTATUS (GPMC_BASE + 0x18) +#define GPMC_IRQENABLE (GPMC_BASE + 0x1C) + +#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40) +#define TIMEOUTENABLE BIT0 +#define TIMEOUTDISABLE (0x0UL << 0) + +#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44) +#define GPMC_ERR_TYPE (GPMC_BASE + 0x48) + +#define GPMC_CONFIG (GPMC_BASE + 0x50) +#define WRITEPROTECT_HIGH BIT4 +#define WRITEPROTECT_LOW (0x0UL << 4) + +#define GPMC_STATUS (GPMC_BASE + 0x54) + +#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60) +#define DEVICETYPE_NOR (0x0UL << 10) +#define DEVICETYPE_NAND (0x2UL << 10) +#define DEVICESIZE_X8 (0x0UL << 12) +#define DEVICESIZE_X16 BIT12 + +#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64) +#define CSONTIME (0x0UL << 0) +#define CSRDOFFTIME (0x14UL << 8) +#define CSWROFFTIME (0x14UL << 16) + +#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68) +#define ADVRDOFFTIME (0x14UL << 8) +#define ADVWROFFTIME (0x14UL << 16) + +#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C) +#define OEONTIME BIT0 +#define OEOFFTIME (0xFUL << 8) +#define WEONTIME BIT16 +#define WEOFFTIME (0xFUL << 24) + +#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70) +#define RDCYCLETIME (0x14UL << 0) +#define WRCYCLETIME (0x14UL << 8) +#define RDACCESSTIME (0xCUL << 16) +#define PAGEBURSTACCESSTIME BIT24 + +#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74) +#define CYCLE2CYCLESAMECSEN BIT7 +#define CYCLE2CYCLEDELAY (0xAUL << 8) +#define WRDATAONADMUXBUS (0xFUL << 16) +#define WRACCESSTIME BIT24 + +#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78) +#define BASEADDRESS (0x30UL << 0) +#define CSVALID BIT6 +#define MASKADDRESS_128MB (0x8UL << 8) + +#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C) +#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80) +#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84) + +#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4) +#define ECCENABLE BIT0 +#define ECCDISABLE (0x0UL << 0) +#define ECCCS_0 (0x0UL << 1) +#define ECC16B BIT7 + +#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8) +#define ECCPOINTER_REG1 BIT0 +#define ECCCLEAR BIT8 + +#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC) +#define ECCSIZE0_512BYTES (0xFFUL << 12) +#define ECCSIZE1_512BYTES (0xFFUL << 22) + +#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200) +#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204) +#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208) +#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C) +#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210) +#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214) +#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218) +#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C) +#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220) + +#endif //__OMAP4430GPMC_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430I2c.h b/Omap44xxPkg/Include/Omap4430/Omap4430I2c.h new file mode 100644 index 000000000..50d5a4a05 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430I2c.h @@ -0,0 +1,62 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430I2C_H__ +#define __OMAP4430I2C_H__ + +//I2C register definitions. +#define I2C1BASE 0x48070000 + +#define I2C_IE (I2C1BASE + 0x84) +#define XRDY_IE BIT4 +#define RRDY_IE BIT3 +#define ARDY_IE BIT2 +#define NACK_IE BIT1 + +#define I2C_STAT (I2C1BASE + 0x88) +#define BB BIT12 +#define XRDY BIT4 +#define RRDY BIT3 +#define ARDY BIT2 +#define NACK BIT1 + +#define I2C_WE (I2C1BASE + 0x34) +#define I2C_SYSS (I2C1BASE + 0x90) +#define I2C_BUF (I2C1BASE + 0x94) +#define I2C_CNT (I2C1BASE + 0x98) +#define I2C_DATA (I2C1BASE + 0x9C) +#define I2C_SYSC (I2C1BASE + 0x10) + +#define I2C_CON (I2C1BASE + 0xA4) +#define STT BIT0 +#define STP BIT1 +#define XSA BIT8 +#define TRX BIT9 +#define MST BIT10 +#define I2C_EN BIT15 + +//#define I2C_OA0 (I2C1BASE + 0x28) +#define I2C_SA (I2C1BASE + 0xAC) +#define I2C_PSC (I2C1BASE + 0xB0) +#define I2C_SCLL (I2C1BASE + 0xB4) +#define I2C_SCLH (I2C1BASE + 0xB8) +#define I2C_SYSTEST (I2C1BASE + 0xBC) +#define I2C_BUFSTAT (I2C1BASE + 0xC0) +#define I2C_OA1 (I2C1BASE + 0xC4) +#define I2C_OA2 (I2C1BASE + 0xC8) +#define I2C_OA3 (I2C1BASE + 0xCC) +#define I2C_ACTOA (I2C1BASE + 0xD0) +#define I2C_SBLOCK (I2C1BASE + 0xD4) + +#endif //__OMAP4430I2C_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Interrupt.h b/Omap44xxPkg/Include/Omap4430/Omap4430Interrupt.h new file mode 100644 index 000000000..2b9968f51 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Interrupt.h @@ -0,0 +1,48 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430INTERRUPT_H__ +#define __OMAP4430INTERRUPT_H__ + +#define INTERRUPT_BASE (0x48200000) + +#define INT_NROF_VECTORS (96) +#define MAX_VECTOR (INT_NROF_VECTORS - 1) +#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010) +#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014) +#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040) +#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044) +#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048) +#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C) +#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050) +#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060) +#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064) +#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068) +#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n))) +#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n))) +#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n))) +#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n))) +#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n))) +#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n))) +#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n))) +#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n))) +#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m))) + +#define INTCPS_ILR_FIQ BIT0 +#define INTCPS_SIR_IRQ_MASK (0x7F) +#define INTCPS_CONTROL_NEWIRQAGR BIT0 +#define INTCPS_CONTROL_NEWFIQAGR BIT1 + +#endif // __OMAP4430INTERRUPT_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430MMCHS.h b/Omap44xxPkg/Include/Omap4430/Omap4430MMCHS.h new file mode 100644 index 000000000..579236104 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430MMCHS.h @@ -0,0 +1,214 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430SDIO_H__ +#define __OMAP4430SDIO_H__ + +//MMC/SD/SDIO1 register definitions. +#define MMCHS1BASE 0x4809C000 +#define MMC_REFERENCE_CLK (96000000) + +#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x110) +#define SOFTRESET BIT1 +#define ENAWAKEUP BIT2 + +#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x114) +#define RESETDONE_MASK BIT0 +#define RESETDONE BIT0 + +#define MMCHS_CSRE (MMCHS1BASE + 0x124) +#define MMCHS_SYSTEST (MMCHS1BASE + 0x128) + +#define MMCHS_CON (MMCHS1BASE + 0x12C) +#define OD BIT0 +#define NOINIT (0x0UL << 1) +#define INIT BIT1 +#define HR BIT2 +#define STR BIT3 +#define MODE BIT4 +#define DW8_1_4_BIT (0x0UL << 5) +#define DW8_8_BIT BIT5 +#define MIT BIT6 +#define CDP BIT7 +#define WPP BIT8 +#define CTPL BIT11 +#define CEATA_OFF (0x0UL << 12) +#define CEATA_ON BIT12 + +#define MMCHS_PWCNT (MMCHS1BASE + 0x130) + +#define MMCHS_BLK (MMCHS1BASE + 0x204) +#define BLEN_512BYTES (0x200UL << 0) + +#define MMCHS_ARG (MMCHS1BASE + 0x208) + +#define MMCHS_CMD (MMCHS1BASE + 0x20C) +#define DE_ENABLE BIT0 +#define BCE_ENABLE BIT1 +#define ACEN_ENABLE BIT2 +#define DDIR_READ BIT4 +#define DDIR_WRITE (0x0UL << 4) +#define MSBS_SGLEBLK (0x0UL << 5) +#define MSBS_MULTBLK BIT5 +#define RSP_TYPE_MASK (0x3UL << 16) +#define RSP_TYPE_136BITS BIT16 +#define RSP_TYPE_48BITS (0x2UL << 16) +#define CCCE_ENABLE BIT19 +#define CICE_ENABLE BIT20 +#define DP_ENABLE BIT21 +#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24) + +#define MMCHS_RSP10 (MMCHS1BASE + 0x210) +#define MMCHS_RSP32 (MMCHS1BASE + 0x214) +#define MMCHS_RSP54 (MMCHS1BASE + 0x218) +#define MMCHS_RSP76 (MMCHS1BASE + 0x21C) +#define MMCHS_DATA (MMCHS1BASE + 0x220) + +#define MMCHS_PSTATE (MMCHS1BASE + 0x224) +#define CMDI_MASK BIT0 +#define CMDI_ALLOWED (0x0UL << 0) +#define CMDI_NOT_ALLOWED BIT0 +#define DATI_MASK BIT1 +#define DATI_ALLOWED (0x0UL << 1) +#define DATI_NOT_ALLOWED BIT1 + +#define MMCHS_HCTL (MMCHS1BASE + 0x228) +#define DTW_1_BIT (0x0UL << 1) +#define DTW_4_BIT BIT1 +#define SDBP_MASK BIT8 +#define SDBP_OFF (0x0UL << 8) +#define SDBP_ON BIT8 +#define SDVS_1_8_V (0x5UL << 9) +#define SDVS_3_0_V (0x6UL << 9) +#define IWE BIT24 + +#define MMCHS_SYSCTL (MMCHS1BASE + 0x22C) +#define ICE BIT0 +#define ICS_MASK BIT1 +#define ICS BIT1 +#define CEN BIT2 +#define CLKD_MASK (0x3FFUL << 6) +#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2 +#define CLKD_400KHZ (0xF0UL) +#define DTO_MASK (0xFUL << 16) +#define DTO_VAL (0xEUL << 16) +#define SRA BIT24 +#define SRC_MASK BIT25 +#define SRC BIT25 +#define SRD BIT26 + +#define MMCHS_STAT (MMCHS1BASE + 0x230) +#define CC BIT0 +#define TC BIT1 +#define BWR BIT4 +#define BRR BIT5 +#define ERRI BIT15 +#define CTO BIT16 +#define DTO BIT20 +#define DCRC BIT21 +#define DEB BIT22 + +#define MMCHS_IE (MMCHS1BASE + 0x234) +#define CC_EN BIT0 +#define TC_EN BIT1 +#define BWR_EN BIT4 +#define BRR_EN BIT5 +#define CTO_EN BIT16 +#define CCRC_EN BIT17 +#define CEB_EN BIT18 +#define CIE_EN BIT19 +#define DTO_EN BIT20 +#define DCRC_EN BIT21 +#define DEB_EN BIT22 +#define CERR_EN BIT28 +#define BADA_EN BIT29 + +#define MMCHS_ISE (MMCHS1BASE + 0x238) +#define CC_SIGEN BIT0 +#define TC_SIGEN BIT1 +#define BWR_SIGEN BIT4 +#define BRR_SIGEN BIT5 +#define CTO_SIGEN BIT16 +#define CCRC_SIGEN BIT17 +#define CEB_SIGEN BIT18 +#define CIE_SIGEN BIT19 +#define DTO_SIGEN BIT20 +#define DCRC_SIGEN BIT21 +#define DEB_SIGEN BIT22 +#define CERR_SIGEN BIT28 +#define BADA_SIGEN BIT29 + +#define MMCHS_AC12 (MMCHS1BASE + 0x23C) + +#define MMCHS_CAPA (MMCHS1BASE + 0x240) +#define VS30 BIT25 +#define VS18 BIT26 + +#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x248) +#define MMCHS_REV (MMCHS1BASE + 0x2FC) + +#define CMD0 INDX(0) +#define CMD0_INT_EN (CC_EN | CEB_EN) + +#define CMD1 (INDX(1) | RSP_TYPE_48BITS) +#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN) + +#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS) +#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD5 (INDX(5) | RSP_TYPE_48BITS) +#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN) + +#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) +//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE +#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0) + +#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS) +#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ) +#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE) +#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE) +#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE) +#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define ACMD41 (INDX(41) | RSP_TYPE_48BITS) +#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define ACMD6 (INDX(6) | RSP_TYPE_48BITS) +#define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#endif //__OMAP4430SDIO_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h b/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h new file mode 100644 index 000000000..449e99662 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h @@ -0,0 +1,334 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430_PAD_CONFIGURATION_H__ +#define __OMAP4430_PAD_CONFIGURATION_H__ + +#define OMAP4430_CONTROL_MODULE_CORE_BASE 0x4A100000 +#define OMAP4430_CONTROL_MODULE_WKUP_BASE 0x4A31E000 + +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +typedef struct { + UINT16 Off; + UINT16 Val; + +} PAD_CONFIGURATION; + +#endif //__OMAP4430_PAD_CONFIGURATION_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Prcm.h b/Omap44xxPkg/Include/Omap4430/Omap4430Prcm.h new file mode 100644 index 000000000..40b6e1f36 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Prcm.h @@ -0,0 +1,148 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430PRCM_H__ +#define __OMAP4430PRCM_H__ + +// CONTROL_CORE + +#define CONTROL_CORE_U_BASE (0x4A002000) +#define CONTROL_CORE_ID_CODE (CONTROL_CORE_U_BASE+0x204) +#define CONTROL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL (CONTROL_CORE_U_BASE+0x320) +#define CONTROL_CORE_LDOSRAM_MPU_VOLTAGE_CTRL (CONTROL_CORE_U_BASE+0x324) +#define CONTROL_CORE_LDOSRAM_CORE_VOLTAGE_CTRL (CONTROL_CORE_U_BASE+0x328) + +#define CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL (0x0401040F) + +#define CONTROL_PBIAS_LITE (0x4a100600) +#define PBIASVMODE3V (BIT21) +#define PBIASLITEPWRDNZ (BIT22) +#define PBIASVMODEERR (BIT23) +#define PBIASHIZ (BIT25) +#define PBIASPWRDNZ (BIT26) + +// PRM + +#define PRM_U_BASE (0x4A307B00) + +#define PRM_RSTCTRL (PRM_U_BASE+0x0) +#define PRM_RSTST (PRM_U_BASE+0x4) + +#define PRM_RSTST_GLOBAL_COLD_RST_MASK (0x1) + +#define PRM_RSTCTRL_RST_GLOBAL_COLD_SW_VAL (0x2) + +#define PRM_VC_VAL_BYPASS (PRM_U_BASE+0xA0) +#define PRM_VC_VAL_BYPASS_REGADDR_POS (8) +#define PRM_VC_VAL_BYPASS_DATA_POS (16) + +#define PRM_VC_CFG_I2C_MODE (PRM_U_BASE+0xA8) +#define PRM_VC_CFG_I2C_CLK (PRM_U_BASE+0xAC) + +#define VC_CFG_I2C_MODE_VAL (0x0) +#define VC_CFG_I2C_CLK_VAL (0x167FFB) + +#define PMIC_SMPS_ID0_SLAVE_ADDR (0x12) +#define PMIC_VCORE3_CFG_FORCE_REGADDR (0x61) +#define PMIC_VCORE1_CFG_FORCE_REGADDR (0x55) +#define PMIC_VCORE2_CFG_FORCE_REGADDR (0x5B) +#define PMIC_VCORE3_CFG_FORCE_VSEL (0x28) +#define PMIC_VCORE1_CFG_FORCE_VSEL_VDD_MPU_4430 (0x32) +#define PMIC_VCORE1_CFG_FORCE_VSEL_VDD_CORE_4460 (0x28) +#define PMIC_VCORE2_CFG_FORCE_VSEL (0x28) + +#define TPS62361_SLAVE_ADDR (0x60) +#define TPS62361_SET1_REG_ADDR (0x01) +#define TPS62361_SET1_REG_VAL (0x46) + +// CKGEN_CM1 + +#define CKGEN_CM1_U_BASE (0x4A004100) + +#define CKGEN_CM1_CM_DIV_M3_DPLL_CORE (CKGEN_CM1_U_BASE+0x34) +#define CKGEN_CM1_CM_DIV_M4_DPLL_CORE (CKGEN_CM1_U_BASE+0x38) +#define CKGEN_CM1_CM_DIV_M5_DPLL_CORE (CKGEN_CM1_U_BASE+0x3C) +#define CKGEN_CM1_CM_DIV_M6_DPLL_CORE (CKGEN_CM1_U_BASE+0x40) +#define CKGEN_CM1_CM_DIV_M7_DPLL_CORE (CKGEN_CM1_U_BASE+0x44) + +#define CKGEN_CM1_CM_DIV_M2_DPLL_MPU (CKGEN_CM1_U_BASE+0x70) + +#define CKGEN_CM1_CM_CLKMODE_DPLL_IVA (CKGEN_CM1_U_BASE+0xA0) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA (CKGEN_CM1_U_BASE+0xAC) +#define CKGEN_CM1_CM_DIV_M4_DPLL_IVA (CKGEN_CM1_U_BASE+0xB8) +#define CKGEN_CM1_CM_DIV_M5_DPLL_IVA (CKGEN_CM1_U_BASE+0xBC) +#define CKGEN_CM1_CM_BYPCLK_DPLL_IVA (CKGEN_CM1_U_BASE+0xDC) + +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKSEL_VAL (0x19c10) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M4_VAL (4) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M5_VAL (7) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_BYCLK_VAL (1) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKMODE_VAL (7) + +#define CKGEN_CM1_CM_CLKMODE_DPLL_ABE (CKGEN_CM1_U_BASE+0xE0) +#define CKGEN_CM1_CM_CLKSEL_DPLL_ABE (CKGEN_CM1_U_BASE+0xEC) +#define CKGEN_CM1_CM_DIV_M2_DPLL_ABE (CKGEN_CM1_U_BASE+0xF0) +#define CKGEN_CM1_CM_DIV_M3_DPLL_ABE (CKGEN_CM1_U_BASE+0xF4) + +#define CKGEN_CM1_CM_CLKSEL_DPLL_ABE_VAL (0x82ee00) +#define CKGEN_CM1_CM_DIV_M2_DPLL_ABE_VAL (1) +#define CKGEN_CM1_CM_DIV_M3_DPLL_ABE_VAL (1) +#define CKGEN_CM1_CM_CLKMODE_DPLL_ABE_VAL (0xf27) + +#define CKGEN_CM1_CM_SHADOW_FREQ_CONFIG1 (CKGEN_CM1_U_BASE+0x160) +#define CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_M2_DIV_OPP100 (1<<11) +#define CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_DPLL_EN_LOCK (7<<8) +#define CM_SHADOW_FREQ_CONFIG1_DLL_RESET_RST (1<<3) +#define CM_SHADOW_FREQ_CONFIG1_FREQ_UPDATE_START (1<<0) + +#define CM_DIV_M2_DPLL_MPU_OPP100_VAL (1) +#define CM_DIV_M3_DPLL_CORE_OPP100_VAL (5) +#define CM_DIV_M4_DPLL_CORE_OPP100_VAL (8) +#define CM_DIV_M5_DPLL_CORE_OPP100_VAL (4) +#define CM_DIV_M6_DPLL_CORE_OPP100_VAL (6) +#define CM_DIV_M7_DPLL_CORE_OPP100_VAL (5) + +// CKGEN_CM2 + +#define CKGEN_CM2_U_BASE (0x4A008100) + +#define CKGEN_CM2_CM_CLKMODE_DPLL_USB (CKGEN_CM2_U_BASE+0x80) +#define CKGEN_CM2_CM_CLKSEL_DPLL_USB (CKGEN_CM2_U_BASE+0x8C) +#define CKGEN_CM2_CM_DIV_M2_DPLL_USB (CKGEN_CM2_U_BASE+0x90) + +#define CKGEN_CM2_CM_CLKSEL_DPLL_USB_VAL (0x25817) +#define CKGEN_CM2_CM_DIV_M2_DPLL_USB_VAL (0x282) +#define CKGEN_CM2_CM_CLKMODE_DPLL_USB_VAL (0x7) + +// RESTORE_CM1 + +#define RESTORE_CM1_U_BASE (0x4A004E00) + +#define RESTORE_CM1_CM_DIV_M2_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x4) +#define RESTORE_CM1_CM_DIV_M3_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x8) +#define RESTORE_CM1_CM_DIV_M5_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x10) +#define RESTORE_CM1_CM_DIV_M6_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x14) +#define RESTORE_CM1_CM_DIV_M7_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x18) +#define RESTORE_CM1_CM_CLKSEL_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x1C) +#define RESTORE_CM1_CM_SHADOW_FREQ_CONFIG1_RESTORE (RESTORE_CM1_U_BASE+0x30) + +// SCRM + +#define SCRM_U_BASE (0x4A30A000) + +#define SCRM_AUXCLK3 (SCRM_U_BASE+0x31C) +#define SCRM_AUXCLK3_VAL (0x00010100) + +#endif // __OMAP4430PRCM_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Rom.h b/Omap44xxPkg/Include/Omap4430/Omap4430Rom.h new file mode 100644 index 000000000..d2d2ef3d6 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Rom.h @@ -0,0 +1,53 @@ +/** @file + + Copyright (c) 2012 - 2013, Texas Instruments Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430ROM_H__ +#define __OMAP4430ROM_H__ + +#define PUBLIC_API_BASE (0x28400) + +#define PUBLIC_API_IRQ_REGISTER (0x44) +#define PUBLIC_API_IRQ_UNREGISTER (0x48) +#define PUBLIC_API_CM_ENABLEMODULECLOCKS (0xA0) +#define PUBLIC_API_WDTIMER_DISABLE (0x54) +#define PUBLIC_API_CTRL_CONFIGUREPADS (0xA8) + +//PUBLIC_API_IRQ_REGISTER +typedef UINT32 (** const IRQ_Register_pt)( UINT32, + UINT32, + UINT32 ); +#define RomIrqRegister(a, b, c) \ + (*(IRQ_Register_pt) ((PUBLIC_API_BASE+PUBLIC_API_IRQ_REGISTER)&0xFFFFFFFE))(a, b, c); + +//PUBLIC_API_IRQ_UNREGISTER +typedef UINT32 (** const IRQ_UnRegister_pt)( UINT32 ); +#define RomIrqUnRegister(a) \ + (*(IRQ_UnRegister_pt) (PUBLIC_API_BASE+PUBLIC_API_IRQ_UNREGISTER))(a); + +// PUBLIC_API_WDTIMER_DISABLE +typedef void (** const HAL_WDTIMER_Disable_pt)( void ); +#define RomWdtimerDisable() \ + (*(HAL_WDTIMER_Disable_pt) ((PUBLIC_API_BASE+PUBLIC_API_WDTIMER_DISABLE)&0xFFFFFFFE))(); + +//PUBLIC_API_CM_ENABLEMODULECLOCKS +typedef UINT32 (** const HAL_CM_EnableModuleClocks_pt)( UINT32, UINT32 ); +#define RomEnableClocks(a, b) \ + (*(HAL_CM_EnableModuleClocks_pt) ((PUBLIC_API_BASE+PUBLIC_API_CM_ENABLEMODULECLOCKS)&0xFFFFFFFE))(a, b); + +//PUBLIC_API_CTRL_CONFIGUREPADS +typedef UINT32 (** const HAL_CTRL_ConfigurePads_pt)( UINT32, UINT32 ); +#define RomCtrlConfigurePads(a, b) \ + (*(HAL_CTRL_ConfigurePads_pt) ((PUBLIC_API_BASE+PUBLIC_API_CTRL_CONFIGUREPADS)&0xFFFFFFFE))(a, b); + +#endif // __OMAP4430ROM_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Timer.h b/Omap44xxPkg/Include/Omap4430/Omap4430Timer.h new file mode 100644 index 000000000..15608e356 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Timer.h @@ -0,0 +1,88 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4TIMER_H__ +#define __OMAP4TIMER_H__ + +/* Watchdog */ +#define WDTIMER2_BASE (0x4A314000) +#define WWPS (0x034) +#define WSPR (0x048) + +/* DMTIMERS*/ + +#define GPTIMER1_BASE (0x48313000) +#define GPTIMER2_BASE (0x48032000) +#define GPTIMER3_BASE (0x48034000) +#define GPTIMER4_BASE (0x48036000) +#define GPTIMER5_BASE (0x49038000) +#define GPTIMER6_BASE (0x4903A000) +#define GPTIMER7_BASE (0x4903C000) +#define GPTIMER8_BASE (0x4903E000) +#define GPTIMER9_BASE (0x4803E000) +#define GPTIMER10_BASE (0x48086000) +#define GPTIMER11_BASE (0x48088000) +#define GPTIMER12_BASE (0x48304000) + +// TODO: review below timer IP register offsets changing from OMAP3 to OMAP4 + +#define GPTIMER_TIOCP_CFG (/*0x0010*/) +#define GPTIMER_TISTAT (/*0x0014*/) +#define GPTIMER_TISR (/*0x0018 => IRQSTATUS*/0x28) +#define GPTIMER_TIER (/*0x001C => IRQSTATUS_SET*/0x2C) +#define GPTIMER_TWER (/*0x0020*/) +#define GPTIMER_TCLR (/*0x0024*/0x38) +#define GPTIMER_TCRR (/*0x0028*/0x3C) +#define GPTIMER_TLDR (/*0x002C*/0x40) +#define GPTIMER_TTGR (/*0x0030*/0x44) +#define GPTIMER_TWPS (/*0x0034*/0x48) +#define GPTIMER_TMAR (/*0x0038*/0x4C) +#define GPTIMER_TCAR1 (/*0x003C*/0x50) +#define GPTIMER_TSICR (/*0x0040*/0x54) +#define GPTIMER_TCAR2 (/*0x0044*/0x58) +#define GPTIMER_TPIR (/*0x0048*/) +#define GPTIMER_TNIR (/*0x004C*/) +#define GPTIMER_TCVR (/*0x0050*/) +#define GPTIMER_TOCR (/*0x0054*/) +#define GPTIMER_TOWR (/*0x0058*/) + +#define TISR_TCAR_IT_FLAG_MASK BIT2 +#define TISR_OVF_IT_FLAG_MASK BIT1 +#define TISR_MAT_IT_FLAG_MASK BIT0 +#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK) + +#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2) +#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1) +#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0) +#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING) + +#define TISR_TCAR_IT_FLAG_CLEAR BIT2 +#define TISR_OVF_IT_FLAG_CLEAR BIT1 +#define TISR_MAT_IT_FLAG_CLEAR BIT0 +#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR) + +#define TCLR_AR_AUTORELOAD BIT1 +#define TCLR_AR_ONESHOT (0UL << 1) +#define TCLR_ST_ON BIT0 +#define TCLR_ST_OFF (0UL << 0) + +#define TIER_TCAR_IT_ENABLE (BIT2 +#define TIER_TCAR_IT_DISABLE (0UL << 2) +#define TIER_OVF_IT_ENABLE BIT1 +#define TIER_OVF_IT_DISABLE (0UL << 1) +#define TIER_MAT_IT_ENABLE BIT0 +#define TIER_MAT_IT_DISABLE (0UL << 0) + +#endif // __OMAP4TIMER_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Uart.h b/Omap44xxPkg/Include/Omap4430/Omap4430Uart.h new file mode 100644 index 000000000..27ba44563 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Uart.h @@ -0,0 +1,54 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430UART_H__ +#define __OMAP4430UART_H__ + +#define UART1_BASE (0x4806A000) +#define UART2_BASE (0x4806C000) +#define UART3_BASE (0x48020000) + +#define UART_DLL_REG (0x0000) +#define UART_RBR_REG (0x0000) +#define UART_THR_REG (0x0000) +#define UART_DLH_REG (0x0004) +#define UART_FCR_REG (0x0008) +#define UART_LCR_REG (0x000C) +#define UART_MCR_REG (0x0010) +#define UART_LSR_REG (0x0014) +#define UART_MDR1_REG (0x0020) + +#define UART_FCR_TX_FIFO_CLEAR BIT2 +#define UART_FCR_RX_FIFO_CLEAR BIT1 +#define UART_FCR_FIFO_ENABLE BIT0 + +#define UART_LCR_DIV_EN_ENABLE BIT7 +#define UART_LCR_DIV_EN_DISABLE (0UL << 7) +#define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0) + +#define UART_MCR_RTS_FORCE_ACTIVE BIT1 +#define UART_MCR_DTR_FORCE_ACTIVE BIT0 + +#define UART_LSR_TX_FIFO_E_MASK BIT5 +#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5) +#define UART_LSR_TX_FIFO_E_EMPTY BIT5 +#define UART_LSR_RX_FIFO_E_MASK BIT0 +#define UART_LSR_RX_FIFO_E_NOT_EMPTY BIT0 +#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0) + +// BIT2:BIT0 +#define UART_MDR1_MODE_SELECT_DISABLE (7UL) +#define UART_MDR1_MODE_SELECT_UART_16X (0UL) + +#endif // __OMAP4430UART_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Usb.h b/Omap44xxPkg/Include/Omap4430/Omap4430Usb.h new file mode 100644 index 000000000..22fe47c83 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Usb.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430USB_H__ +#define __OMAP4430USB_H__ + +#define USB_BASE (0x4A060000) + +#define UHH_SYSCONFIG (USB_BASE + 0x4010) +#define UHH_HOSTCONFIG (USB_BASE + 0x4040) +#define UHH_SYSSTATUS (USB_BASE + 0x4014) + +#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4C00) + +#define UHH_SYSCONFIG_STANDBYMODE_NO_STANDBY BIT4 +#define UHH_SYSCONFIG_IDLEMODE_NO_IDLE BIT2 +#define UHH_SYSCONFIG_SOFTRESET BIT0 + +#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9) +#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8) +#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5) +#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4 +#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3 +#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2 +#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1) +#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 16) + +#define UHH_SYSSTATUS_RESETDONE (BIT1 | BIT2) + +#endif // __OMAP4430USB_H__ diff --git a/Omap44xxPkg/Include/TWL6030.h b/Omap44xxPkg/Include/TWL6030.h new file mode 100644 index 000000000..8126ca7c2 --- /dev/null +++ b/Omap44xxPkg/Include/TWL6030.h @@ -0,0 +1,78 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __TWL6030_H__ +#define __TWL6030_H__ + +#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF) +#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF) +#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF)) + +// I2C Address group +#define I2C_ADDR_GRP_ID1 0x48 +#define I2C_ADDR_GRP_ID2 0x49 +#define I2C_ADDR_GRP_ID3 0x4A +#define I2C_ADDR_GRP_ID4 0x4B +#define I2C_ADDR_GRP_ID5 0x12 + +// MMC definitions. +#define VMMC_CFG_GRP 0x98 +#define DEV_GRP_APP BIT0 + +#define VMMC_CFG_STATE 0x9A +#define VMMC_CFG_STATE_OFF 0xE0 +#define VMMC_CFG_STATE_ON 0xE1 + +#define VMMC_CFG_VOLTAGE 0x9B +#define VSEL_3_00V 0x15 + +#define MMCCTRL 0xEE +#define CARD_DET_STS_MMC BIT0 +#define CARD_DET_CFG BIT3 + +// LEDEN register +#define LEDEN 0xEE +#define LEDAON BIT0 +#define LEDBON BIT1 +#define LEDAPWM BIT4 +#define LEDBPWM BIT5 + +// RTC registers +#define SECONDS_REG 0x1C +#define MINUTES_REG 0x1D +#define HOURS_REG 0x1E +#define DAYS_REG 0x1F +#define MONTHS_REG 0x20 +#define YEARS_REG 0x21 +#define WEEKS_REG 0x22 +#define RTC_CTRL_REG 0x29 + +// USB PHY power +#define VAUX2_DEDICATED 0x79 +#define VAUX2_DEV_GRP 0x76 + +#define VAUX_DEV_GRP_NONE 0x00 +#define VAUX_DEV_GRP_P1 0x20 +#define VAUX_DEV_GRP_P2 0x40 +#define VAUX_DEV_GRP_P3 0x80 +#define VAUX_DEDICATED_18V 0x05 + +// Display subsystem +#define VPLL2_DEDICATED 0x91 +#define VPLL2_DEV_GRP 0x8E + +#define GPIODATADIR1 0x9B +#define SETGPIODATAOUT1 0xA4 + +#endif //__TWL6030_H__ diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c new file mode 100644 index 000000000..38c84dd88 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c @@ -0,0 +1,445 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include <PiDxe.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DevicePathLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> + +#include <Guid/GlobalVariable.h> + +#include "LcdGraphicsOutputDxe.h" + +extern BOOLEAN mDisplayInitialized; + +// +// Function Definitions +// + +STATIC +EFI_STATUS +VideoCopyNoHorizontalOverlap ( + IN UINTN BitsPerPixel, + IN volatile VOID *FrameBufferBase, + IN UINT32 HorizontalResolution, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN SourceLine; + UINTN DestinationLine; + UINTN WidthInBytes; + UINTN LineCount; + INTN Step; + VOID *SourceAddr; + VOID *DestinationAddr; + + if( DestinationY <= SourceY ) { + // scrolling up (or horizontally but without overlap) + SourceLine = SourceY; + DestinationLine = DestinationY; + Step = 1; + } else { + // scrolling down + SourceLine = SourceY + Height; + DestinationLine = DestinationY + Height; + Step = -1; + } + + WidthInBytes = Width * 2; + + for( LineCount = 0; LineCount < Height; LineCount++ ) { + // Update the start addresses of source & destination using 16bit pointer arithmetic + SourceAddr = (VOID *)((UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourceX ); + DestinationAddr = (VOID *)((UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX); + + // Copy the entire line Y from video ram to the temp buffer + CopyMem( DestinationAddr, SourceAddr, WidthInBytes); + + // Update the line numbers + SourceLine += Step; + DestinationLine += Step; + } + + return Status; +} + +STATIC +EFI_STATUS +VideoCopyHorizontalOverlap ( + IN UINTN BitsPerPixel, + IN volatile VOID *FrameBufferBase, + UINT32 HorizontalResolution, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + UINT16 *PixelBuffer16bit; + UINT16 *SourcePixel16bit; + UINT16 *DestinationPixel16bit; + + UINT32 SourcePixelY; + UINT32 DestinationPixelY; + UINTN SizeIn16Bits; + + // Allocate a temporary buffer + PixelBuffer16bit = (UINT16 *) AllocatePool((Height * Width) * sizeof(UINT16)); + + if (PixelBuffer16bit == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto EXIT; + } + + // Access each pixel inside the source area of the Video Memory and copy it to the temp buffer + + SizeIn16Bits = Width * 2; + + for (SourcePixelY = SourceY, DestinationPixel16bit = PixelBuffer16bit; + SourcePixelY < SourceY + Height; + SourcePixelY++, DestinationPixel16bit += Width) + { + // Calculate the source address: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourcePixelY * HorizontalResolution + SourceX; + + // Copy the entire line Y from Video to the temp buffer + CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits); + } + + // Copy from the temp buffer into the destination area of the Video Memory + + for (DestinationPixelY = DestinationY, SourcePixel16bit = PixelBuffer16bit; + DestinationPixelY < DestinationY + Height; + DestinationPixelY++, SourcePixel16bit += Width) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + (DestinationPixelY * HorizontalResolution + DestinationX); + + // Copy the entire line Y from the temp buffer to Video + CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits); + } + + // Free the allocated memory + FreePool((VOID *) PixelBuffer16bit); + + +EXIT: + return Status; +} + +STATIC +EFI_STATUS +BltVideoFill ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_PIXEL_BITMASK* PixelInformation; + EFI_STATUS Status; + UINT32 HorizontalResolution; + VOID *FrameBufferBase; + UINT16 *DestinationPixel16bit; + UINT16 Pixel16bit; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + HorizontalResolution = This->Mode->Info->HorizontalResolution; + + // Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel + Pixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + ); + + // Copy the SourcePixel into every pixel inside the target rectangle + for (DestinationLine = DestinationY; + DestinationLine < DestinationY + Height; + DestinationLine++) + { + for (DestinationPixelX = DestinationX; + DestinationPixelX < DestinationX + Width; + DestinationPixelX++) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + *DestinationPixel16bit = Pixel16bit; + } + } + + + return Status; +} + +STATIC +EFI_STATUS +BltVideoToBltBuffer ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + EFI_PIXEL_BITMASK *PixelInformation; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiDestinationPixel; + VOID *FrameBufferBase; + UINT16 *SourcePixel16bit; + UINT16 Pixel16bit; + UINT32 SourcePixelX; + UINT32 SourceLine; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINT32 BltBufferHorizontalResolution; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { + // Delta is not zero and it is different from the width. + // Divide it by the size of a pixel to find out the buffer's horizontal resolution. + BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); + } else { + BltBufferHorizontalResolution = Width; + } + + // Access each pixel inside the Video Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX; + EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX; + + // Snapshot the pixel from the video buffer once, to speed up the operation. + // If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations. + Pixel16bit = *SourcePixel16bit; + + // Copy the pixel into the new target + EfiDestinationPixel->Red = (UINT8) ( (Pixel16bit & PixelInformation->RedMask ) >> 8 ); + EfiDestinationPixel->Green = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask ) >> 3 ); + EfiDestinationPixel->Blue = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask ) << 3 ); + } + } + + return Status; +} + +STATIC +EFI_STATUS +BltBufferToVideo ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + EFI_PIXEL_BITMASK *PixelInformation; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel; + VOID *FrameBufferBase; + UINT16 *DestinationPixel16bit; + UINT32 SourcePixelX; + UINT32 SourceLine; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINT32 BltBufferHorizontalResolution; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { + // Delta is not zero and it is different from the width. + // Divide it by the size of a pixel to find out the buffer's horizontal resolution. + BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); + } else { + BltBufferHorizontalResolution = Width; + } + + // Access each pixel inside the BltBuffer Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) { + + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX; + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + // Only the most significant bits will be copied across: + // To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits + *DestinationPixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + ); + } + } + + return Status; +} + +STATIC +EFI_STATUS +BltVideoToVideo ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + UINTN BitsPerPixel; + VOID *FrameBufferBase; + + BitsPerPixel = 16; + + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + // + // BltVideo to BltVideo: + // + // Source is the Video Memory, + // Destination is the Video Memory + + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + // The UEFI spec currently states: + // "There is no limitation on the overlapping of the source and destination rectangles" + // Therefore, we must be careful to avoid overwriting the source data + if( SourceY == DestinationY ) { + // Copying within the same height, e.g. horizontal shift + if( SourceX == DestinationX ) { + // Nothing to do + Status = EFI_SUCCESS; + } else if( ((SourceX>DestinationX)?(SourceX - DestinationX):(DestinationX - SourceX)) < Width ) { + // There is overlap + Status = VideoCopyHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } else { + // No overlap + Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } + } else { + // Copying from different heights + Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } + + return Status; +} + +EFI_STATUS +EFIAPI +LcdGraphicsBlt ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + if (!mDisplayInitialized) { + InitializeDisplay (Instance); + } + + switch (BltOperation) { + case EfiBltVideoFill: + Status = BltVideoFill (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltVideoToBltBuffer: + Status = BltVideoToBltBuffer (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltBufferToVideo: + Status = BltBufferToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltVideoToVideo: + Status = BltVideoToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiGraphicsOutputBltOperationMax: + default: + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: Invalid Operation\n")); + Status = EFI_INVALID_PARAMETER; + break; + } + + return Status; +} diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c new file mode 100644 index 000000000..e43680407 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -0,0 +1,406 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "LcdGraphicsOutputDxe.h" + +BOOLEAN mDisplayInitialized = FALSE; + +LCD_MODE LcdModes[] = { + { + 0, 640, 480, + 9, 4, + 96, 16, 48, + 2, 10, 33 + }, + { + 1, 800, 600, + 11, 2, + 120, 56, 64, + 5, 37, 22 + }, + { + 2, 1024, 768, + 6, 2, + 96, 16, 48, + 2, 10, 33 + }, +}; + +LCD_INSTANCE mLcdTemplate = { + LCD_INSTANCE_SIGNATURE, + NULL, // Handle + { // ModeInfo + 0, // Version + 0, // HorizontalResolution + 0, // VerticalResolution + PixelBltOnly, // PixelFormat + { + 0xF800, //RedMask; + 0x7E0, //GreenMask; + 0x1F, //BlueMask; + 0x0//ReservedMask + }, // PixelInformation + 0, // PixelsPerScanLine + }, + { // Mode + 3, // MaxMode; + 0, // Mode; + NULL, // Info; + 0, // SizeOfInfo; + 0, // FrameBufferBase; + 0 // FrameBufferSize; + }, + { // Gop + LcdGraphicsQueryMode, // QueryMode + LcdGraphicsSetMode, // SetMode + LcdGraphicsBlt, // Blt + NULL // *Mode + }, + { // DevicePath + { + { + HARDWARE_DEVICE_PATH, HW_VENDOR_DP, + (UINT8) (sizeof(VENDOR_DEVICE_PATH)), + (UINT8) ((sizeof(VENDOR_DEVICE_PATH)) >> 8), + }, + // Hardware Device Path for Lcd + EFI_CALLER_ID_GUID // Use the driver's GUID + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + sizeof(EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +EFI_STATUS +LcdInstanceContructor ( + OUT LCD_INSTANCE** NewInstance + ) +{ + LCD_INSTANCE* Instance; + + Instance = AllocateCopyPool (sizeof(LCD_INSTANCE), &mLcdTemplate); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->Gop.Mode = &Instance->Mode; + Instance->Mode.Info = &Instance->ModeInfo; + + *NewInstance = Instance; + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ) +{ + EFI_STATUS Status; + EFI_CPU_ARCH_PROTOCOL *Cpu; + UINTN MaxSize; + + MaxSize = 0x500000; + *VramSize = MaxSize; + + // Allocate VRAM from DRAM + Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES((MaxSize)), VramBaseAddress); + if (EFI_ERROR(Status)) { + return Status; + } + + // Ensure the Cpu architectural protocol is already installed + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); + ASSERT_EFI_ERROR(Status); + + // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. + Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + if (EFI_ERROR(Status)) { + gBS->FreePool (VramBaseAddress); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +DssSetMode ( + UINT32 VramBaseAddress, + UINTN ModeNumber + ) +{ + // Make sure the interface clock is running + MmioWrite32 (CM_ICLKEN_DSS, EN_DSS); + + // Stop the functional clocks + MmioAnd32 (CM_FCLKEN_DSS, ~(EN_DSS1 | EN_DSS2 | EN_TV)); + + // Program the DSS clock divisor + MmioWrite32 (CM_CLKSEL_DSS, 0x1000 | (LcdModes[ModeNumber].DssDivisor)); + + // Start the functional clocks + MmioOr32 (CM_FCLKEN_DSS, (EN_DSS1 | EN_DSS2 | EN_TV)); + + // Wait for DSS to stabilize + gBS->Stall(1); + + // Reset the subsystem + MmioWrite32(DSS_SYSCONFIG, DSS_SOFTRESET); + while (!(MmioRead32 (DSS_SYSSTATUS) & DSS_RESETDONE)); + + // Configure LCD parameters + MmioWrite32 (DISPC_SIZE_LCD, + ((LcdModes[ModeNumber].HorizontalResolution - 1) + | ((LcdModes[ModeNumber].VerticalResolution - 1) << 16)) + ); + MmioWrite32 (DISPC_TIMING_H, + ( (LcdModes[ModeNumber].HSync - 1) + | ((LcdModes[ModeNumber].HFrontPorch - 1) << 8) + | ((LcdModes[ModeNumber].HBackPorch - 1) << 20)) + ); + MmioWrite32 (DISPC_TIMING_V, + ( (LcdModes[ModeNumber].VSync - 1) + | ((LcdModes[ModeNumber].VFrontPorch - 1) << 8) + | ((LcdModes[ModeNumber].VBackPorch - 1) << 20)) + ); + + // Set the framebuffer to only load frames (no gamma tables) + MmioAnd32 (DISPC_CONFIG, CLEARLOADMODE); + MmioOr32 (DISPC_CONFIG, LOAD_FRAME_ONLY); + + // Divisor for the pixel clock + MmioWrite32(DISPC_DIVISOR, ((1 << 16) | LcdModes[ModeNumber].DispcDivisor) ); + + // Set up the graphics layer + MmioWrite32 (DISPC_GFX_PRELD, 0x2D8); + MmioWrite32 (DISPC_GFX_BA0, VramBaseAddress); + MmioWrite32 (DISPC_GFX_SIZE, + ((LcdModes[ModeNumber].HorizontalResolution - 1) + | ((LcdModes[ModeNumber].VerticalResolution - 1) << 16)) + ); + + MmioWrite32(DISPC_GFX_ATTR, (GFXENABLE | RGB16 | BURSTSIZE16)); + + // Start it all + MmioOr32 (DISPC_CONTROL, (LCDENABLE | ACTIVEMATRIX | DATALINES24 | BYPASS_MODE | LCDENABLESIGNAL)); + MmioOr32 (DISPC_CONTROL, GOLCD); + + return EFI_SUCCESS; +} + +EFI_STATUS +HwInitializeDisplay ( + UINTN VramBaseAddress, + UINTN VramSize + ) +{ + EFI_STATUS Status; + UINT8 Data; + EFI_TPL OldTpl; + EMBEDDED_EXTERNAL_DEVICE *gTPS65950; + + // Enable power lines used by TFP410 + Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950); + ASSERT_EFI_ERROR (Status); + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + Data = VAUX_DEV_GRP_P1; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEV_GRP), 1, &Data); + ASSERT_EFI_ERROR(Status); + + Data = VAUX_DEDICATED_18V; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEDICATED), 1, &Data); + ASSERT_EFI_ERROR (Status); + + // Power up TFP410 (set GPIO2 on TPS - for PandaBoard-xM) + Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data); + ASSERT_EFI_ERROR (Status); + Data |= BIT2; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data); + ASSERT_EFI_ERROR (Status); + + Data = BIT2; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, SETGPIODATAOUT1), 1, &Data); + ASSERT_EFI_ERROR (Status); + + gBS->RestoreTPL(OldTpl); + + // Power up TFP410 (set GPIO 170 - for older PandaBoards) + MmioAnd32 (GPIO6_BASE + GPIO_OE, ~BIT10); + MmioOr32 (GPIO6_BASE + GPIO_SETDATAOUT, BIT10); + + return EFI_SUCCESS; +} + +EFI_STATUS +InitializeDisplay ( + IN LCD_INSTANCE* Instance + ) +{ + EFI_STATUS Status; + UINTN VramSize; + EFI_PHYSICAL_ADDRESS VramBaseAddress; + + Status = LcdPlatformGetVram (&VramBaseAddress, &VramSize); + if (EFI_ERROR (Status)) { + return Status; + } + + Instance->Mode.FrameBufferBase = VramBaseAddress; + Instance->Mode.FrameBufferSize = VramSize; + + Status = HwInitializeDisplay((UINTN)VramBaseAddress, VramSize); + if (!EFI_ERROR (Status)) { + mDisplayInitialized = TRUE; + } + + return Status; +} + +EFI_STATUS +EFIAPI +LcdGraphicsQueryMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info + ) +{ + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + if (!mDisplayInitialized) { + InitializeDisplay (Instance); + } + + // Error checking + if ( (This == NULL) || (Info == NULL) || (SizeOfInfo == NULL) || (ModeNumber >= This->Mode->MaxMode) ) { + DEBUG((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber )); + return EFI_INVALID_PARAMETER; + } + + *Info = AllocateCopyPool(sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), &Instance->ModeInfo); + if (*Info == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + + (*Info)->Version = 0; + (*Info)->HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution; + (*Info)->VerticalResolution = LcdModes[ModeNumber].VerticalResolution; + (*Info)->PixelFormat = PixelBltOnly; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LcdGraphicsSetMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber + ) +{ + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + if (ModeNumber >= Instance->Mode.MaxMode) { + return EFI_UNSUPPORTED; + } + + if (!mDisplayInitialized) { + InitializeDisplay (Instance); + } + + DssSetMode((UINT32)Instance->Mode.FrameBufferBase, ModeNumber); + + Instance->Mode.Mode = ModeNumber; + Instance->ModeInfo.HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution; + Instance->ModeInfo.VerticalResolution = LcdModes[ModeNumber].VerticalResolution; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LcdGraphicsOutputDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + LCD_INSTANCE* Instance; + + // TODO: this driver makes boot-up crashing on Panda + return EFI_SUCCESS; + + Status = LcdInstanceContructor (&Instance); + if (EFI_ERROR(Status)) { + goto EXIT; + } + + // Install the Graphics Output Protocol and the Device Path + Status = gBS->InstallMultipleProtocolInterfaces( + &Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, + NULL + ); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the protocol. Exit Status=%r\n", Status)); + goto EXIT; + } + + // Register for an ExitBootServicesEvent + // When ExitBootServices starts, this function here will make sure that the graphics driver will shut down properly, + // i.e. it will free up all allocated memory and perform any necessary hardware re-configuration. + /*Status = gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + LcdGraphicsExitBootServicesEvent, NULL, + &Instance->ExitBootServicesEvent + ); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the ExitBootServicesEvent handler. Exit Status=%r\n", Status)); + goto EXIT_ERROR_UNINSTALL_PROTOCOL; + }*/ + + // To get here, everything must be fine, so just exit + goto EXIT; + +//EXIT_ERROR_UNINSTALL_PROTOCOL: + /* The following function could return an error message, + * however, to get here something must have gone wrong already, + * so preserve the original error, i.e. don't change + * the Status variable, even it fails to uninstall the protocol. + */ +/* gBS->UninstallMultipleProtocolInterfaces ( + Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, // Uninstall Graphics Output protocol + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, // Uninstall device path + NULL + );*/ + +EXIT: + return Status; + +} diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h new file mode 100644 index 000000000..721859724 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -0,0 +1,157 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4_DSS_GRAPHICS__ +#define __OMAP4_DSS_GRAPHICS__ + +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> + +#include <Protocol/DevicePathToText.h> +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/Cpu.h> + +#include <Guid/GlobalVariable.h> + +#include <Omap4430/Omap4430.h> +#include <TWL6030.h> + +typedef struct { + VENDOR_DEVICE_PATH Guid; + EFI_DEVICE_PATH_PROTOCOL End; +} LCD_GRAPHICS_DEVICE_PATH; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode; + EFI_GRAPHICS_OUTPUT_PROTOCOL Gop; + LCD_GRAPHICS_DEVICE_PATH DevicePath; +// EFI_EVENT ExitBootServicesEvent; +} LCD_INSTANCE; + +#define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0') +#define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE) + +typedef struct { + UINTN Mode; + UINTN HorizontalResolution; + UINTN VerticalResolution; + + UINT32 DssDivisor; + UINT32 DispcDivisor; + + UINT32 HSync; + UINT32 HFrontPorch; + UINT32 HBackPorch; + + UINT32 VSync; + UINT32 VFrontPorch; + UINT32 VBackPorch; +} LCD_MODE; + +EFI_STATUS +InitializeDisplay ( + IN LCD_INSTANCE* Instance +); + +EFI_STATUS +EFIAPI +LcdGraphicsQueryMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info +); + +EFI_STATUS +EFIAPI +LcdGraphicsSetMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber +); + +EFI_STATUS +EFIAPI +LcdGraphicsBlt ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer +); + +// HW registers +#define CM_FCLKEN_DSS 0x48004E00 +#define CM_ICLKEN_DSS 0x48004E10 + +#define DSS_CONTROL 0x48050040 +#define DSS_SYSCONFIG 0x48050010 +#define DSS_SYSSTATUS 0x48050014 + +#define DISPC_CONTROL 0x48050440 +#define DISPC_CONFIG 0x48050444 +#define DISPC_SIZE_LCD 0x4805047C +#define DISPC_TIMING_H 0x48050464 +#define DISPC_TIMING_V 0x48050468 + +#define CM_CLKSEL_DSS 0x48004E40 +#define DISPC_DIVISOR 0x48050470 +#define DISPC_POL_FREQ 0x4805046C + +#define DISPC_GFX_TABLE_BA 0x480504B8 +#define DISPC_GFX_BA0 0x48050480 +#define DISPC_GFX_BA1 0x48050484 +#define DISPC_GFX_POS 0x48050488 +#define DISPC_GFX_SIZE 0x4805048C +#define DISPC_GFX_ATTR 0x480504A0 +#define DISPC_GFX_PRELD 0x4805062C + +#define DISPC_DEFAULT_COLOR_0 0x4805044C + +//#define DISPC_IRQSTATUS + +// Bits +#define EN_TV 0x4 +#define EN_DSS2 0x2 +#define EN_DSS1 0x1 +#define EN_DSS 0x1 + +#define DSS_SOFTRESET 0x2 +#define DSS_RESETDONE 0x1 + +#define BYPASS_MODE (BIT15 | BIT16) + +#define LCDENABLE BIT0 +#define ACTIVEMATRIX BIT3 +#define GOLCD BIT5 +#define DATALINES24 (BIT8 | BIT9) +#define LCDENABLESIGNAL BIT28 + +#define GFXENABLE BIT0 +#define RGB16 (0x6 << 1) +#define BURSTSIZE16 (0x2 << 6) + +#define CLEARLOADMODE ~(BIT2 | BIT1) +#define LOAD_FRAME_ONLY BIT2 + +#endif diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf new file mode 100644 index 000000000..f859b28c1 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf @@ -0,0 +1,52 @@ +#/** @file +# +# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = LcdGraphicsDxe + FILE_GUID = E68088EF-D1A4-4336-C1DB-4D3A204730A6 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = LcdGraphicsOutputDxeInitialize + +[Sources.common] + LcdGraphicsOutputDxe.c + LcdGraphicsOutputBlt.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + ArmLib + UefiLib + BaseLib + DebugLib + TimerLib + UefiDriverEntryPoint + UefiBootServicesTableLib + IoLib + BaseMemoryLib + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiGraphicsOutputProtocolGuid + gEfiDevicePathToTextProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + +[Depex] + gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid diff --git a/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c new file mode 100755 index 000000000..b57a099c0 --- /dev/null +++ b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c @@ -0,0 +1,166 @@ +/** @file + Debug Agent timer lib for OMAP. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include <Base.h> +#include <Library/BaseLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include <Omap4430/Omap4430.h> + + +volatile UINT32 gVector; + +// Cached registers +volatile UINT32 gTISR; +volatile UINT32 gTCLR; +volatile UINT32 gTLDR; +volatile UINT32 gTCRR; +volatile UINT32 gTIER; + +VOID +EnableInterruptSource ( + VOID + ) +{ + UINTN Bank; + UINTN Bit; + + // Map vector to FIQ, IRQ is default + MmioWrite32 (INTCPS_ILR (gVector), 1); + + Bank = gVector / 32; + Bit = 1UL << (gVector % 32); + + MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit); +} + +VOID +DisableInterruptSource ( + VOID + ) +{ + UINTN Bank; + UINTN Bit; + + Bank = gVector / 32; + Bit = 1UL << (gVector % 32); + + MmioWrite32 (INTCPS_MIR_SET(Bank), Bit); +} + + + +/** + Setup all the hardware needed for the debug agents timer. + + This function is used to set up debug enviroment. It may enable interrupts. + +**/ +VOID +EFIAPI +DebugAgentTimerIntialize ( + VOID + ) +{ + UINT32 TimerBaseAddress; + UINT32 TimerNumber; + + TimerNumber = PcdGet32(PcdOmap44xxDebugAgentTimer); + gVector = InterruptVectorForTimer (TimerNumber); + + // Set up the timer registers + TimerBaseAddress = TimerBase (TimerNumber); + gTISR = TimerBaseAddress + GPTIMER_TISR; + gTCLR = TimerBaseAddress + GPTIMER_TCLR; + gTLDR = TimerBaseAddress + GPTIMER_TLDR; + gTCRR = TimerBaseAddress + GPTIMER_TCRR; + gTIER = TimerBaseAddress + GPTIMER_TIER; + + if ((TimerNumber < 2) || (TimerNumber > 9)) { + // This code assumes one the General Purpose timers is used + // GPT2 - GPT9 + CpuDeadLoop (); + } + // Set source clock for GPT2 - GPT9 to SYS_CLK + MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2)); + +} + + +/** + Set the period for the debug agent timer. Zero means disable the timer. + + @param[in] TimerPeriodMilliseconds Frequency of the debug agent timer. + +**/ +VOID +EFIAPI +DebugAgentTimerSetPeriod ( + IN UINT32 TimerPeriodMilliseconds + ) +{ + UINT64 TimerCount; + INT32 LoadValue; + + if (TimerPeriodMilliseconds == 0) { + // Turn off GPTIMER3 + MmioWrite32 (gTCLR, TCLR_ST_OFF); + + DisableInterruptSource (); + } else { + // Calculate required timer count + TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds)); + + // Set GPTIMER5 Load register + LoadValue = (INT32) -TimerCount; + MmioWrite32 (gTLDR, LoadValue); + MmioWrite32 (gTCRR, LoadValue); + + // Enable Overflow interrupt + MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE); + + // Turn on GPTIMER3, it will reload at overflow + MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + + EnableInterruptSource (); + } +} + + +/** + Perform End Of Interrupt for the debug agent timer. This is called in the + interrupt handler after the interrupt has been processed. + +**/ +VOID +EFIAPI +DebugAgentTimerEndOfInterrupt ( + VOID + ) +{ + // Clear all timer interrupts + MmioWrite32 (gTISR, TISR_CLEAR_ALL); + + // Poll interrupt status bits to ensure clearing + while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING); + + MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR); + ArmDataSyncronizationBarrier (); + +} + + diff --git a/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf new file mode 100755 index 000000000..80ada2137 --- /dev/null +++ b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf @@ -0,0 +1,47 @@ +#/** @file +# Component description file for Base PCI Cf8 Library. +# +# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles. +# Layers on top of an I/O Library instance. +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DebugAgentTimerLibNull + FILE_GUID = E82F99DE-74ED-4e56-BBA1-B143FCA3F69A + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DebugAgentTimerLib|SEC BASE DXE_CORE + + +[Sources.common] + DebugAgentTimerLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + ArmPkg/ArmPkg.dec + + +[LibraryClasses] + BaseLib + IoLib + OmapLib + ArmLib + +[Pcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxDebugAgentTimer + gOmap44xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds +
\ No newline at end of file diff --git a/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.c b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.c new file mode 100644 index 000000000..5d7d84052 --- /dev/null +++ b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.c @@ -0,0 +1,72 @@ +/** @file + Add custom commands for PandaBoard development. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiDxe.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/EblCmdLib.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> +#include <Library/EfiFileLib.h> + + +//PcdEmbeddedFdBaseAddress + +/** + Fill Me In + + Argv[0] - "%CommandName%" + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblEdk2Cmd ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + return EFI_SUCCESS; +} + + +GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] = +{ + { + "edk2", + " filename ; Load FD into memory and boot from it", + NULL, + EblEdk2Cmd + } +}; + + +VOID +EblInitializeExternalCmd ( + VOID + ) +{ + EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE)); + return; +} diff --git a/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.inf b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.inf new file mode 100644 index 000000000..456d2c017 --- /dev/null +++ b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.inf @@ -0,0 +1,48 @@ +#/** @file +# Component description file for the entry point to a EFIDXE Drivers +# +# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification +# Copyright (c) 2007 - 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardEblCmdLib + FILE_GUID = ea62bdc3-1063-425f-8851-98cb47f213a8 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + EblCmdLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + +[Protocols] + +[Guids] + +[Pcd] diff --git a/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.c b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.c new file mode 100644 index 000000000..418db6e9d --- /dev/null +++ b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.c @@ -0,0 +1,102 @@ +/** @file + Basic serial IO abstaction for GDB + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> +#include <Library/GdbSerialLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +RETURN_STATUS +EFIAPI +GdbSerialLibConstructor ( + VOID + ) +{ + return RETURN_SUCCESS; +} + +RETURN_STATUS +EFIAPI +GdbSerialInit ( + IN UINT64 BaudRate, + IN UINT8 Parity, + IN UINT8 DataBits, + IN UINT8 StopBits + ) +{ + return RETURN_SUCCESS; +} + +BOOLEAN +EFIAPI +GdbIsCharAvailable ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + + if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { + return TRUE; + } else { + return FALSE; + } +} + +CHAR8 +EFIAPI +GdbGetChar ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 RBR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_RBR_REG; + CHAR8 Char; + + while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); + Char = MmioRead8(RBR); + + return Char; +} + +VOID +EFIAPI +GdbPutChar ( + IN CHAR8 Char + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 THR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_THR_REG; + + while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); + MmioWrite8(THR, Char); +} + +VOID +GdbPutString ( + IN CHAR8 *String + ) +{ + while (*String != '\0') { + GdbPutChar (*String); + String++; + } +} + + + + diff --git a/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf new file mode 100644 index 000000000..34d75b1bd --- /dev/null +++ b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = GdbSerialLib + FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = GdbSerialLib + + CONSTRUCTOR = GdbSerialLibConstructor + + +[Sources.common] + GdbSerialLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + IoLib + OmapLib + +[FixedPcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + diff --git a/Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf b/Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf new file mode 100644 index 000000000..11cf1ad49 --- /dev/null +++ b/Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf @@ -0,0 +1,45 @@ +#/** @file +# Timer library implementation +# +# A non-functional instance of the Timer Library that can be used as a template +# for the implementation of a functional timer library instance. This library instance can +# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer +# services as well as EBC modules that require timer services +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardTimerLib + FILE_GUID = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = TimerLib + +[Sources.common] + TimerLib.c + +[Packages] + Omap44xxPkg/Omap44xxPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DebugLib + OmapLib + IoLib + +[Pcd] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer + diff --git a/Omap44xxPkg/Library/Omap44xxTimerLib/TimerLib.c b/Omap44xxPkg/Library/Omap44xxTimerLib/TimerLib.c new file mode 100644 index 000000000..55b952a39 --- /dev/null +++ b/Omap44xxPkg/Library/Omap44xxTimerLib/TimerLib.c @@ -0,0 +1,145 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> + +#include <Library/BaseLib.h> +#include <Library/TimerLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +RETURN_STATUS +EFIAPI +TimerConstructor ( + VOID + ) +{ + UINTN Timer = PcdGet32(PcdOmap44xxFreeTimer); + UINT32 TimerBaseAddress = TimerBase(Timer); + + // If the DMTIMER3 and DMTIMER4 are not enabled it is probably because it is the first call to TimerConstructor + if ((MmioRead32 (0x4A009440) & 0x3) == 0x0) { + // Enable DMTIMER3 with SYS_CLK source + MmioOr32(0x4A009440, 0x2); + + // Enable DMTIMER4 with SYS_CLK source + MmioOr32(0x4A009448, 0x2); + } + + if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) { + // Set count & reload registers + MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000); + MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000); + + // Disable interrupts + MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE); + + // Start Timer + MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + + /* Sending first command to turn off watchdog */ + MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA); + + /* Wait for write to complete */ + while( MmioBitFieldRead32(WDTIMER2_BASE + WWPS, 4, 5) ); + + /* Sending second command to turn off watchdog */ + MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555); + + /* Wait for write to complete */ + while( MmioBitFieldRead32(WDTIMER2_BASE + WWPS, 4, 5) ); + } + return EFI_SUCCESS; +} + +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + UINT64 NanoSeconds; + + NanoSeconds = MultU64x32(MicroSeconds, 1000); + + while (NanoSeconds > (UINTN)-1) { + NanoSecondDelay((UINTN)-1); + NanoSeconds -= (UINTN)-1; + } + + NanoSecondDelay(NanoSeconds); + + return MicroSeconds; +} + +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + UINT32 Delay; + UINT32 StartTime; + UINT32 CurrentTime; + UINT32 ElapsedTime; + UINT32 TimerCountRegister; + + Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1; + + TimerCountRegister = TimerBase(PcdGet32(PcdOmap44xxFreeTimer)) + GPTIMER_TCRR; + + StartTime = MmioRead32 (TimerCountRegister); + + do + { + CurrentTime = MmioRead32 (TimerCountRegister); + ElapsedTime = CurrentTime - StartTime; + } while (ElapsedTime < Delay); + + NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds); + + return NanoSeconds; +} + +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap44xxFreeTimer)) + GPTIMER_TCRR); +} + +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + // Timer starts with the reload value + *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap44xxFreeTimer)) + GPTIMER_TLDR); + } + + if (EndValue != NULL) { + // Timer counts up to 0xFFFFFFFF + *EndValue = 0xFFFFFFFF; + } + + return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz); +} diff --git a/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.c b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.c new file mode 100755 index 000000000..8926d41b5 --- /dev/null +++ b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.c @@ -0,0 +1,176 @@ +/** @file + Abstractions for simple OMAP DMA channel. + + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/DebugLib.h> +#include <Library/OmapDmaLib.h> +#include <Library/IoLib.h> +#include <Library/BaseMemoryLib.h> +#include <Omap4430/Omap4430.h> + + +/** + Configure OMAP DMA Channel + + @param Channel DMA Channel to configure + @param Dma4 Pointer to structure used to initialize DMA registers for the Channel + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +EnableDmaChannel ( + IN UINTN Channel, + IN OMAP_DMA4 *DMA4 + ) +{ + UINT32 RegVal; + + + if (Channel > DMA4_MAX_CHANNEL) { + return EFI_INVALID_PARAMETER; + } + + /* 1) Configure the transfer parameters in the logical DMA registers */ + /*-------------------------------------------------------------------*/ + + /* a) Set the data type CSDP[1:0], the Read/Write Port access type + CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19], + write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */ + + // Read CSDP + RegVal = MmioRead32 (DMA4_CSDP (Channel)); + + // Build reg + RegVal = ((RegVal & ~ 0x3) | DMA4->DataType ); + RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7)); + RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14)); + RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21)); + RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19)); + RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16)); + RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6)); + RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13)); + // Write CSDP + MmioWrite32 (DMA4_CSDP (Channel), RegVal); + + /* b) Set the number of element per frame CEN[23:0]*/ + MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame); + + /* c) Set the number of frame per block CFN[15:0]*/ + MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock); + + /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/ + MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress); + MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress); + + /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14], + read/write priority CCR[6]/CCR[26] + I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to + LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber + */ + + // Read CCR + RegVal = MmioRead32 (DMA4_CCR (Channel)); + + // Build reg + RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber); + RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19); + RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12)); + RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14)); + RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6)); + RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26)); + + // Write CCR + MmioWrite32 (DMA4_CCR (Channel), RegVal); + + /* f)- Set the source element index CSEI[15:0]*/ + MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex); + + /* - Set the source frame index CSFI[15:0]*/ + MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex); + + + /* - Set the destination element index CDEI[15:0]*/ + MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex); + + /* - Set the destination frame index CDFI[31:0]*/ + MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex); + + MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex); + + // Enable all the status bits since we are polling + MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL); + MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET); + + /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */ + /*--------------------------------------------------------------*/ + //write enable bit + MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer + + return EFI_SUCCESS; +} + +/** + Turn of DMA channel configured by EnableDma(). + + @param Channel DMA Channel to configure + @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS + @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR + + @retval EFI_SUCCESS DMA hardware disabled + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +DisableDmaChannel ( + IN UINTN Channel, + IN UINT32 SuccessMask, + IN UINT32 ErrorMask + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Reg; + + + if (Channel > DMA4_MAX_CHANNEL) { + return EFI_INVALID_PARAMETER; + } + + do { + Reg = MmioRead32 (DMA4_CSR(Channel)); + if ((Reg & ErrorMask) != 0) { + Status = EFI_DEVICE_ERROR; + DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg)); + break; + } + } while ((Reg & SuccessMask) != SuccessMask); + + + // Disable all status bits and clear them + MmioWrite32 (DMA4_CICR (Channel), 0); + MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET); + + MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE)); + return Status; +} + + + diff --git a/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf new file mode 100755 index 000000000..90078e0df --- /dev/null +++ b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OmapDmaLib + FILE_GUID = 09B17D99-BB07-49a8-B0D2-06D6AFCBE3AB + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = OmapDmaLib + + +[Sources.common] + OmapDmaLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + MemoryAllocationLib + UncachedMemoryAllocationLib + IoLib + BaseMemoryLib + ArmLib + + +[Protocols] + gEfiCpuArchProtocolGuid + +[Guids] + +[Pcd] + +[Depex] + gEfiCpuArchProtocolGuid
\ No newline at end of file diff --git a/Omap44xxPkg/Library/OmapLib/OmapLib.c b/Omap44xxPkg/Library/OmapLib/OmapLib.c new file mode 100644 index 000000000..5b7629074 --- /dev/null +++ b/Omap44xxPkg/Library/OmapLib/OmapLib.c @@ -0,0 +1,85 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/DebugLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +UINT32 +GpioBase ( + IN UINTN Port + ) +{ + switch (Port) { + case 1: return GPIO1_BASE; + case 2: return GPIO2_BASE; + case 3: return GPIO3_BASE; + case 4: return GPIO4_BASE; + case 5: return GPIO5_BASE; + case 6: return GPIO6_BASE; + default: ASSERT(FALSE); return 0; + } +} + +UINT32 +TimerBase ( + IN UINTN Timer + ) +{ + switch (Timer) { + case 1: return GPTIMER1_BASE; + case 2: return GPTIMER2_BASE; + case 3: return GPTIMER3_BASE; + case 4: return GPTIMER4_BASE; + case 5: return GPTIMER5_BASE; + case 6: return GPTIMER6_BASE; + case 7: return GPTIMER7_BASE; + case 8: return GPTIMER8_BASE; + case 9: return GPTIMER9_BASE; + case 10: return GPTIMER10_BASE; + case 11: return GPTIMER11_BASE; + case 12: return GPTIMER12_BASE; + default: return 0; + } +} + +UINTN +InterruptVectorForTimer ( + IN UINTN Timer + ) +{ + if ((Timer < 1) || (Timer > 12)) { + ASSERT(FALSE); + return 0xFFFFFFFF; + } + + /* OD: On OMAP4, gic peripheral interrupts start at id 32 */ + /* return 36 + Timer; */ + return 32 + 36 + Timer; +} + +UINT32 +UartBase ( + IN UINTN Uart + ) +{ + switch (Uart) { + case 1: return UART1_BASE; + case 2: return UART2_BASE; + case 3: return UART3_BASE; + default: ASSERT(FALSE); return 0; + } +} + diff --git a/Omap44xxPkg/Library/OmapLib/OmapLib.inf b/Omap44xxPkg/Library/OmapLib/OmapLib.inf new file mode 100644 index 000000000..a92fc7791 --- /dev/null +++ b/Omap44xxPkg/Library/OmapLib/OmapLib.inf @@ -0,0 +1,37 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OmapLib + FILE_GUID = d035f5c2-1b92-4746-9f6c-5ff6202970df + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = OmapLib + +[Sources.common] + OmapLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + +[Protocols] + +[Guids] + +[Pcd] diff --git a/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c new file mode 100644 index 000000000..b215b5512 --- /dev/null +++ b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c @@ -0,0 +1,303 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Uefi.h> + +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> + +#include <Protocol/RealTimeClock.h> +#include <Protocol/EmbeddedExternalDevice.h> + +#include <Omap4430/Omap4430.h> +#include <TWL6030.h> + + +EMBEDDED_EXTERNAL_DEVICE *gTWL6030; +INT16 TimeZone = EFI_UNSPECIFIED_TIMEZONE; + +/** + Returns the current time and date information, and the time-keeping capabilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot of the current time. + @param Capabilities An optional pointer to a buffer to receive the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Data; + EFI_TPL OldTpl; + + if (Time == NULL) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + + /* Get time and date */ + ZeroMem(Time, sizeof(EFI_TIME)); + + // Latch values + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Data |= BIT6; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + // Read registers + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Year = 2000 + ((Data >> 4) & 0xF) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Month = ((Data >> 4) & 0x1) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Day = ((Data >> 4) & 0x3) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Hour = ((Data >> 4) & 0x3) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Minute = ((Data >> 4) & 0x7) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Second = ((Data >> 4) & 0x7) * 10 + (Data & 0xF); + + Time->TimeZone = TimeZone; + // TODO: check what to use here + Time->Daylight = EFI_TIME_ADJUST_DAYLIGHT; + + // Set capabilities + + // TODO: Set real capabilities + if (Capabilities != NULL) { + Capabilities->Resolution = 1; + Capabilities->Accuracy = 50000000; + Capabilities->SetsToZero = FALSE; + } + +EXIT: + gBS->RestoreTPL(OldTpl); + + return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + EFI_STATUS Status; + UINT8 Data; + UINT8 MonthDayCount[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + EFI_TPL OldTpl; + + // Input validation according both to UEFI spec and hardware constraints + // UEFI spec says valid year range is 1900-9999 but TPS only supports 2000-2099 + if ( (Time == NULL) + || (Time->Year < 2000 || Time->Year > 2099) + || (Time->Month < 1 || Time->Month > 12) + || (Time->Day < 1 || Time->Day > MonthDayCount[Time->Month]) + || (Time->Hour > 23) + || (Time->Minute > 59) + || (Time->Second > 59) + || (Time->Nanosecond > 999999999) + || ((Time->TimeZone < -1440 || Time->TimeZone > 1440) && Time->TimeZone != 2047) + ) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + + Data = Time->Year - 2000; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Month / 10) << 4) | (Time->Month % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Day / 10) << 4) | (Time->Day % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Hour / 10) << 4) | (Time->Hour % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Minute / 10) << 4) | (Time->Minute % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Second / 10) << 4) | (Time->Second % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + TimeZone = Time->TimeZone; + +EXIT: + gBS->RestoreTPL(OldTpl); + + return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR; +} + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enabled or disabled. + @param Pending Indicates if the alarm signal is pending and requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wakeup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If + Enable is FALSE, then the wakeup alarm was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This is the declaration of an EFI image entry point. This can be the entry point to an application + written to this specification, an EFI boot service driver, or an EFI runtime driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // TODO: adapt to Panda +#if 0 + UINT8 Data; + EFI_TPL OldTpl; +#endif + + Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTWL6030); + ASSERT_EFI_ERROR(Status); + +#if 0 + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + Data = 1; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data); + ASSERT_EFI_ERROR(Status); + gBS->RestoreTPL(OldTpl); +#endif + + // Setup the setters and getters + gRT->GetTime = LibGetTime; + gRT->SetTime = LibSetTime; + gRT->GetWakeupTime = LibGetWakeupTime; + gRT->SetWakeupTime = LibSetWakeupTime; + + // Install the protocol + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiRealTimeClockArchProtocolGuid, NULL, + NULL + ); + + return Status; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + return; +} diff --git a/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf new file mode 100755 index 000000000..b1fa82a33 --- /dev/null +++ b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf @@ -0,0 +1,38 @@ +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RealTimeClockLib + FILE_GUID = EC1713DB-7DB5-4c99-8FE2-6F52F95A1132 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RealTimeClockLib + +[Sources.common] + RealTimeClockLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + IoLib + UefiLib + DebugLib + PcdLib + +[Protocols] + gEmbeddedExternalDeviceProtocolGuid + +[depex] + gEmbeddedExternalDeviceProtocolGuid diff --git a/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.c b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 000000000..a2af61264 --- /dev/null +++ b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,90 @@ +/** @file + Template library implementation to support ResetSystem Runtime call. + + Fill in the templates with what ever makes you system reset. + + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include <PiDxe.h> + +#include <Library/PcdLib.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/EfiResetSystemLib.h> + + +/** + Resets the entire platform. + + @param ResetType The type of reset to perform. + @param ResetStatus The status code for the reset. + @param DataSize The size, in bytes, of WatchdogData. + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or + EfiResetShutdown the data buffer starts with a Null-terminated + Unicode string, optionally followed by additional binary data. + +**/ +EFI_STATUS +EFIAPI +LibResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN CHAR16 *ResetData OPTIONAL + ) +{ + if (ResetData != NULL) { + DEBUG((EFI_D_ERROR, "%s", ResetData)); + } + + switch (ResetType) { + case EfiResetWarm: + // Map a warm reset into a cold reset + case EfiResetCold: + case EfiResetShutdown: + default: + // Perform cold reset of the system. + MmioOr32 (PRM_RSTCTRL, RST_DPLL3); + while ((MmioRead32 (PRM_RSTST) & GLOBAL_COLD_RST) != 0x1); + break; + } + + // If the reset didn't work, return an error. + ASSERT (FALSE); + return EFI_DEVICE_ERROR; +} + + + +/** + Initialize any infrastructure required for LibResetSystem () to function. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +LibInitializeResetSystem ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} + diff --git a/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.inf b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 000000000..986ddb551 --- /dev/null +++ b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,40 @@ +#/** @file +# Reset System lib to make it easy to port new platforms +# +# Copyright (c) 2008, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardResetSystemLib + FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = EfiResetSystemLib + + +[Sources.common] + ResetSystemLib.c + +[Packages] + Omap44xxPkg/Omap44xxPkg.dec + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[Pcd.common] + gArmTokenSpaceGuid.PcdCpuResetAddress + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress + +[LibraryClasses] + DebugLib + PandaBoardSystemLib diff --git a/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.c b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.c new file mode 100644 index 000000000..9162c6c84 --- /dev/null +++ b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.c @@ -0,0 +1,155 @@ +/** @file + Serial I/O Port library functions with no library constructor/destructor + + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/DebugLib.h> +#include <Library/SerialPortLib.h> +#include <Library/SerialPortExtLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +/* + + Programmed hardware of Serial port. + + @return Always return EFI_UNSUPPORTED. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINTN Uart = PcdGet32(PcdOmap44xxConsoleUart); + UINT32 UartBaseAddress = UartBase(Uart); + + // Configure UART3 pads + MmioAnd32(0x4A100144, ~0x70007); + + // Enable UART3 clocks + MmioOr32(0x4A009550, 0x2); + + // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers. + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE); + + // Put device in configuration mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE); + + // Programmable divisor N = 48Mhz/16/115200 = 26 + MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000 / PcdGet64 (PcdUartDefaultBaudRate)); // low divisor + MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor + + // Enter into UART operational mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8); + + // Force DTR and RTS output to active + MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE); + + // Clear & enable fifos + MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); + + // Restore MODE_SELECT + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X); + + return RETURN_SUCCESS; +} + +/** + Write data to serial device. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes writed to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 THR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_THR_REG; + UINTN Count; + + for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { + while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); + MmioWrite8(THR, *Buffer); + } + + return NumberOfBytes; +} + + +/** + Read data from serial device and save the datas in buffer. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval 0 Read data failed. + @retval !0 Aactual number of bytes read from serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 RBR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_RBR_REG; + UINTN Count; + + for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { + while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); + *Buffer = MmioRead8(RBR); + } + + return NumberOfBytes; +} + + +/** + Check to see if any data is avaiable to be read from the debug device. + + @retval EFI_SUCCESS At least one byte of data is avaiable to be read + @retval EFI_NOT_READY No data is avaiable to be read + @retval EFI_DEVICE_ERROR The serial device is not functioning properly + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + + if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { + return TRUE; + } else { + return FALSE; + } +} + diff --git a/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf new file mode 100644 index 000000000..07db0f837 --- /dev/null +++ b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf @@ -0,0 +1,44 @@ +#/** @file +# EDK Serial port lib +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardSerialPortLib + FILE_GUID = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerialPortLib + + +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + SerialPortLib.c + +[LibraryClasses] + DebugLib + IoLib + OmapLib + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[FixedPcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate diff --git a/Omap44xxPkg/MmcHostDxe/MmcHostDxe.c b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.c new file mode 100644 index 000000000..f2ac0bbcc --- /dev/null +++ b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.c @@ -0,0 +1,697 @@ +/** @file +* +* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved. +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "MmcHostDxe.h" + +EMBEDDED_EXTERNAL_DEVICE *gTWL6030; +UINT8 mMaxDataTransferRate = 0; +UINT32 mRca = 0; +BOOLEAN mBitModeSet = FALSE; + + +typedef struct { + VENDOR_DEVICE_PATH Mmc; + EFI_DEVICE_PATH End; +} MMCHS_DEVICE_PATH; + +MMCHS_DEVICE_PATH gMMCDevicePath = { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + (UINT8)(sizeof(VENDOR_DEVICE_PATH)), + (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8), + 0xb615f1f5, 0x5088, 0x43cd, 0x80, 0x9c, 0xa1, 0x6e, 0x52, 0x48, 0x7d, 0x00 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } +}; + +BOOLEAN +IgnoreCommand ( + UINT32 Command + ) +{ + switch(Command) { + case MMC_CMD12: + return TRUE; + case MMC_CMD13: + return TRUE; + default: + return FALSE; + } +} + +UINT32 +TranslateCommand ( + UINT32 Command + ) +{ + UINT32 Translation; + + switch(Command) { + case MMC_CMD2: + Translation = CMD2; + break; + case MMC_CMD3: + Translation = CMD3; + break; + /*case MMC_CMD6: + Translation = CMD6; + break;*/ + case MMC_CMD7: + Translation = CMD7; + break; + case MMC_CMD8: + Translation = CMD8; + break; + case MMC_CMD9: + Translation = CMD9; + break; + /*case MMC_CMD12: + Translation = CMD12; + break; + case MMC_CMD13: + Translation = CMD13; + break;*/ + case MMC_CMD16: + Translation = CMD16; + break; + case MMC_CMD17: + Translation = 0x113A0014;//CMD17; + break; + case MMC_CMD24: + Translation = CMD24 | 4; + break; + case MMC_CMD55: + Translation = CMD55; + break; + case MMC_ACMD41: + Translation = ACMD41; + break; + default: + Translation = Command; + } + + return Translation; +} + +VOID +CalculateCardCLKD ( + UINTN *ClockFrequencySelect + ) +{ + UINTN TransferRateValue = 0; + UINTN TimeValue = 0 ; + UINTN Frequency = 0; + + DEBUG ((DEBUG_BLKIO, "CalculateCardCLKD()\n")); + + // For SD Cards we would need to send CMD6 to set + // speeds abouve 25MHz. High Speed mode 50 MHz and up + + // Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED) + switch (mMaxDataTransferRate & 0x7) { // 2 + case 0: + TransferRateValue = 100 * 1000; + break; + + case 1: + TransferRateValue = 1 * 1000 * 1000; + break; + + case 2: + TransferRateValue = 10 * 1000 * 1000; + break; + + case 3: + TransferRateValue = 100 * 1000 * 1000; + break; + + default: + DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n")); + ASSERT(FALSE); + return; + } + + //Calculate Time value (Bits 6:3 of TRAN_SPEED) + switch ((mMaxDataTransferRate >> 3) & 0xF) { // 6 + case 1: + TimeValue = 10; + break; + + case 2: + TimeValue = 12; + break; + + case 3: + TimeValue = 13; + break; + + case 4: + TimeValue = 15; + break; + + case 5: + TimeValue = 20; + break; + + case 6: + TimeValue = 25; + break; + + case 7: + TimeValue = 30; + break; + + case 8: + TimeValue = 35; + break; + + case 9: + TimeValue = 40; + break; + + case 10: + TimeValue = 45; + break; + + case 11: + TimeValue = 50; + break; + + case 12: + TimeValue = 55; + break; + + case 13: + TimeValue = 60; + break; + + case 14: + TimeValue = 70; + break; + + case 15: + TimeValue = 80; + break; + + default: + DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n")); + ASSERT(FALSE); + return; + } + + Frequency = TransferRateValue * TimeValue/10; + + // Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field. + *ClockFrequencySelect = ((MMC_REFERENCE_CLK/Frequency) + 1); + + DEBUG ((DEBUG_BLKIO, "mMaxDataTransferRate: 0x%x, Frequency: %d KHz, ClockFrequencySelect: %x\n", mMaxDataTransferRate, Frequency/1000, *ClockFrequencySelect)); +} + +VOID +UpdateMMCHSClkFrequency ( + UINTN NewCLKD + ) +{ + DEBUG ((DEBUG_BLKIO, "UpdateMMCHSClkFrequency()\n")); + + // Set Clock enable to 0x0 to not provide the clock to the card + MmioAnd32 (MMCHS_SYSCTL, ~CEN); + + // Set new clock frequency. + MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6); + + // Poll till Internal Clock Stable + while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS); + + // Set Clock enable to 0x1 to provide the clock to the card + MmioOr32 (MMCHS_SYSCTL, CEN); +} + +EFI_STATUS +InitializeMMCHS ( + VOID + ) +{ + UINT8 Data; + EFI_STATUS Status; + + DEBUG ((DEBUG_BLKIO, "InitializeMMCHS()\n")); + + // Disconnect PBIAS prior to voltage change + MmioAnd32 (CONTROL_PBIAS_LITE, ~(PBIASPWRDNZ | PBIASLITEPWRDNZ)); + + // Disable VMMC LDO + Data = VMMC_CFG_STATE_OFF; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, VMMC_CFG_STATE), 1, &Data); + ASSERT_EFI_ERROR(Status); + + // Wait for stabilization + gBS->Stall(500); + + // Configure VMMC LDO to output 3.0 voltage. + Data = VSEL_3_00V; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, VMMC_CFG_VOLTAGE), 1, &Data); + ASSERT_EFI_ERROR(Status); + + // Enable VMMC LDO + Data = VMMC_CFG_STATE_ON; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, VMMC_CFG_STATE), 1, &Data); + ASSERT_EFI_ERROR(Status); + + // Wait for stabilization + gBS->Stall(500); + + // PBIAS in normal operating mode (not HiZ) + MmioAnd32 (CONTROL_PBIAS_LITE, ~PBIASHIZ); + + // Select VMODE=3V and connect VDDS_MMC1 to PBIAS + MmioOr32 (CONTROL_PBIAS_LITE, (PBIASVMODE3V|PBIASLITEPWRDNZ)); + + // Wait for PBIAS supply detection + gBS->Stall(100); + + // Connect pads + MmioOr32 (CONTROL_PBIAS_LITE, PBIASPWRDNZ); + + // Stop here if supply detector did not sense 3V + ASSERT( !(MmioRead32(CONTROL_PBIAS_LITE) & PBIASVMODEERR) ); + + return Status; +} + +BOOLEAN +MMCIsCardPresent ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINT8 Data; + + // + // Card detect is a GPIO0 on the TWL6030 + // + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, MMCCTRL), 1, &Data); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return !(Data & CARD_DET_STS_MMC); + +} + +BOOLEAN +MMCIsReadOnly ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + /* Note: + * On our BeagleBoard the SD card WP pin is always read as TRUE. + * Probably something wrong with GPIO configuration. + * BeagleBoard-xM uses microSD cards so there is no write protect at all. + * Hence commenting out SD card WP pin read status. + */ + //return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23; + return 0; + +} + +// TODO +EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID; + +EFI_STATUS +MMCBuildDevicePath ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode; + + NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH)); + CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid); + *DevicePath = NewDevicePathNode; + return EFI_SUCCESS; +} + +EFI_STATUS +MMCSendCommand ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_CMD MmcCmd, + IN UINT32 Argument + ) +{ + UINTN MmcStatus; + UINTN RetryCount = 0; + + if (IgnoreCommand(MmcCmd)) + return EFI_SUCCESS; + + MmcCmd = TranslateCommand(MmcCmd); + + //DEBUG ((EFI_D_ERROR, "MMCSendCommand(%d)\n", MmcCmd)); + + // Check if command line is in use or not. Poll till command line is available. + while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED); + + // Provide the block size. + MmioWrite32 (MMCHS_BLK, BLEN_512BYTES); + + // Setting Data timeout counter value to max value. + MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL); + + // Clear Status register. + MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF); + + // Set command argument register + MmioWrite32 (MMCHS_ARG, Argument); + + //TODO: fix this + //Enable interrupt enable events to occur + //MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal); + + // Send a command + MmioWrite32 (MMCHS_CMD, MmcCmd); + + // Check for the command status. + while (RetryCount < MAX_RETRY_COUNT) { + do { + MmcStatus = MmioRead32 (MMCHS_STAT); + } while (MmcStatus == 0); + + // Read status of command response + if ((MmcStatus & ERRI) != 0) { + + // Perform soft-reset for mmci_cmd line. + MmioOr32 (MMCHS_SYSCTL, SRC); + while ((MmioRead32 (MMCHS_SYSCTL) & SRC)); + + //DEBUG ((EFI_D_INFO, "MmcStatus: 0x%x\n", MmcStatus)); + return EFI_DEVICE_ERROR; + } + + // Check if command is completed. + if ((MmcStatus & CC) == CC) { + MmioWrite32 (MMCHS_STAT, CC); + break; + } + + RetryCount++; + } + + if (RetryCount == MAX_RETRY_COUNT) { + DEBUG ((DEBUG_BLKIO, "MMCSendCommand: Timeout\n")); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MMCNotifyState ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_STATE State + ) +{ + EFI_STATUS Status; + UINTN FreqSel; + + switch(State) { + case MmcInvalidState: + ASSERT(0); + break; + case MmcHwInitializationState: + mBitModeSet = FALSE; + + DEBUG ((DEBUG_BLKIO, "MMCHwInitializationState()\n")); + Status = InitializeMMCHS (); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_BLKIO, "Initialize MMC host controller fails. Status: %x\n", Status)); + return Status; + } + + // Software reset of the MMCHS host controller. + MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET); + gBS->Stall(1000); + while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE); + + // Soft reset for all. + MmioWrite32 (MMCHS_SYSCTL, SRA); + gBS->Stall(1000); + while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0); + + //Voltage capabilities initialization. Activate VS18 and VS30. + MmioOr32 (MMCHS_CAPA, (VS30 | VS18)); + + // Wakeup configuration + MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP); + MmioOr32 (MMCHS_HCTL, IWE); + + // MMCHS Controller default initialization + MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF)); + + MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF)); + + // Enable internal clock + MmioOr32 (MMCHS_SYSCTL, ICE); + + // Set the clock frequency to 80KHz. + UpdateMMCHSClkFrequency (CLKD_80KHZ); + + // Enable SD bus power. + MmioOr32 (MMCHS_HCTL, (SDBP_ON)); + + // Poll till SD bus power bit is set. + while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON); + + // Enable interrupts. + MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN | + CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN)); + + // Controller INIT procedure start. + MmioOr32 (MMCHS_CON, INIT); + MmioWrite32 (MMCHS_CMD, 0x00000000); + while (!(MmioRead32 (MMCHS_STAT) & CC)); + + // Wait for 1 ms + gBS->Stall (1000); + + // Set CC bit to 0x1 to clear the flag + MmioOr32 (MMCHS_STAT, CC); + + // Retry INIT procedure. + MmioWrite32 (MMCHS_CMD, 0x00000000); + while (!(MmioRead32 (MMCHS_STAT) & CC)); + + // End initialization sequence + MmioAnd32 (MMCHS_CON, ~INIT); + + MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON)); + + // Change clock frequency to 400KHz to fit protocol + UpdateMMCHSClkFrequency(CLKD_400KHZ); + + MmioOr32 (MMCHS_CON, OD); + break; + case MmcIdleState: + break; + case MmcReadyState: + break; + case MmcIdentificationState: + break; + case MmcStandByState: + CalculateCardCLKD (&FreqSel); + UpdateMMCHSClkFrequency (FreqSel); + break; + case MmcTransferState: + if (!mBitModeSet) { + Status = MMCSendCommand (This, CMD55, mRca << 16); + if (!EFI_ERROR (Status)) { + // Set device into 4-bit data bus mode + Status = MMCSendCommand (This, ACMD6, 0x2); + if (!EFI_ERROR (Status)) { + // Set host controler into 4-bit mode + MmioOr32 (MMCHS_HCTL, DTW_4_BIT); + DEBUG ((DEBUG_BLKIO, "SD Memory Card set to 4-bit mode\n")); + mBitModeSet = TRUE; + } + } + } + break; + case MmcSendingDataState: + break; + case MmcReceiveDataState: + break; + case MmcProgrammingState: + break; + case MmcDisconnectState: + default: + ASSERT(0); + } + return EFI_SUCCESS; +} + +EFI_STATUS +MMCReceiveResponse ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_RESPONSE_TYPE Type, + IN UINT32* Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Type == MMC_RESPONSE_TYPE_R2) { + Buffer[0] = MmioRead32 (MMCHS_RSP10); + Buffer[1] = MmioRead32 (MMCHS_RSP32); + Buffer[2] = MmioRead32 (MMCHS_RSP54); + Buffer[3] = MmioRead32 (MMCHS_RSP76); + } else { + Buffer[0] = MmioRead32 (MMCHS_RSP10); + } + + if (Type == MMC_RESPONSE_TYPE_CSD) { + mMaxDataTransferRate = Buffer[3] & 0xFF; + } else if (Type == MMC_RESPONSE_TYPE_RCA) { + mRca = Buffer[0] >> 16; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MMCReadBlockData ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINT32* Buffer + ) +{ + UINTN MmcStatus; + UINTN Count; + UINTN RetryCount = 0; + + DEBUG ((DEBUG_BLKIO, "MMCReadBlockData(LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n", Lba, Length, Buffer)); + + // Check controller status to make sure there is no error. + while (RetryCount < MAX_RETRY_COUNT) { + do { + // Read Status. + MmcStatus = MmioRead32 (MMCHS_STAT); + } while(MmcStatus == 0); + + // Check if Buffer read ready (BRR) bit is set? + if (MmcStatus & BRR) { + + // Clear BRR bit + MmioOr32 (MMCHS_STAT, BRR); + + for (Count = 0; Count < Length / 4; Count++) { + *Buffer++ = MmioRead32(MMCHS_DATA); + } + break; + } + RetryCount++; + } + + if (RetryCount == MAX_RETRY_COUNT) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MMCWriteBlockData ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINT32* Buffer + ) +{ + UINTN MmcStatus; + UINTN Count; + UINTN RetryCount = 0; + + // Check controller status to make sure there is no error. + while (RetryCount < MAX_RETRY_COUNT) { + do { + // Read Status. + MmcStatus = MmioRead32 (MMCHS_STAT); + } while(MmcStatus == 0); + + // Check if Buffer write ready (BWR) bit is set? + if (MmcStatus & BWR) { + + // Clear BWR bit + MmioOr32 (MMCHS_STAT, BWR); + + // Write block worth of data. + for (Count = 0; Count < Length / 4; Count++) { + MmioWrite32 (MMCHS_DATA, *Buffer++); + } + + break; + } + RetryCount++; + } + + if (RetryCount == MAX_RETRY_COUNT) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_MMC_HOST_PROTOCOL gMMCHost = { + MMC_HOST_PROTOCOL_REVISION, + MMCIsCardPresent, + MMCIsReadOnly, + MMCBuildDevicePath, + MMCNotifyState, + MMCSendCommand, + MMCReceiveResponse, + MMCReadBlockData, + MMCWriteBlockData +}; + +EFI_STATUS +MMCInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle = NULL; + + DEBUG ((DEBUG_BLKIO, "MMCInitialize()\n")); + + Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTWL6030); + ASSERT_EFI_ERROR(Status); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiMmcHostProtocolGuid, &gMMCHost, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Omap44xxPkg/MmcHostDxe/MmcHostDxe.h b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.h new file mode 100755 index 000000000..4b9da8527 --- /dev/null +++ b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.h @@ -0,0 +1,44 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef _MMC_HOST_DXE_H_ +#define _MMC_HOST_DXE_H_ + +#include <Uefi.h> + +#include <Library/BaseLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/OmapLib.h> +#include <Library/OmapDmaLib.h> +#include <Library/DmaLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/BlockIo.h> +#include <Protocol/DevicePath.h> +#include <Protocol/MmcHost.h> + +#include <Omap4430/Omap4430.h> +#include <TWL6030.h> + +#define MAX_RETRY_COUNT (100*5) + +extern EFI_BLOCK_IO_PROTOCOL gBlockIo; + +#endif diff --git a/Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf new file mode 100755 index 000000000..72a498287 --- /dev/null +++ b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf @@ -0,0 +1,53 @@ +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MMC + FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = MMCInitialize + + +[Sources.common] + MmcHostDxe.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + PcdLib + UefiLib + UefiDriverEntryPoint + MemoryAllocationLib + IoLib + OmapDmaLib + DmaLib + +[Guids] + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiCpuArchProtocolGuid + gEfiDevicePathProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + gEfiMmcHostProtocolGuid + +[Pcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxMMCHS1Base + gOmap44xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds + +[depex] + gEmbeddedExternalDeviceProtocolGuid diff --git a/Omap44xxPkg/Omap44xxPkg.dec b/Omap44xxPkg/Omap44xxPkg.dec new file mode 100644 index 000000000..4a2a47e20 --- /dev/null +++ b/Omap44xxPkg/Omap44xxPkg.dec @@ -0,0 +1,58 @@ +#/** @file +# Omap44xx SoC package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Omap44xxPkg + PACKAGE_GUID = D196A631-B7B7-4953-A3EE-0F773CBABF20 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[LibraryClasses] + ## @libraryclass Abstract location of basic OMAP components + ## + OmapLib|Include/Library/OmapLib.h + + ## @libraryclass Abstract OMAP and ARM DMA, modeled after PCI IO protocol + ## + OmapDmaLib|Include/Library/OmapDmaLib.h + + +[Guids.common] + gOmap44xxTokenSpaceGuid = { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} } + +[PcdsFeatureFlag.common] + +[PcdsFixedAtBuild.common] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart|3|UINT32|0x00000202 + gOmap44xxTokenSpaceGuid.PcdOmap44xxGpmcOffset|0x00000000|UINT32|0x00000203 + gOmap44xxTokenSpaceGuid.PcdOmap44xxMMCHS1Base|0x00000000|UINT32|0x00000204 + gOmap44xxTokenSpaceGuid.PcdOmap44xxArchTimer|3|UINT32|0x00000205 + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer|4|UINT32|0x00000206 + gOmap44xxTokenSpaceGuid.PcdOmap44xxDebugAgentTimer|5|UINT32|0x00000207 + gOmap44xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds|77|UINT32|0x00000208 + gOmap44xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds|1000000|UINT32|0x00000209 + diff --git a/Omap44xxPkg/Omap44xxPkg.dsc b/Omap44xxPkg/Omap44xxPkg.dsc new file mode 100644 index 000000000..a7fa9375a --- /dev/null +++ b/Omap44xxPkg/Omap44xxPkg.dsc @@ -0,0 +1,183 @@ +#/** @file +# Omap44xx SoC package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Omap44xxPkg + PLATFORM_GUID = D196A631-B7B7-4953-A3EE-0F773CBABF20 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/Omap44xxPkg + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + DEFINE TARGET_HACK = DEBUG + + +[LibraryClasses.common] + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OmapLib|Omap44xxPkg/Library/OmapLib/OmapLib.inf + OmapDmaLib|Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf + + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + +# +# Assume everything is fixed at build +# + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf + UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf + + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + + +[LibraryClasses.ARM] + # + # Note: This NULL library feature is not yet in theBaseTools, but it is checked in to + # the BaseTools project. So you need to build with the BaseTools project util this feature gets synced. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + +[BuildOptions] + XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 + XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 + XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 + + GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb + GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a + + RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu 7-A + RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu 7-A + + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + + +[PcdsFixedAtBuild.common] + +# DEBUG_ASSERT_ENABLED 0x01 +# DEBUG_PRINT_ENABLED 0x02 +# DEBUG_CODE_ENABLED 0x04 +# CLEAR_MEMORY_ENABLED 0x08 +# ASSERT_BREAKPOINT_ENABLED 0x10 +# ASSERT_DEADLOOP_ENABLED 0x20 + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f + +# DEBUG_INIT 0x00000001 // Initialization +# DEBUG_WARN 0x00000002 // Warnings +# DEBUG_LOAD 0x00000004 // Load events +# DEBUG_FS 0x00000008 // EFI File system +# DEBUG_POOL 0x00000010 // Alloc & Free's +# DEBUG_PAGE 0x00000020 // Alloc & Free's +# DEBUG_INFO 0x00000040 // Verbose +# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers +# DEBUG_VARIABLE 0x00000100 // Variable +# DEBUG_BM 0x00000400 // Boot Manager +# DEBUG_BLKIO 0x00001000 // BlkIo Driver +# DEBUG_NET 0x00004000 // SNI Driver +# DEBUG_UNDI 0x00010000 // UNDI Driver +# DEBUG_LOADFILE 0x00020000 // UNDI Driver +# DEBUG_EVENT 0x00080000 // Event messages +# DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0 + gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0 + gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0 + gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0 + gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0 + gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000 + gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000 + + gOmap44xxTokenSpaceGuid.PcdOmap44xxGpmcOffset|0x50000000 + gOmap44xxTokenSpaceGuid.PcdOmap44xxMMCHS1Base|0x4809C000 + + # Console + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart|3 + + # Timers + gOmap44xxTokenSpaceGuid.PcdOmap44xxArchTimer|3 + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer|4 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|26 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|38400000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf + Omap44xxPkg/Library/OmapLib/OmapLib.inf + Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf + Omap44xxPkg/SmbusDxe/Smbus.inf + Omap44xxPkg/Gpio/Gpio.inf + Omap44xxPkg/TimerDxe/TimerDxe.inf + Omap44xxPkg/TPS65950Dxe/TPS65950.inf + + + diff --git a/Omap44xxPkg/PciEmulation/PciEmulation.c b/Omap44xxPkg/PciEmulation/PciEmulation.c new file mode 100644 index 000000000..2a2fcd58e --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciEmulation.c @@ -0,0 +1,498 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciEmulation.h" + +EMBEDDED_EXTERNAL_DEVICE *gTWL6030; + +#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44 + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + PCI_DEVICE_PATH PciDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_IO_DEVICE_PATH; + +typedef struct { + UINT32 Signature; + EFI_PCI_IO_DEVICE_PATH DevicePath; + EFI_PCI_IO_PROTOCOL PciIoProtocol; + PCI_TYPE00 *ConfigSpace; + PCI_ROOT_BRIDGE RootBridge; + UINTN Segment; +} EFI_PCI_IO_PRIVATE_DATA; + +#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o') +#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE) + +EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate = +{ + { + { ACPI_DEVICE_PATH, ACPI_DP, sizeof (ACPI_HID_DEVICE_PATH), 0}, + EISA_PNP_ID(0x0A03), // HID + 0 // UID + }, + { + { HARDWARE_DEVICE_PATH, HW_PCI_DP, sizeof (PCI_DEVICE_PATH), 0}, + 0, + 0 + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} +}; + +STATIC +VOID +ConfigureUSBHost ( + VOID + ) +{ + // Take USB host out of force-standby mode + MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_STANDBYMODE_NO_STANDBY + | UHH_SYSCONFIG_IDLEMODE_NO_IDLE); + MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT + | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT + | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE + | UHH_HOSTCONFIG_ENA_INCR16_ENABLE + | UHH_HOSTCONFIG_ENA_INCR8_ENABLE + | UHH_HOSTCONFIG_ENA_INCR4_ENABLE + | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON + | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE); + + // fref auxclk3 feeds USB3320 ULPI/DPDM converter with 19.2 MHz square clock + MmioWrite32 (SCRM_AUXCLK3, SCRM_AUXCLK3_VAL); + + // USB3320 and LAN9514 reset (HUB_NRESET: GPIO 62 - Port 2 pin 30 output high) + MmioAnd32 (GPIO2_BASE + GPIO_OE, ~BIT30); + MmioOr32 (GPIO2_BASE + GPIO_SETDATAOUT, BIT30); + + // Enable power to USB hub (HUB_NPD: GPIO1 - Port 1 pin 1 output high) + MmioAnd32 (GPIO1_BASE + GPIO_OE, ~BIT1); + MmioOr32 (GPIO1_BASE + GPIO_SETDATAOUT, BIT1); +} + +EFI_STATUS +PciIoPollMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoPollIo ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMemRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemRead (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Private->ConfigSpace->Device.Bar[BarIndex] + Offset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoMemWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Private->ConfigSpace->Device.Bar[BarIndex] + Offset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoIoRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoIoWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoPciRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, + Count, + TRUE, + (PTR)(UINTN)Buffer, + TRUE, + (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) + ); +} + +EFI_STATUS +PciIoPciWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Count, + TRUE, + (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), + TRUE, + (PTR)(UINTN)Buffer + ); +} + +EFI_STATUS +PciIoCopyMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 DestBarIndex, + IN UINT64 DestOffset, + IN UINT8 SrcBarIndex, + IN UINT64 SrcOffset, + IN UINTN Count + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + DMA_MAP_OPERATION DmaOperation; + + if (Operation == EfiPciIoOperationBusMasterRead) { + DmaOperation = MapOperationBusMasterRead; + } else if (Operation == EfiPciIoOperationBusMasterWrite) { + DmaOperation = MapOperationBusMasterWrite; + } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) { + DmaOperation = MapOperationBusMasterCommonBuffer; + } else { + return EFI_INVALID_PARAMETER; + } + return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping); +} + +EFI_STATUS +PciIoUnmap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN VOID *Mapping + ) +{ + return DmaUnmap (Mapping); +} + +EFI_STATUS +PciIoAllocateBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) { + // Check this + return EFI_UNSUPPORTED; + } + + return DmaAllocateBuffer (MemoryType, Pages, HostAddress); +} + + +EFI_STATUS +PciIoFreeBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + return DmaFreeBuffer (Pages, HostAddress); +} + + +EFI_STATUS +PciIoFlush ( + IN EFI_PCI_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoGetLocation ( + IN EFI_PCI_IO_PROTOCOL *This, + OUT UINTN *SegmentNumber, + OUT UINTN *BusNumber, + OUT UINTN *DeviceNumber, + OUT UINTN *FunctionNumber + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + if (SegmentNumber != NULL) { + *SegmentNumber = Private->Segment; + } + + if (BusNumber != NULL) { + *BusNumber = 0xff; + } + + if (DeviceNumber != NULL) { + *DeviceNumber = 0; + } + + if (FunctionNumber != NULL) { + *FunctionNumber = 0; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, + IN UINT64 Attributes, + OUT UINT64 *Result OPTIONAL + ) +{ + switch (Operation) { + case EfiPciIoAttributeOperationGet: + case EfiPciIoAttributeOperationSupported: + if (Result == NULL) { + return EFI_INVALID_PARAMETER; + } + // We are not a real PCI device so just say things we kind of do + *Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE; + break; + + case EfiPciIoAttributeOperationSet: + case EfiPciIoAttributeOperationEnable: + case EfiPciIoAttributeOperationDisable: + // Since we are not a real PCI device no enable/set or disable operations exist. + return EFI_SUCCESS; + + default: + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + }; + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoGetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT8 BarIndex, + OUT UINT64 *Supports, OPTIONAL + OUT VOID **Resources OPTIONAL + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoSetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN UINT8 BarIndex, + IN OUT UINT64 *Offset, + IN OUT UINT64 *Length + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_PCI_IO_PROTOCOL PciIoTemplate = +{ + PciIoPollMem, + PciIoPollIo, + PciIoMemRead, + PciIoMemWrite, + PciIoIoRead, + PciIoIoWrite, + PciIoPciRead, + PciIoPciWrite, + PciIoCopyMem, + PciIoMap, + PciIoUnmap, + PciIoAllocateBuffer, + PciIoFreeBuffer, + PciIoFlush, + PciIoGetLocation, + PciIoAttributes, + PciIoGetBarAttributes, + PciIoSetBarAttributes, + 0, + 0 +}; + +EFI_STATUS +EFIAPI +PciEmulationEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + EFI_PCI_IO_PRIVATE_DATA *Private; + UINT8 CapabilityLength; + UINT8 PhysicalPorts; + UINTN Count; + + //Configure USB host for OMAP4430. + ConfigureUSBHost(); + + // Create a private structure + Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA)); + if (Private == NULL) { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } + + Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature + Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too + Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base + Private->Segment = 0; // Default to segment zero + + // Find out the capability register length and number of physical ports. + CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart); + PhysicalPorts = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F; + + // Calculate the total size of the USB registers. + Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1)); + + // Enable Port Power bit in Port status and control registers in EHCI register space. + // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates + // host controller implementation includes port power control. + for (Count = 0; Count < PhysicalPorts; Count++) { + MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000); + } + + // Create fake PCI config space. + Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00)); + if (Private->ConfigSpace == NULL) { + Status = EFI_OUT_OF_RESOURCES; + FreePool(Private); + return Status; + } + + // Configure PCI config space + Private->ConfigSpace->Hdr.VendorId = 0x3530; + Private->ConfigSpace->Hdr.DeviceId = 0x3530; + Private->ConfigSpace->Hdr.ClassCode[0] = 0x20; + Private->ConfigSpace->Hdr.ClassCode[1] = 0x03; + Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C; + Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart; + + Handle = NULL; + + // Unique device path. + CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate)); + Private->DevicePath.AcpiDevicePath.UID = 0; + + // Copy protocol structure + CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate)); + + Status = gBS->InstallMultipleProtocolInterfaces(&Handle, + &gEfiPciIoProtocolGuid, &Private->PciIoProtocol, + &gEfiDevicePathProtocolGuid, &Private->DevicePath, + NULL); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n")); + } + + return Status; +} + diff --git a/Omap44xxPkg/PciEmulation/PciEmulation.h b/Omap44xxPkg/PciEmulation/PciEmulation.h new file mode 100644 index 000000000..ba719e1db --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciEmulation.h @@ -0,0 +1,292 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCI_ROOT_BRIDGE_H_ +#define _PCI_ROOT_BRIDGE_H_ + +#include <PiDxe.h> + +#include <TWL6030.h> + +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PciLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/OmapDmaLib.h> +#include <Library/DmaLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/DevicePath.h> +#include <Protocol/PciIo.h> +#include <Protocol/PciRootBridgeIo.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> + +#include <IndustryStandard/Pci22.h> +#include <IndustryStandard/Acpi.h> + +#include <Omap4430/Omap4430.h> + + + +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL +#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL + + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + + +#define ACPI_CONFIG_IO 0 +#define ACPI_CONFIG_MMIO 1 +#define ACPI_CONFIG_BUS 2 + +typedef struct { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3]; + EFI_ACPI_END_TAG_DESCRIPTOR EndDesc; +} ACPI_CONFIG_INFO; + + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; + + UINT8 StartBus; + UINT8 EndBus; + UINT16 Type; + UINT32 MemoryStart; + UINT32 MemorySize; + UINTN IoOffset; + UINT32 IoStart; + UINT32 IoSize; + UINT64 PciAttributes; + + ACPI_CONFIG_INFO *Config; + +} PCI_ROOT_BRIDGE; + + +#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE) + + +typedef union { + UINT8 volatile *buf; + UINT8 volatile *ui8; + UINT16 volatile *ui16; + UINT32 volatile *ui32; + UINT64 volatile *ui64; + UINTN volatile ui; +} PTR; + + + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ); + +// +// Private Function Prototypes +// +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN BOOLEAN InStrideFlag, + IN PTR In, + IN BOOLEAN OutStrideFlag, + OUT PTR Out + ); + +BOOLEAN +PciIoMemAddressValid ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Address + ); + +EFI_STATUS +EmulatePciIoForEhci ( + INTN MvPciIfMaxIf + ); + +#endif + diff --git a/Omap44xxPkg/PciEmulation/PciEmulation.inf b/Omap44xxPkg/PciEmulation/PciEmulation.inf new file mode 100644 index 000000000..5907d9808 --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciEmulation.inf @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardPciEmulation + FILE_GUID = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = PciEmulationEntryPoint + +[Sources.common] + PciRootBridgeIo.c + PciEmulation.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + BaseLib + DxeServicesTableLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + IoLib + OmapDmaLib + DmaLib + +[Protocols] + gEfiPciRootBridgeIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + gEfiPciIoProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + +[Depex] + gEfiMetronomeArchProtocolGuid AND + gEmbeddedExternalDeviceProtocolGuid +
\ No newline at end of file diff --git a/Omap44xxPkg/PciEmulation/PciRootBridgeIo.c b/Omap44xxPkg/PciEmulation/PciRootBridgeIo.c new file mode 100644 index 000000000..2f5b1aa1d --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciRootBridgeIo.c @@ -0,0 +1,306 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciEmulation.h" + +BOOLEAN +PciRootBridgeMemAddressValid ( + IN PCI_ROOT_BRIDGE *Private, + IN UINT64 Address + ) +{ + if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) { + return TRUE; + } + + return FALSE; +} + + +EFI_STATUS +PciRootBridgeIoMemRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN BOOLEAN InStrideFlag, + IN PTR In, + IN BOOLEAN OutStrideFlag, + OUT PTR Out + ) +{ + UINTN Stride; + UINTN InStride; + UINTN OutStride; + + + Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + Stride = (UINTN)1 << Width; + InStride = InStrideFlag ? Stride : 0; + OutStride = OutStrideFlag ? Stride : 0; + + // + // Loop for each iteration and move the data + // + switch (Width) { + case EfiPciWidthUint8: + for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) { + *In.ui8 = *Out.ui8; + } + break; + case EfiPciWidthUint16: + for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) { + *In.ui16 = *Out.ui16; + } + break; + case EfiPciWidthUint32: + for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) { + *In.ui32 = *Out.ui32; + } + break; + default: + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +PciRootBridgeIoPciRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +{ + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + UINTN AlignMask; + PTR In; + PTR Out; + + if ( Buffer == NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + return EFI_INVALID_PARAMETER; + } + + AlignMask = (1 << (Width & 0x03)) - 1; + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + In.buf = Buffer; + Out.buf = (VOID *)(UINTN) Address; + + switch (Width) { + case EfiPciWidthUint8: + case EfiPciWidthUint16: + case EfiPciWidthUint32: + case EfiPciWidthUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); + + case EfiPciWidthFifoUint8: + case EfiPciWidthFifoUint16: + case EfiPciWidthFifoUint32: + case EfiPciWidthFifoUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); + + case EfiPciWidthFillUint8: + case EfiPciWidthFillUint16: + case EfiPciWidthFillUint32: + case EfiPciWidthFillUint64: + return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); + + default: + break; + } + + return EFI_INVALID_PARAMETER; +} + + + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + UINTN AlignMask; + PTR In; + PTR Out; + + if ( Buffer == NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + return EFI_INVALID_PARAMETER; + } + + AlignMask = (1 << (Width & 0x03)) - 1; + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + In.buf = (VOID *)(UINTN) Address; + Out.buf = Buffer; + + switch (Width) { + case EfiPciWidthUint8: + case EfiPciWidthUint16: + case EfiPciWidthUint32: + case EfiPciWidthUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); + + case EfiPciWidthFifoUint8: + case EfiPciWidthFifoUint16: + case EfiPciWidthFifoUint32: + case EfiPciWidthFifoUint64: + return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); + + case EfiPciWidthFillUint8: + case EfiPciWidthFillUint16: + case EfiPciWidthFillUint32: + case EfiPciWidthFillUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); + + default: + break; + } + + return EFI_INVALID_PARAMETER; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); +} + + + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); +} + + diff --git a/Omap44xxPkg/SmbusDxe/Smbus.c b/Omap44xxPkg/SmbusDxe/Smbus.c new file mode 100644 index 000000000..bed5121e4 --- /dev/null +++ b/Omap44xxPkg/SmbusDxe/Smbus.c @@ -0,0 +1,325 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> +#include <Omap4430/Omap4430.h> + +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/SmbusHc.h> + +#define MAX_RETRY 1000 + +// +// Internal Functions +// +STATIC +EFI_STATUS +WaitForBusBusy ( + VOID + ) +{ + UINTN Retry = 0; + + while (++Retry < MAX_RETRY && (MmioRead16(I2C_STAT) & BB) == 0x1); + + if (Retry == MAX_RETRY) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +PollForStatus( + UINT16 StatusBit + ) +{ + UINTN Retry = 0; + + while(Retry < MAX_RETRY) { + if (MmioRead16(I2C_STAT) & StatusBit) { + //Clear particular status bit from Status register. + MmioOr16(I2C_STAT, StatusBit); + break; + } + Retry++; + } + + if (Retry == MAX_RETRY) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +ConfigureI2c ( + VOID + ) +{ + //Program prescaler to obtain 12-MHz clock + MmioWrite16(I2C_PSC, 0x0000); + + //Program SCLL and SCLH + //NOTE: Following values are the register dump after U-Boot code executed. + //We need to figure out how its calculated based on the I2C functional clock and I2C_PSC. + MmioWrite16(I2C_SCLL, 0x0035); + MmioWrite16(I2C_SCLH, 0x0035); + + //Take the I2C controller out of reset. + MmioOr16(I2C_CON, I2C_EN); + + //Initialize the I2C controller. + + //Set I2C controller in Master mode. + MmioOr16(I2C_CON, MST); + + //Enable interrupts for receive/transmit mode. + MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE)); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2CReadOneByte ( + UINT8 *Data + ) +{ + EFI_STATUS Status; + + //I2C bus status checking + Status = WaitForBusBusy(); + if (EFI_ERROR(Status)) { + return Status; + } + + //Poll till Receive ready bit is set. + Status = PollForStatus(RRDY); + if (EFI_ERROR(Status)) { + return Status; + } + + *Data = MmioRead8(I2C_DATA); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2CWriteOneByte ( + UINT8 Data + ) +{ + EFI_STATUS Status; + + //I2C bus status checking + Status = WaitForBusBusy(); + if (EFI_ERROR(Status)) { + return Status; + } + + //Data transfer + //Poll till Transmit ready bit is set + Status = PollForStatus(XRDY); + if (EFI_ERROR(Status)) { + return Status; + } + + MmioWrite8(I2C_DATA, Data); + + //Wait and check if the NACK is not set. + gBS->Stall(1000); + if (MmioRead16(I2C_STAT) & NACK) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SmbusBlockRead ( + OUT UINT8 *Buffer, + IN UINTN Length + ) +{ + UINTN Index = 0; + EFI_STATUS Status = EFI_SUCCESS; + + //Transfer configuration for receiving data. + MmioWrite16(I2C_CNT, Length); + //Need stop bit before sending data. + MmioWrite16(I2C_CON, (I2C_EN | MST | STP | STT)); + + while (Index < Length) { + //Read a byte + Status = I2CReadOneByte(&Buffer[Index++]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + //Transfer completion + Status = PollForStatus(ARDY); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +STATIC +EFI_STATUS +SmbusBlockWrite ( + IN UINT8 *Buffer, + IN UINTN Length + ) +{ + UINTN Index = 0; + EFI_STATUS Status = EFI_SUCCESS; + + //Transfer configuration for transmitting data + MmioWrite16(I2C_CNT, Length); + MmioWrite16(I2C_CON, (I2C_EN | TRX | MST | STT | STP)); + + while (Index < Length) { + //Send a byte + Status = I2CWriteOneByte(Buffer[Index++]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + //Transfer completion + Status = PollForStatus(ARDY); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +// +// Public Functions. +// +EFI_STATUS +EFIAPI +SmbusExecute ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN CONST EFI_SMBUS_DEVICE_COMMAND Command, + IN CONST EFI_SMBUS_OPERATION Operation, + IN CONST BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer + ) +{ + UINT8 *ByteBuffer = Buffer; + EFI_STATUS Status = EFI_SUCCESS; + UINT8 SlaveAddr = (UINT8)(SlaveAddress.SmbusDeviceAddress); + + if (PecCheck) { + return EFI_UNSUPPORTED; + } + + if ((Operation != EfiSmbusWriteBlock) && (Operation != EfiSmbusReadBlock)) { + return EFI_UNSUPPORTED; + } + + //Set the Slave address. + MmioWrite16(I2C_SA, SlaveAddr); + + if (Operation == EfiSmbusReadBlock) { + Status = SmbusBlockRead(ByteBuffer, *Length); + } else if (Operation == EfiSmbusWriteBlock) { + Status = SmbusBlockWrite(ByteBuffer, *Length); + } + + return Status; +} + +EFI_STATUS +EFIAPI +SmbusArpDevice ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid OPTIONAL, + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + + +EFI_STATUS +EFIAPI +SmbusGetArpMap ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap + ) +{ + return EFI_UNSUPPORTED; +} + + +EFI_STATUS +EFIAPI +SmbusNotify ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN CONST UINTN Data, + IN CONST EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_SMBUS_HC_PROTOCOL SmbusProtocol = +{ + SmbusExecute, + SmbusArpDevice, + SmbusGetArpMap, + SmbusNotify +}; + +EFI_STATUS +InitializeSmbus ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + + //Configure I2C controller. + Status = ConfigureI2c(); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "InitializeI2c fails.\n")); + return Status; + } + + // Install the SMBUS interface + Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiSmbusHcProtocolGuid, &SmbusProtocol, NULL); + ASSERT_EFI_ERROR(Status); + + return Status; +} + diff --git a/Omap44xxPkg/SmbusDxe/Smbus.inf b/Omap44xxPkg/SmbusDxe/Smbus.inf new file mode 100644 index 000000000..b1000501d --- /dev/null +++ b/Omap44xxPkg/SmbusDxe/Smbus.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Smbus + FILE_GUID = d5125e0f-1226-444f-a218-0085996ed5da + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeSmbus + +[Sources.common] + Smbus.c + +[Packages] + MdePkg/MdePkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + PcdLib + UefiLib + UefiDriverEntryPoint + MemoryAllocationLib + IoLib + +[Guids] + +[Protocols] + gEfiSmbusHcProtocolGuid + +[Pcd] + +[depex] + TRUE
\ No newline at end of file diff --git a/Omap44xxPkg/TWL6030Dxe/TWL6030.c b/Omap44xxPkg/TWL6030Dxe/TWL6030.c new file mode 100644 index 000000000..f4027bfa8 --- /dev/null +++ b/Omap44xxPkg/TWL6030Dxe/TWL6030.c @@ -0,0 +1,116 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> + +#include <TWL6030.h> + +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/SmbusHc.h> + +EFI_SMBUS_HC_PROTOCOL *Smbus; + +EFI_STATUS +Read ( + IN EMBEDDED_EXTERNAL_DEVICE *This, + IN UINTN Register, + IN UINTN Length, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 DeviceRegister; + UINTN DeviceRegisterLength = 1; + + SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register); + DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register); + + //Write DeviceRegister. + Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceRegisterLength, &DeviceRegister); + if (EFI_ERROR(Status)) { + return Status; + } + + //Read Data + Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusReadBlock, FALSE, &Length, Buffer); + return Status; +} + +EFI_STATUS +Write ( + IN EMBEDDED_EXTERNAL_DEVICE *This, + IN UINTN Register, + IN UINTN Length, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 DeviceRegister; + UINTN DeviceBufferLength = Length + 1; + UINT8 *DeviceBuffer; + + SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register); + DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register); + + //Prepare buffer for writing + DeviceBuffer = (UINT8 *)AllocatePool(DeviceBufferLength); + if (DeviceBuffer == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto exit; + } + + //Set Device register followed by data to write. + DeviceBuffer[0] = DeviceRegister; + CopyMem(&DeviceBuffer[1], Buffer, Length); + + //Write Data + Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceBufferLength, DeviceBuffer); + if (EFI_ERROR(Status)) { + goto exit; + } + +exit: + if (DeviceBuffer) { + FreePool(DeviceBuffer); + } + + return Status; +} + +EMBEDDED_EXTERNAL_DEVICE ExternalDevice = { + Read, + Write +}; + +EFI_STATUS +TWL6030Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol(&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&Smbus); + ASSERT_EFI_ERROR(Status); + + Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedExternalDeviceProtocolGuid, &ExternalDevice, NULL); + return Status; +} diff --git a/Omap44xxPkg/TWL6030Dxe/TWL6030.inf b/Omap44xxPkg/TWL6030Dxe/TWL6030.inf new file mode 100644 index 000000000..a539bfaae --- /dev/null +++ b/Omap44xxPkg/TWL6030Dxe/TWL6030.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = TWL6030 + FILE_GUID = 71fe861a-5450-48b6-bfb0-b93522616f99 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = TWL6030Initialize + + +[Sources.common] + TWL6030.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + BaseMemoryLib + PcdLib + UefiLib + UefiDriverEntryPoint + MemoryAllocationLib + +[Guids] + +[Protocols] + gEfiSmbusHcProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + +[Pcd] + +[depex] + gEfiSmbusHcProtocolGuid diff --git a/Omap44xxPkg/TimerDxe/Timer.c b/Omap44xxPkg/TimerDxe/Timer.c new file mode 100644 index 000000000..e297f0ce9 --- /dev/null +++ b/Omap44xxPkg/TimerDxe/Timer.c @@ -0,0 +1,373 @@ +/** @file + Template for Timer Architecture Protocol driver of the ARM flavor + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include <PiDxe.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> + +#include <Protocol/Timer.h> +#include <Protocol/HardwareInterrupt.h> + +#include <Omap4430/Omap4430.h> + + +// The notification function to call on every timer interrupt. +volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL; + + +// The current period of the timer interrupt +volatile UINT64 mTimerPeriod = 0; + +// Cached copy of the Hardware Interrupt protocol instance +EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; + +// Cached registers +volatile UINT32 TISR; +volatile UINT32 TCLR; +volatile UINT32 TLDR; +volatile UINT32 TCRR; +volatile UINT32 TIER; + +// Cached interrupt vector +volatile UINTN gVector; + + +/** + + C Interrupt Handler calledin the interrupt context when Source interrupt is active. + + + @param Source Source of the interrupt. Hardware routing off a specific platform defines + what source means. + + @param SystemContext Pointer to system register context. Mostly used by debuggers and will + update the system context after the return from the interrupt if + modified. Don't change these values unless you know what you are doing + +**/ +VOID +EFIAPI +TimerInterruptHandler ( + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + + + + // + // DXE core uses this callback for the EFI timer tick. The DXE core uses locks + // that raise to TPL_HIGH and then restore back to current level. Thus we need + // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick. + // + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); + + if (mTimerNotifyFunction) { + mTimerNotifyFunction(mTimerPeriod); + } + + // Clear all timer interrupts + MmioWrite32 (TISR, TISR_CLEAR_ALL); + + // Poll interrupt status bits to ensure clearing + while ((MmioRead32 (TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING); + + gBS->RestoreTPL (OriginalTPL); +} + +/** + This function registers the handler NotifyFunction so it is called every time + the timer interrupt fires. It also passes the amount of time since the last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS is + returned. If the CPU does not support registering a timer interrupt handler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler + when a handler is already registered, then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not registered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fires. This + function executes at TPL_HIGH_LEVEL. The DXE Core will + register a handler for the timer interrupt, so it can know + how much time has passed. This information is used to + signal timer based events. NULL will unregister the handler. + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support timer interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be registered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) { + return EFI_ALREADY_STARTED; + } + + mTimerNotifyFunction = NotifyFunction; + + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specified + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust the + interrupt controller so that a CPU interrupt is not generated when the timer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is + returned. If the timer is programmable, then the timer period + will be rounded up to the nearest timer period that is supported + by the timer hardware. If TimerPeriod is set to 0, then the + timer interrupts will be disabled. + + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + EFI_STATUS Status; + UINT64 TimerCount; + INT32 LoadValue; + + if (TimerPeriod == 0) { + // Turn off GPTIMER3 + MmioWrite32 (TCLR, TCLR_ST_OFF); + + Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector); + } else { + // Calculate required timer count + TimerCount = DivU64x32(TimerPeriod * 100, PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)); + + // Set GPTIMER3 Load register + LoadValue = (INT32) -TimerCount; + MmioWrite32 (TLDR, LoadValue); + MmioWrite32 (TCRR, LoadValue); + + // Enable Overflow interrupt + MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE); + + // Turn on GPTIMER3, it will reload at overflow + MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + + Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector); + } + + // + // Save the new timer period + // + mTimerPeriod = TimerPeriod; + return Status; +} + + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If + 0 is returned, then the timer is currently disabled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeriod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + if (TimerPeriod == NULL) { + return EFI_INVALID_PARAMETER; + } + + *TimerPeriod = mTimerPeriod; + return EFI_SUCCESS; +} + +/** + This function generates a soft timer interrupt. If the platform does not support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() + service, then a soft timer interrupt will be generated. If the timer interrupt is + enabled when this service is called, then the registered handler will be invoked. The + registered handler should not be able to distinguish a hardware-generated timer + interrupt from a software-generated timer interrupt. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Interface stucture for the Timer Architectural Protocol. + + @par Protocol Description: + This protocol provides the services to initialize a periodic timer + interrupt, and to register a handler that is called each time the timer + interrupt fires. It may also provide a service to adjust the rate of the + periodic timer interrupt. When a timer interrupt occurs, the handler is + passed the amount of time that has passed since the previous timer + interrupt. + + @param RegisterHandler + Registers a handler that will be called each time the + timer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + + @param GenerateSoftInterrupt + Generates a soft timer interrupt that simulates the firing of + the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for + a period of time. + +**/ +EFI_TIMER_ARCH_PROTOCOL gTimer = { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + + +/** + Initialize the state information for the Timer Architectural Protocol and + the Timer Debug support protocol that allows the debugger to break into a + running program. + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +TimerInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + UINT32 TimerBaseAddress; + + // Find the interrupt controller protocol. ASSERT if not found. + Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt); + ASSERT_EFI_ERROR (Status); + + // Set up the timer registers + TimerBaseAddress = TimerBase (FixedPcdGet32(PcdOmap44xxArchTimer)); + TISR = TimerBaseAddress + GPTIMER_TISR; + TCLR = TimerBaseAddress + GPTIMER_TCLR; + TLDR = TimerBaseAddress + GPTIMER_TLDR; + TCRR = TimerBaseAddress + GPTIMER_TCRR; + TIER = TimerBaseAddress + GPTIMER_TIER; + + // Disable the timer + Status = TimerDriverSetTimerPeriod (&gTimer, 0); + ASSERT_EFI_ERROR (Status); + + // Install interrupt handler + gVector = InterruptVectorForTimer (FixedPcdGet32(PcdOmap44xxArchTimer)); + Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // Set up default timer + Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); + ASSERT_EFI_ERROR (Status); + + // Install the Timer Architectural Protocol onto a new handle + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiTimerArchProtocolGuid, &gTimer, + NULL + ); + ASSERT_EFI_ERROR(Status); + + return Status; +} + diff --git a/Omap44xxPkg/TimerDxe/TimerDxe.inf b/Omap44xxPkg/TimerDxe/TimerDxe.inf new file mode 100644 index 000000000..b607e19b0 --- /dev/null +++ b/Omap44xxPkg/TimerDxe/TimerDxe.inf @@ -0,0 +1,57 @@ +#/** @file +# +# Component discription file for Timer module +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardTimerDxe + FILE_GUID = 6ddbf08b-cfc9-43cc-9e81-0784ba312ca0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = TimerInitialize + +[Sources.common] + Timer.c + +[Packages] + Omap44xxPkg/Omap44xxPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + UefiRuntimeServicesTableLib + UefiLib + UefiBootServicesTableLib + BaseMemoryLib + DebugLib + UefiDriverEntryPoint + IoLib + OmapLib + +[Guids] + +[Protocols] + gEfiTimerArchProtocolGuid + gHardwareInterruptProtocolGuid + +[Pcd.common] + gEmbeddedTokenSpaceGuid.PcdTimerPeriod + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds + gOmap44xxTokenSpaceGuid.PcdOmap44xxArchTimer + +[Depex] + gHardwareInterruptProtocolGuid
\ No newline at end of file diff --git a/PandaBoardPkg/Bds/Bds.inf b/PandaBoardPkg/Bds/Bds.inf new file mode 100644 index 000000000..c2ea26c83 --- /dev/null +++ b/PandaBoardPkg/Bds/Bds.inf @@ -0,0 +1,65 @@ + +#/** @file +# +# Component discription file for Bds module +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardBds + FILE_GUID = 934431fe-5745-402e-913d-17b4434eb0f3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = BdsInitialize + +[Sources.common] + BdsEntry.c + FirmwareVolume.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DevicePathLib + BaseLib + HobLib + UefiRuntimeServicesTableLib + ReportStatusCodeLib + PerformanceLib + DxeServicesTableLib + MemoryAllocationLib + UefiLib + UefiBootServicesTableLib + BaseMemoryLib + DebugLib + PrintLib + UefiDriverEntryPoint + +[Guids] + + +[Protocols] + gEfiBdsArchProtocolGuid + gEfiSimpleTextInProtocolGuid + gEfiSimpleTextOutProtocolGuid + gEfiSerialIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiSimpleFileSystemProtocolGuid + gEfiUsbIoProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + +[Depex] + TRUE diff --git a/PandaBoardPkg/Bds/BdsEntry.c b/PandaBoardPkg/Bds/BdsEntry.c new file mode 100644 index 000000000..15fda69d9 --- /dev/null +++ b/PandaBoardPkg/Bds/BdsEntry.c @@ -0,0 +1,246 @@ +/** @file + The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements + of the UEFI specification as it is designed to implement an embedded systmes + propriatary boot scheme. + + This template assume a DXE driver produces a SerialIo protocol not using the EFI + driver module and it will attempt to connect a console on top of this. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "BdsEntry.h" + + +BOOLEAN gConsolePresent = FALSE; + + +EFI_HANDLE mBdsImageHandle = NULL; +EFI_BDS_ARCH_PROTOCOL gBdsProtocol = { + BdsEntry, +}; + + + + +/** + This function uses policy data from the platform to determine what operating + system or system utility should be loaded and invoked. This function call + also optionally make the use of user input to determine the operating system + or system utility to be loaded and invoked. When the DXE Core has dispatched + all the drivers on the dispatch queue, this function is called. This + function will attempt to connect the boot devices required to load and invoke + the selected operating system or system utility. During this process, + additional firmware volumes may be discovered that may contain addition DXE + drivers that can be dispatched by the DXE Core. If a boot device cannot be + fully connected, this function calls the DXE Service Dispatch() to allow the + DXE drivers from any newly discovered firmware volumes to be dispatched. + Then the boot device connection can be attempted again. If the same boot + device connection operation fails twice in a row, then that boot device has + failed, and should be skipped. This function should never return. + + @param This The EFI_BDS_ARCH_PROTOCOL instance. + + @return None. + +**/ +VOID +EFIAPI +BdsEntry ( + IN EFI_BDS_ARCH_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINTN NoHandles; + EFI_HANDLE *Buffer; + EFI_HANDLE FvHandle; + EFI_HANDLE ImageHandle; + EFI_HANDLE UsbDeviceHandle; + EFI_GUID NameGuid; + UINTN Size; + UINTN HandleCount; + UINTN OldHandleCount; + EFI_HANDLE *HandleBuffer; + UINTN Index; + EFI_DEVICE_PATH_PROTOCOL *LoadImageDevicePath; + EFI_DEVICE_PATH_PROTOCOL *FileSystemDevicePath; + + PERF_END (NULL, "DXE", NULL, 0); + PERF_START (NULL, "BDS", NULL, 0); + + + // + // Now do the EFI stuff + // + Size = 0x100; + gST->FirmwareVendor = AllocateRuntimePool (Size); + ASSERT (gST->FirmwareVendor != NULL); + + UnicodeSPrint (gST->FirmwareVendor, Size, L"PandaBoard EFI %a %a", __DATE__, __TIME__); + + // + // Now we need to setup the EFI System Table with information about the console devices. + // This code is normally in the console spliter driver on platforms that support multiple + // consoles at the same time + // + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextOutProtocolGuid, NULL, &NoHandles, &Buffer); + if (!EFI_ERROR (Status)) { + // Use the first SimpleTextOut we find and update the EFI System Table + gST->ConsoleOutHandle = Buffer[0]; + gST->StandardErrorHandle = Buffer[0]; + Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextOutProtocolGuid, (VOID **)&gST->ConOut); + ASSERT_EFI_ERROR (Status); + + gST->StdErr = gST->ConOut; + + gST->ConOut->OutputString (gST->ConOut, L"BDS: Console Started!!!!\n\r"); + FreePool (Buffer); + + gConsolePresent = TRUE; + } + + + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextInProtocolGuid, NULL, &NoHandles, &Buffer); + if (!EFI_ERROR (Status)) { + // Use the first SimpleTextIn we find and update the EFI System Table + gST->ConsoleInHandle = Buffer[0]; + Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextInProtocolGuid, (VOID **)&gST->ConIn); + ASSERT_EFI_ERROR (Status); + + FreePool (Buffer); + } + + // + // We now have EFI Consoles up and running. Print () will work now. DEBUG () and ASSERT () worked + // prior to this point as they were configured to use a more primative output scheme. + // + + // + //Perform Connect + // + HandleCount = 0; + while (1) { + OldHandleCount = HandleCount; + Status = gBS->LocateHandleBuffer ( + AllHandles, + NULL, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + break; + } + + if (HandleCount == OldHandleCount) { + break; + } + + for (Index = 0; Index < HandleCount; Index++) { + gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE); + } + } + + EfiSignalEventReadyToBoot (); + + //Locate handles for SimpleFileSystem protocol + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSimpleFileSystemProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (!EFI_ERROR(Status)) { + for (Index = 0; Index < HandleCount; Index++) { + //Get the device path + FileSystemDevicePath = DevicePathFromHandle(HandleBuffer[Index]); + if (FileSystemDevicePath == NULL) { + continue; + } + + //Check if UsbIo is on any handles in the device path. + Status = gBS->LocateDevicePath(&gEfiUsbIoProtocolGuid, &FileSystemDevicePath, &UsbDeviceHandle); + if (EFI_ERROR(Status)) { + continue; + } + + //Check if Usb stick has a magic EBL file. + LoadImageDevicePath = FileDevicePath(HandleBuffer[Index], L"Ebl.efi"); + Status = gBS->LoadImage (TRUE, gImageHandle, LoadImageDevicePath, NULL, 0, &ImageHandle); + if (EFI_ERROR(Status)) { + continue; + } + + //Boot to Shell on USB stick. + Status = gBS->StartImage (ImageHandle, NULL, NULL); + if (EFI_ERROR(Status)) { + continue; + } + } + } + + // + // Normal UEFI behavior is to process Globally Defined Variables as defined in Chapter 3 + // (Boot Manager) of the UEFI specification. For this embedded system we don't do this. + // + + // + // Search all the FVs for an application with a UI Section of Ebl. A .FDF file can be used + // to control the names of UI sections in an FV. + // + Status = FindApplicationMatchingUiSection (L"Ebl", &FvHandle, &NameGuid); + if (!EFI_ERROR (Status)) { + + //Boot to Shell. + Status = LoadPeCoffSectionFromFv (FvHandle, &NameGuid); + + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Boot from Shell failed. Status: %r\n", Status)); + } + } + + // + // EFI does not define the behaviour if all boot attemps fail and the last one returns. + // So we make a policy choice to reset the system since this BDS does not have a UI. + // + gRT->ResetSystem (EfiResetShutdown, Status, 0, NULL); + + return ; +} + + +EFI_STATUS +EFIAPI +BdsInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mBdsImageHandle = ImageHandle; + + // + // Install protocol interface + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &mBdsImageHandle, + &gEfiBdsArchProtocolGuid, &gBdsProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/PandaBoardPkg/Bds/BdsEntry.h b/PandaBoardPkg/Bds/BdsEntry.h new file mode 100644 index 000000000..47891c01d --- /dev/null +++ b/PandaBoardPkg/Bds/BdsEntry.h @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __BDS_ENTRY_H__ +#define __BDS_ENTRY_H__ + +#include <PiDxe.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/PrintLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/HobLib.h> +#include <Library/DevicePathLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PrintLib.h> +#include <Library/PerformanceLib.h> + +#include <Protocol/Bds.h> +#include <Protocol/SerialIo.h> +#include <Protocol/FirmwareVolume2.h> +#include <Protocol/SimpleTextIn.h> +#include <Protocol/SimpleTextOut.h> +#include <Protocol/EmbeddedDevice.h> +#include <Protocol/DevicePath.h> +#include <Protocol/SimpleFileSystem.h> +#include <Protocol/UsbIo.h> + + +EFI_STATUS +LoadPeCoffSectionFromFv ( + IN EFI_HANDLE FvHandle, + IN EFI_GUID *NameGuid + ); + +EFI_STATUS +FindApplicationMatchingUiSection ( + IN CHAR16 *UiString, + OUT EFI_HANDLE *FvHandle, + OUT EFI_GUID *NameGuid + ); + +VOID +EFIAPI +BdsEntry ( + IN EFI_BDS_ARCH_PROTOCOL *This + ); + +#endif + diff --git a/PandaBoardPkg/Bds/FirmwareVolume.c b/PandaBoardPkg/Bds/FirmwareVolume.c new file mode 100644 index 000000000..6c891f4e4 --- /dev/null +++ b/PandaBoardPkg/Bds/FirmwareVolume.c @@ -0,0 +1,150 @@ +/** @file + The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements + of the UEFI specification as it is designed to implement an embedded systmes + propriatary boot scheme. + + This template assume a DXE driver produces a SerialIo protocol not using the EFI + driver module and it will attempt to connect a console on top of this. + + + Copyright (c) 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "BdsEntry.h" + + +EFI_STATUS +FindApplicationMatchingUiSection ( + IN CHAR16 *UiString, + OUT EFI_HANDLE *FvHandle, + OUT EFI_GUID *NameGuid + ) +{ + EFI_STATUS Status; + EFI_STATUS NextStatus; + UINTN NoHandles; + EFI_HANDLE *Buffer; + UINTN Index; + EFI_FV_FILETYPE FileType; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + VOID *Key; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN UiStringLen; + CHAR16 *UiSection; + UINT32 Authentication; + + + UiStringLen = 0; + if (UiString != NULL) { + DEBUG ((DEBUG_ERROR, "UiString %s\n", UiString)); + UiStringLen = StrLen (UiString); + } + + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Buffer); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < NoHandles; Index++) { + Status = gBS->HandleProtocol (Buffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **)&Fv); + if (!EFI_ERROR (Status)) { + Key = AllocatePool (Fv->KeySize); + ASSERT (Key != NULL); + ZeroMem (Key, Fv->KeySize); + + FileType = EFI_FV_FILETYPE_APPLICATION; + + do { + NextStatus = Fv->GetNextFile (Fv, Key, &FileType, NameGuid, &Attributes, &Size); + if (!EFI_ERROR (NextStatus)) { + if (UiString == NULL) { + // + // If UiString is NULL match first application we find. + // + *FvHandle = Buffer[Index]; + FreePool (Key); + return Status; + } + + UiSection = NULL; + Status = Fv->ReadSection ( + Fv, + NameGuid, + EFI_SECTION_USER_INTERFACE, + 0, + (VOID **)&UiSection, + &Size, + &Authentication + ); + if (!EFI_ERROR (Status)) { + if (StrnCmp (UiString, UiSection, UiStringLen) == 0) { + // + // We found a UiString match. + // + *FvHandle = Buffer[Index]; + FreePool (Key); + FreePool (UiSection); + return Status; + } + FreePool (UiSection); + } + } + } while (!EFI_ERROR (NextStatus)); + + FreePool (Key); + } + } + + FreePool (Buffer); + } + + return EFI_NOT_FOUND; +} + + +EFI_DEVICE_PATH * +FvFileDevicePath ( + IN EFI_HANDLE FvHandle, + IN EFI_GUID *NameGuid + ) +{ + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH NewNode; + + DevicePath = DevicePathFromHandle (FvHandle); + + EfiInitializeFwVolDevicepathNode (&NewNode, NameGuid); + + return AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&NewNode); +} + + + +EFI_STATUS +LoadPeCoffSectionFromFv ( + IN EFI_HANDLE FvHandle, + IN EFI_GUID *NameGuid + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_HANDLE ImageHandle; + + DevicePath = FvFileDevicePath (FvHandle, NameGuid); + + Status = gBS->LoadImage (TRUE, gImageHandle, DevicePath, NULL, 0, &ImageHandle); + if (!EFI_ERROR (Status)) { + PERF_END (NULL, "BDS", NULL, 0); + Status = gBS->StartImage (ImageHandle, NULL, NULL); + } + + return Status; +} + diff --git a/PandaBoardPkg/ConfigurationHeader.dat b/PandaBoardPkg/ConfigurationHeader.dat new file mode 100644 index 000000000..ec7dbcd30 --- /dev/null +++ b/PandaBoardPkg/ConfigurationHeader.dat @@ -0,0 +1,64 @@ +TARGET=OMAP4 + +CHSETTINGS +SectionKey=0xC0C0C0C1 +Valid=0x00000001 +Version=0x00000000 +Reserved=0x00000000 +Flags=0x00000BBD +CM_CLKSEL_CORE=0x00000110 +CM_DLL_CTRL=0x00000000 +CM_AUTOIDLE_DPLL_MPU=0x00000000 +CM_CLKSEL_DPLL_MPU=0x00007D05 +CM_DIV_M2_DPLL_MPU=0x00000002 +CM_AUTOIDLE_DPLL_CORE=0x00000000 +CM_CLKSEL_DPLL_CORE=0x00007D05 +CM_DIV_M2_DPLL_CORE=0x00000002 +CM_DIV_M3_DPLL_CORE=0x00000008 +CM_DIV_M4_DPLL_CORE=0x00000008 +CM_DIV_M5_DPLL_CORE=0x00000008 +CM_DIV_M6_DPLL_CORE=0x00000008 +CM_DIV_M7_DPLL_CORE=0x00000010 +CM_AUTOIDLE_DPLL_PER=0x00000000 +CM_CLKSEL_DPLL_PER=0x00001400 +CM_DIV_M2_DPLL_PER=0x00000008 +CM_DIV_M3_DPLL_PER=0x00000008 +CM_DIV_M4_DPLL_PER=0x0000000C +CM_DIV_M5_DPLL_PER=0x00000009 +CM_DIV_M6_DPLL_PER=0x00000008 +CM_DIV_M7_DPLL_PER=0x0000000A +CM_AUTOIDLE_DPLL_USB=0x00000000 +CM_CLKSEL_DPLL_USB=0x00000000 +CM_DIV_M2_DPLL_USB=0x00000000 + +CHRAM +SectionKey=0xC0C0C0C2 +Valid=0x00000001 +Version=0x00000000 +Reserved=0x00000000 +SdramConfigEMIF1=0x80001ab9 +SdramRefreshEMIF1=0x00000618 +SdramTim1EMIF1=0x10eb0662 +SdramTim2EMIF1=0x20370dd2 +SdramTim3EMIF1=0x00b1c33f +PwrMgtCtrlEMIF1=0x000000ff +DdrPhyCtrl1EMIF1=0x049ff418 +DdrPhyCtrl2EMIF1=0x00000004 +ModeReg1EMIF1=0x000000c3 +ModeReg2EMIF1=0x00000004 +ModeReg3EMIF1=0x00000001 +Reserved=0x00000000 +SdramConfigEMIF2=0x80001ab9 +SdramRefreshEMIF2=0x00000618 +SdramTim1EMIF2=0x10eb0662 +SdramTim2EMIF2=0x20370dd2 +SdramTim3EMIF2=0x00b1c33f +PwrMgtCtrlEMIF2=0x000000ff +DdrPhyCtrl1EMIF2=0x049ff418 +DdrPhyCtrl2EMIF2=0x00000004 +ModeReg1EMIF2=0x000000c3 +ModeReg2EMIF2=0x00000004 +ModeReg3EMIF2=0x00000001 +Reserved=0x00000000 +DMMLisaMap0=0x80640300 +Flags=0x0000010f diff --git a/PandaBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc b/PandaBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc new file mode 100644 index 000000000..543ddb7a0 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc @@ -0,0 +1,21 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +error = continue +unload +error = abort + +setreg @CP15_CONTROL = 0x0005107E +setreg @pc=0x80008208 +setreg @cpsr=0x000000D3 +dis/D +readfile,raw,nowarn "ZZZZZZ/FV/PANDABOARD_EFI.fd"=0x80008000 + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_convert_symbols.sh b/PandaBoardPkg/Debugger_scripts/rvi_convert_symbols.sh new file mode 100644 index 000000000..9567f5c62 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_convert_symbols.sh @@ -0,0 +1,23 @@ +#!/bin/sh +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http:#opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + + +IN=`/usr/bin/cygpath -u $1` +OUT=`/usr/bin/cygpath -u $2` + +/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \ + -e 's:\\:/:g' \ + -e "s/^/load\/a\/ni\/np \"/g" \ + -e "s/dll /dll\" \&/g" \ + $IN | /usr/bin/sort.exe --key=3 --output=$OUT + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_dummy.axf b/PandaBoardPkg/Debugger_scripts/rvi_dummy.axf Binary files differnew file mode 100755 index 000000000..17fabaa6c --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_dummy.axf diff --git a/PandaBoardPkg/Debugger_scripts/rvi_hw_setup.inc b/PandaBoardPkg/Debugger_scripts/rvi_hw_setup.inc new file mode 100644 index 000000000..ea5f8ec15 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_hw_setup.inc @@ -0,0 +1,67 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +error = continue +unload +error = abort + +setreg @CP15_CONTROL = 0x0005107E +setreg @cpsr=0x000000D3 + +; General clock settings. +setmem /32 0x48307270=0x00000080 +setmem /32 0x48306D40=0x00000003 +setmem /32 0x48005140=0x03020A50 + +;Clock configuration +setmem /32 0x48004A40=0x0000030A +setmem /32 0x48004C40=0x00000015 + +;DPLL3 (Core) settings +setmem /32 0x48004D00=0x00370037 +setmem /32 0x48004D30=0x00000000 +setmem /32 0x48004D40=0x094C0C00 + +;DPLL4 (Peripheral) settings +setmem /32 0x48004D00=0x00370037 +setmem /32 0x48004D30=0x00000000 +setmem /32 0x48004D44=0x0001B00C +setmem /32 0x48004D48=0x00000009 + +;DPLL1 (MPU) settings +setmem /32 0x48004904=0x00000037 +setmem /32 0x48004934=0x00000000 +setmem /32 0x48004940=0x0011F40C +setmem /32 0x48004944=0x00000001 +setmem /32 0x48004948=0x00000000 + +;RAM setup. +setmem /16 0x6D000010=0x0000 +setmem /16 0x6D000040=0x0001 +setmem /16 0x6D000044=0x0100 +setmem /16 0x6D000048=0x0000 +setmem /32 0x6D000060=0x0000000A +setmem /32 0x6D000070=0x00000081 +setmem /16 0x6D000040=0x0003 +setmem /32 0x6D000080=0x02D04011 +setmem /16 0x6D000084=0x0032 +setmem /16 0x6D00008C=0x0000 +setmem /32 0x6D00009C=0xBA9DC4C6 +setmem /32 0x6D0000A0=0x00012522 +setmem /32 0x6D0000A4=0x0004E201 +setmem /16 0x6D000040=0x0003 +setmem /32 0x6D0000B0=0x02D04011 +setmem /16 0x6D0000B4=0x0032 +setmem /16 0x6D0000BC=0x0000 +setmem /32 0x6D0000C4=0xBA9DC4C6 +setmem /32 0x6D0000C8=0x00012522 +setmem /32 0x6D0000D4=0x0004E201
\ No newline at end of file diff --git a/PandaBoardPkg/Debugger_scripts/rvi_load_symbols.inc b/PandaBoardPkg/Debugger_scripts/rvi_load_symbols.inc new file mode 100644 index 000000000..b4a67365d --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_load_symbols.inc @@ -0,0 +1,23 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +include 'ZZZZZZ/rvi_symbols_macros.inc' + +macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000) + +host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc" +include 'ZZZZZZ/rvi_symbols.inc' +load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata +unload rvi_dummy.axf +delfile rvi_dummy.axf + + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_symbols_macros.inc b/PandaBoardPkg/Debugger_scripts/rvi_symbols_macros.inc new file mode 100644 index 000000000..9e7f42774 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_symbols_macros.inc @@ -0,0 +1,194 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +define /R int compare_guid(guid1, guid2) + unsigned char *guid1; + unsigned char *guid2; +{ + return strncmp(guid1, guid2, 16); +} +. + +define /R unsigned char * find_system_table(mem_start, mem_size) + unsigned char *mem_start; + unsigned long mem_size; +{ + unsigned char *mem_ptr; + + mem_ptr = mem_start + mem_size; + + do + { + mem_ptr -= 0x400000; // 4 MB + + if (strncmp(mem_ptr, "IBI SYST", 8) == 0) + { + return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase + } + + } while (mem_ptr > mem_start); + + return 0; +} +. + +define /R unsigned char * find_debug_info_table_header(system_table) + unsigned char *system_table; +{ + unsigned long configuration_table_entries; + unsigned char *configuration_table; + unsigned long index; + unsigned char debug_table_guid[16]; + + // Fill in the debug table's guid + debug_table_guid[ 0] = 0x77; + debug_table_guid[ 1] = 0x2E; + debug_table_guid[ 2] = 0x15; + debug_table_guid[ 3] = 0x49; + debug_table_guid[ 4] = 0xDA; + debug_table_guid[ 5] = 0x1A; + debug_table_guid[ 6] = 0x64; + debug_table_guid[ 7] = 0x47; + debug_table_guid[ 8] = 0xB7; + debug_table_guid[ 9] = 0xA2; + debug_table_guid[10] = 0x7A; + debug_table_guid[11] = 0xFE; + debug_table_guid[12] = 0xFE; + debug_table_guid[13] = 0xD9; + debug_table_guid[14] = 0x5E; + debug_table_guid[15] = 0x8B; + + configuration_table_entries = *(unsigned long *)(system_table + 64); + configuration_table = *(unsigned long *)(system_table + 68); + + for (index = 0; index < configuration_table_entries; index++) + { + if (compare_guid(configuration_table, debug_table_guid) == 0) + { + return *(unsigned long *)(configuration_table + 16); + } + + configuration_table += 20; + } + + return 0; +} +. + +define /R int valid_pe_header(header) + unsigned char *header; +{ + if ((header[0x00] == 'M') && + (header[0x01] == 'Z') && + (header[0x80] == 'P') && + (header[0x81] == 'E')) + { + return 1; + } + + return 0; +} +. + +define /R unsigned long pe_headersize(header) + unsigned char *header; +{ + unsigned long *size; + + size = header + 0x00AC; + + return *size; +} +. + +define /R unsigned char *pe_filename(header) + unsigned char *header; +{ + unsigned long *debugOffset; + unsigned char *stringOffset; + + if (valid_pe_header(header)) + { + debugOffset = header + 0x0128; + stringOffset = header + *debugOffset + 0x002C; + + return stringOffset; + } + + return 0; +} +. + +define /R int char_is_valid(c) + unsigned char c; +{ + if (c >= 32 && c < 127) + return 1; + + return 0; +} +. + +define /R write_symbols_file(filename, mem_start, mem_size) + unsigned char *filename; + unsigned char *mem_start; + unsigned long mem_size; +{ + unsigned char *system_table; + unsigned char *debug_info_table_header; + unsigned char *debug_info_table; + unsigned long debug_info_table_size; + unsigned long index; + unsigned char *debug_image_info; + unsigned char *loaded_image_protocol; + unsigned char *image_base; + unsigned char *debug_filename; + unsigned long header_size; + int status; + + system_table = find_system_table(mem_start, mem_size); + if (system_table == 0) + { + return; + } + + status = fopen(88, filename, "w"); + + debug_info_table_header = find_debug_info_table_header(system_table); + + debug_info_table = *(unsigned long *)(debug_info_table_header + 8); + debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4); + + for (index = 0; index < (debug_info_table_size * 4); index += 4) + { + debug_image_info = *(unsigned long *)(debug_info_table + index); + + if (debug_image_info == 0) + { + break; + } + + loaded_image_protocol = *(unsigned long *)(debug_image_info + 4); + + image_base = *(unsigned long *)(loaded_image_protocol + 32); + + debug_filename = pe_filename(image_base); + header_size = pe_headersize(image_base); + + $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$; + } + + + fclose(88); +} +. + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_unload_symbols.inc b/PandaBoardPkg/Debugger_scripts/rvi_unload_symbols.inc new file mode 100644 index 000000000..546c4f960 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_unload_symbols.inc @@ -0,0 +1,118 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +error = continue + +unload + +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 + +error = abort diff --git a/PandaBoardPkg/Debugger_scripts/trace32_load_symbols.cmm b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols.cmm new file mode 100644 index 000000000..c70a67393 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols.cmm @@ -0,0 +1,215 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + + ENTRY &ram_start &ram_size + + ;If system is running then stop the execution so we can load symbols. + break + + ;Reset all windows + WINPAGE.RESET + + ;Create AREA to display the symbols we are loading. + AREA.Reset + AREA.Create SYMBOL 300. 100. + AREA.View SYMBOL + AREA.Select SYMBOL + + // SYS.Option BE OFF + + ;Added based on suggestion from Lauterbach support. + MMU.TABLEWALK ON + MMU.ON + + ;Load symbols. + GOSUB load_symbols &ram_start &ram_size + + ;Open some windows and enable semihosting. + TOOLBAR ON + STATUSBAR ON + WINPAGE.RESET + + WINCLEAR + WINPOS 0.0 17.0 72. 13. 0. 0. W000 + SYStem + + WINPOS 0.0 0.0 110. 55. 13. 1. W001 + WINTABS 10. 10. 25. 62. + Data.List + + WINPAGE.SELECT P000 + + //Enable semihosting + // System.Option.BigEndian OFF + + tronchip.set swi on // ARM9/10/11 variant + + // configure and open semihosting channel + winpos 50% 50% 50% 50% + term.heapinfo 0 0x20000 0x30000 0x20000 + term.method armswi + term.mode string + term.gate + + WINPOS 115.0 0. 70. 35. 0. 1. W002 + Var.Local %HEX + + WINPOS 115.10 45. 48. 9. 0. 0. W003 + Register + + END + +find_system_table: + ENTRY &mem_start &mem_size + &mem_ptr=&mem_start+&mem_size + RPT + ( + &mem_ptr=&mem_ptr-0x400000 // 4 MB + &word1=Data.LONG(D:&mem_ptr) + &word2=Data.LONG(D:&mem_ptr+0x04) + IF &word1==0x20494249 + ( + IF &word2==0x54535953 + ( + &result=Data.LONG(D:&mem_ptr+0x08) + RETURN &result + ) + ) + ) + WHILE &mem_ptr>&mem_start + &result=0 + RETURN &result + +compare_guid: + ENTRY &guid + IF Data.LONG(D:&guid)==0x49152E77 + ( + IF Data.LONG(D:&guid+0x04)==0x47641ADA + ( + IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7 + ( + IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE + ( + RETURN 0 + ) + ) + ) + ) + RETURN 1 + +find_debug_info_table_header: + ENTRY &system_table + &config_table_entries=Data.LONG(D:&system_table+0x40) + &config_table_pointer=Data.LONG(D:&system_table+0x44) + RPT &config_table_entries + ( + GOSUB compare_guid &config_table_pointer + ENTRY &result + IF &result==0 + ( + &result=Data.LONG(D:&config_table_pointer+0x10) + RETURN &result + ) + &config_table_pointer=&config_table_pointer+0x14 + ) + RETURN 0; + +valid_pe_header: + ENTRY &header + IF Data.BYTE(D:&header+0x00)==0x4D + ( + IF Data.BYTE(D:&header+0x01)==0x5A + ( + IF Data.BYTE(D:&header+0x80)==0x50 + ( + IF Data.BYTE(D:&header+0x81)==0x45 + ( + RETURN 1 + ) + ) + ) + ) + RETURN 0 + +get_file_string: + ENTRY &stringOffset + + local &string + + &more_string=data.string(d:&stringOffset) + + if (string.len("&more_string")>=128.) + ( + &string="&string"+"&more_string" + &stringOffset=&stringOffset+string.len("&more_string") + + //Get remaining file string + GOSUB get_file_string &stringOffset + ENTRY &more_string + &string="&string"+"&more_string" + ) + else + ( + &string="&string"+"&more_string" + &more_string="" + ) + RETURN &string + +load_symbol_file: + ENTRY &header &load_address + GOSUB valid_pe_header &header + ENTRY &result + + IF &result==1 + ( + &debugOffset=Data.LONG(D:&header+0x0128) + &stringOffset=&header+&debugOffset+0x002C + + GOSUB get_file_string &stringOffset + ENTRY &filestring + + // the below has to be customized per your environment + &filestring="x:"+string.mid("&filestring", 36., string.len("&filestring")) + + PRINT "&filestring 0x" &load_address + TDIAG Data.load.elf &filestring &load_address /nocode /noclear + ) + RETURN + +pe_headersize: + ENTRY &header; + RETURN Data.LONG(D:&header+0x00AC) + +load_symbols: + ENTRY &mem_start &mem_size + GOSUB find_system_table &mem_start &mem_size + ENTRY &system_table + GOSUB find_debug_info_table_header &system_table + ENTRY &debug_info_table_header + &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08) + &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04) + &index=0 + RPT &debug_info_table_size + ( + &debug_image_info=Data.LONG(D:&debug_info_table+&index) + IF &debug_image_info==0 + RETURN + &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04); + &image_base=Data.LONG(D:&loaded_image_protocol+0x20); + GOSUB pe_headersize &image_base + ENTRY &header_size + &image_load_address=&image_base+&header_size + GOSUB load_symbol_file &image_base &image_load_address + &index=&index+0x4 + ) + + RETURN diff --git a/PandaBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm new file mode 100644 index 000000000..13943aad6 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm @@ -0,0 +1,188 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + + ENTRY &ram_start &ram_size + + ;If system is running then stop the execution so we can load symbols. + break + + ;Reset all windows + WINPAGE.RESET + + AREA.Reset + AREA.Create SYMBOL 300. 100. + AREA.View SYMBOL + AREA.Select SYMBOL + SYS.Option BE OFF + + ; Added based on suggestion from Lauterbach support. + MMU.TABLEWALK ON + MMU.ON + + GOSUB load_symbols &ram_start &ram_size + + ;Open some windows. + WINPOS 83.125 29.063 48. 9. 0. 0. W003 + Register + + WINPOS 83.25 10. 48. 9. 0. 1. W002 + Var.Local + + END + +find_system_table: + ENTRY &mem_start &mem_size + &mem_ptr=&mem_start+&mem_size + RPT + ( + &mem_ptr=&mem_ptr-0x400000 // 4 MB + &word1=Data.LONG(D:&mem_ptr) + &word2=Data.LONG(D:&mem_ptr+0x04) + IF &word1==0x20494249 + ( + IF &word2==0x54535953 + ( + &result=Data.LONG(D:&mem_ptr+0x08) + RETURN &result + ) + ) + ) + WHILE &mem_ptr>&mem_start + &result=0 + RETURN &result + +compare_guid: + ENTRY &guid + IF Data.LONG(D:&guid)==0x49152E77 + ( + IF Data.LONG(D:&guid+0x04)==0x47641ADA + ( + IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7 + ( + IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE + ( + RETURN 0 + ) + ) + ) + ) + RETURN 1 + +find_debug_info_table_header: + ENTRY &system_table + &config_table_entries=Data.LONG(D:&system_table+0x40) + &config_table_pointer=Data.LONG(D:&system_table+0x44) + RPT &config_table_entries + ( + GOSUB compare_guid &config_table_pointer + ENTRY &result + IF &result==0 + ( + &result=Data.LONG(D:&config_table_pointer+0x10) + RETURN &result + ) + &config_table_pointer=&config_table_pointer+0x14 + ) + RETURN 0; + +valid_pe_header: + ENTRY &header + IF Data.BYTE(D:&header+0x00)==0x4D + ( + IF Data.BYTE(D:&header+0x01)==0x5A + ( + IF Data.BYTE(D:&header+0x80)==0x50 + ( + IF Data.BYTE(D:&header+0x81)==0x45 + ( + RETURN 1 + ) + ) + ) + ) + RETURN 0 + +get_file_string: + ENTRY &stringOffset + + local &string + + &more_string=data.string(d:&stringOffset) + + if (string.len("&more_string")>=128.) + ( + &string="&string"+"&more_string" + &stringOffset=&stringOffset+string.len("&more_string") + + //Get remaining file string + GOSUB get_file_string &stringOffset + ENTRY &more_string + &string="&string"+"&more_string" + ) + else + ( + &string="&string"+"&more_string" + &more_string="" + ) + RETURN &string + +load_symbol_file: + ENTRY &header &load_address + GOSUB valid_pe_header &header + ENTRY &result + + IF &result==1 + ( + &debugOffset=Data.LONG(D:&header+0x0128) + &stringOffset=&header+&debugOffset+0x002C + + &stringOffset=&stringOffset+11. + + GOSUB get_file_string &stringOffset + ENTRY &filestring + + &filestring="c:"+"&filestring" + + PRINT "&filestring 0x" &load_address + Data.load.elf &filestring &load_address /nocode /noclear + ) + RETURN + +pe_headersize: + ENTRY &header; + RETURN Data.LONG(D:&header+0x00AC) + +load_symbols: + ENTRY &mem_start &mem_size + GOSUB find_system_table &mem_start &mem_size + ENTRY &system_table + GOSUB find_debug_info_table_header &system_table + ENTRY &debug_info_table_header + &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08) + &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04) + &index=0 + RPT &debug_info_table_size + ( + &debug_image_info=Data.LONG(D:&debug_info_table+&index) + IF &debug_image_info==0 + RETURN + &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04); + &image_base=Data.LONG(D:&loaded_image_protocol+0x20); + GOSUB pe_headersize &image_base + ENTRY &header_size + &image_load_address=&image_base+&header_size + GOSUB load_symbol_file &image_base &image_load_address + &index=&index+0x4 + ) + + RETURN +
\ No newline at end of file diff --git a/PandaBoardPkg/Include/PandaBoard.h b/PandaBoardPkg/Include/PandaBoard.h new file mode 100644 index 000000000..3f806e8e2 --- /dev/null +++ b/PandaBoardPkg/Include/PandaBoard.h @@ -0,0 +1,182 @@ +/** @file +* Header defining the PandaBoard constants (Base addresses, sizes, flags) +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __PANDABOARD_PLATFORM_H__ +#define __PANDABOARD_PLATFORM_H__ + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +#if 0 +// SoC registers. L3 interconnects +#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000 +#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE +#endif + +// GPMC +#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x50000000 +#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + +// SoC registers. L4 interconnects +#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000 +#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + + +#if 0 +/******************************************* +// Platform Memory Map +*******************************************/ + +// Can be NOR, DOC, DRAM, SRAM +#define ARM_EB_REMAP_BASE 0x00000000 +#define ARM_EB_REMAP_SZ 0x04000000 + +// Motherboard Peripheral and On-chip peripheral +#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000 +#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000 +#define ARM_EB_BOARD_PERIPH_BASE 0x10000000 +//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000 + +// SMC +#define ARM_EB_SMC_BASE 0x40000000 +#define ARM_EB_SMC_SZ 0x20000000 + +// NOR Flash 1 +#define ARM_EB_SMB_NOR_BASE 0x40000000 +#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */ +// DOC Flash +#define ARM_EB_SMB_DOC_BASE 0x44000000 +#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */ +// SRAM +#define ARM_EB_SMB_SRAM_BASE 0x48000000 +#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */ +// USB, Ethernet, VRAM +#define ARM_EB_SMB_PERIPH_BASE 0x4E000000 +//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000 +#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */ + +// DRAM +#define ARM_EB_DRAM_BASE 0x70000000 +#define ARM_EB_DRAM_SZ 0x10000000 + +// Logic Tile +#define ARM_EB_LOGIC_TILE_BASE 0xC0000000 +#define ARM_EB_LOGIC_TILE_SZ 0x40000000 + +/******************************************* +// Motherboard peripherals +*******************************************/ + +// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE) +#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030) +#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030) +#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034) +#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038) +#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038) +#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C) +#define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050) +#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084) +#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088) +#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0) +#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4) +#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8) + +// SP810 Controller +#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000) + +// SYSTRCL Register +#define ARM_EB_SYSCTRL 0x10001000 + +// Uart0 +#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000) +#define PL011_CONSOLE_UART_SPEED 115200 + +// SP804 Timer Bases +#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000) +#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020) +#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000) +#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020) + +// PL301 RTC +#define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000) + +// Dynamic Memory Controller Base +#define ARM_EB_DMC_BASE 0x10018000 + +// Static Memory Controller Base +#define ARM_EB_SMC_CTRL_BASE 0x10080000 + +#define PL111_CLCD_BASE 0x10020000 +//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption +#define PL111_CLCD_VRAM_BASE 0x78000000 + +#define ARM_EB_SYS_OSCCLK4 0x1000001C + + +/*// System Configuration Controller register Base addresses +//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000 +#define ARM_EB_SYS_CFGRW0_REG 0x100E2000 +#define ARM_EB_SYS_CFGRW1_REG 0x100E2004 +#define ARM_EB_SYS_CFGRW2_REG 0x100E2008 + +#define ARM_EB_CFGRW1_REMAP_NOR0 0 +#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28) +#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29) +#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30) + +// PL301 Fast AXI Base Address +#define ARM_EB_FAXI_BASE 0x100E9000 + +// L2x0 Cache Controller Base Address +//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/ + + +// PL031 RTC - Other settings +#define PL031_PPM_ACCURACY 300000000 + +/******************************************* +// Interrupt Map +*******************************************/ + +// Timer Interrupts +#define TIMER01_INTERRUPT_NUM 34 +#define TIMER23_INTERRUPT_NUM 35 + + +/******************************************* +// EFI Memory Map in Permanent Memory (DRAM) +*******************************************/ + +// This region is allocated at the bottom of the DRAM. It will be used +// for fixed address allocations such as Vector Table +#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB + +// This region is the memory declared to PEI as permanent memory for PEI +// and DXE. EFI stacks and heaps will be declared in this region. +#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000 +#endif + +#endif + +typedef enum { + PANDABOARD_REVISION_UNKNOWN=0, + PANDABOARD_REVISION_PANDA, + PANDABOARD_REVISION_PANDAES + +} PANDABOARD_REVISION; diff --git a/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.c b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.c new file mode 100644 index 000000000..a303e606b --- /dev/null +++ b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.c @@ -0,0 +1,299 @@ +/** @file + Add custom commands for PandaBoard development. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiDxe.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/EblCmdLib.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> +#include <Library/EfiFileLib.h> +#include <Library/ArmDisassemblerLib.h> +#include <Library/PeCoffGetEntryPointLib.h> +#include <Library/PerformanceLib.h> +#include <Library/TimerLib.h> + +#include <Guid/DebugImageInfoTable.h> + +#include <Protocol/DebugSupport.h> +#include <Protocol/LoadedImage.h> + +/** + Simple arm disassembler via a library + + Argv[0] - symboltable + Argv[1] - Optional quoted format string + Argv[2] - Optional flag + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblSymbolTable ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + EFI_STATUS Status; + EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugImageTableHeader = NULL; + EFI_DEBUG_IMAGE_INFO *DebugTable; + UINTN Entry; + CHAR8 *Format; + CHAR8 *Pdb; + UINT32 PeCoffSizeOfHeaders; + UINT32 ImageBase; + BOOLEAN Elf; + + // Need to add lots of error checking on the passed in string + // Default string is for RealView debugger or gdb depending on toolchain used. + if (Argc > 1) { + Format = Argv[1]; + } else { +#if __GNUC__ + // Assume gdb + Format = "add-symbol-file %a 0x%x"; +#else + // Default to RVCT + Format = "load /a /ni /np %a &0x%x"; +#endif + } + Elf = (Argc > 2) ? FALSE : TRUE; + + Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugImageTableHeader); + if (EFI_ERROR (Status)) { + return Status; + } + + DebugTable = DebugImageTableHeader->EfiDebugImageInfoTable; + if (DebugTable == NULL) { + return EFI_SUCCESS; + } + + for (Entry = 0; Entry < DebugImageTableHeader->TableSize; Entry++, DebugTable++) { + if (DebugTable->NormalImage != NULL) { + if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) && (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) { + ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase; + PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)ImageBase); + Pdb = PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase); + if (Pdb != NULL) { + if (Elf) { + // ELF and Mach-O images don't include the header so the linked address does not include header + ImageBase += PeCoffSizeOfHeaders; + } + AsciiPrint (Format, Pdb, ImageBase); + AsciiPrint ("\n"); + } else { + } + } + } + } + + return EFI_SUCCESS; +} + + +/** + Simple arm disassembler via a library + + Argv[0] - disasm + Argv[1] - Address to start disassembling from + ARgv[2] - Number of instructions to disassembly (optional) + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblDisassembler ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + UINT8 *Ptr, *CurrentAddress; + UINT32 Address; + UINT32 Count; + CHAR8 Buffer[80]; + UINT32 ItBlock; + + if (Argc < 2) { + return EFI_INVALID_PARAMETER; + } + + Address = AsciiStrHexToUintn (Argv[1]); + Count = (Argc > 2) ? (UINT32)AsciiStrHexToUintn (Argv[2]) : 20; + + Ptr = (UINT8 *)(UINTN)Address; + ItBlock = 0; + do { + CurrentAddress = Ptr; + DisassembleInstruction (&Ptr, TRUE, TRUE, &ItBlock, Buffer, sizeof (Buffer)); + AsciiPrint ("0x%08x: %a\n", CurrentAddress, Buffer); + } while (Count-- > 0); + + + return EFI_SUCCESS; +} + + +CHAR8 * +ImageHandleToPdbFileName ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + CHAR8 *Pdb; + CHAR8 *StripLeading; + + Status = gBS->HandleProtocol (Handle, &gEfiLoadedImageProtocolGuid, (VOID **)&LoadedImage); + if (EFI_ERROR (Status)) { + return ""; + } + + Pdb = PeCoffLoaderGetPdbPointer (LoadedImage->ImageBase); + StripLeading = AsciiStrStr (Pdb, "\\ARM\\"); + if (StripLeading == NULL) { + StripLeading = AsciiStrStr (Pdb, "/ARM/"); + if (StripLeading == NULL) { + return Pdb; + } + } + // Hopefully we hacked off the unneeded part + return (StripLeading + 5); +} + + +CHAR8 *mTokenList[] = { + "SEC", + "PEI", + "DXE", + "BDS", + NULL +}; + +/** + Simple arm disassembler via a library + + Argv[0] - disasm + Argv[1] - Address to start disassembling from + ARgv[2] - Number of instructions to disassembly (optional) + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblPerformance ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + UINTN Key; + CONST VOID *Handle; + CONST CHAR8 *Token, *Module; + UINT64 Start, Stop, TimeStamp; + UINT64 Delta, TicksPerSecond, Milliseconds, Microseconds; + UINTN Index; + + TicksPerSecond = GetPerformanceCounterProperties (NULL, NULL); + + Key = 0; + do { + Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop); + if (Key != 0) { + if (AsciiStriCmp ("StartImage:", Token) == 0) { + if (Stop == 0) { + // The entry for EBL is still running so the stop time will be zero. Skip it + AsciiPrint (" running %a\n", ImageHandleToPdbFileName ((EFI_HANDLE)Handle)); + } else { + Delta = Stop - Start; + Microseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000000), TicksPerSecond, NULL); + AsciiPrint ("%10ld us %a\n", Microseconds, ImageHandleToPdbFileName ((EFI_HANDLE)Handle)); + } + } + } + } while (Key != 0); + + AsciiPrint ("\n"); + + TimeStamp = 0; + Key = 0; + do { + Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop); + if (Key != 0) { + for (Index = 0; mTokenList[Index] != NULL; Index++) { + if (AsciiStriCmp (mTokenList[Index], Token) == 0) { + Delta = Stop - Start; + TimeStamp += Delta; + Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL); + AsciiPrint ("%6a %6ld ms\n", Token, Milliseconds); + break; + } + } + } + } while (Key != 0); + + AsciiPrint ("Total Time = %ld ms\n\n", DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL)); + + return EFI_SUCCESS; +} + + +GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] = +{ + { + "disasm address [count]", + " disassemble count instructions", + NULL, + EblDisassembler + }, + { + "performance", + " Display boot performance info", + NULL, + EblPerformance + }, + { + "symboltable [\"format string\"] [PECOFF]", + " show symbol table commands for debugger", + NULL, + EblSymbolTable + } +}; + + +VOID +EblInitializeExternalCmd ( + VOID + ) +{ + EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE)); + return; +} diff --git a/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.inf b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.inf new file mode 100644 index 000000000..594956eb7 --- /dev/null +++ b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.inf @@ -0,0 +1,53 @@ +#/** @file +# Component description file for the entry point to a EFIDXE Drivers +# +# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification +# Copyright (c) 2007 - 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardEblCmdLib + FILE_GUID = ea62bdc3-1063-425f-8851-98cb47f213a8 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + EblCmdLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + ArmDisassemblerLib + PerformanceLib + TimerLib + +[Protocols] + gEfiDebugSupportProtocolGuid + gEfiLoadedImageProtocolGuid + +[Guids] + gEfiDebugImageInfoTableGuid diff --git a/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.c b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.c new file mode 100644 index 000000000..9072c5856 --- /dev/null +++ b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.c @@ -0,0 +1,103 @@ +/** @file + Basic serial IO abstaction for GDB + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> +#include <Library/GdbSerialLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +RETURN_STATUS +EFIAPI +GdbSerialLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return RETURN_SUCCESS; +} + +RETURN_STATUS +EFIAPI +GdbSerialInit ( + IN UINT64 BaudRate, + IN UINT8 Parity, + IN UINT8 DataBits, + IN UINT8 StopBits + ) +{ + return RETURN_SUCCESS; +} + +BOOLEAN +EFIAPI +GdbIsCharAvailable ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + + if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { + return TRUE; + } else { + return FALSE; + } +} + +CHAR8 +EFIAPI +GdbGetChar ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 RBR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_RBR_REG; + CHAR8 Char; + + while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); + Char = MmioRead8(RBR); + + return Char; +} + +VOID +EFIAPI +GdbPutChar ( + IN CHAR8 Char + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 THR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_THR_REG; + + while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); + MmioWrite8(THR, Char); +} + +VOID +GdbPutString ( + IN CHAR8 *String + ) +{ + while (*String != '\0') { + GdbPutChar (*String); + String++; + } +} + + + + diff --git a/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf new file mode 100644 index 000000000..a9eb2a745 --- /dev/null +++ b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = GdbSerialLib + FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = GdbSerialLib + + CONSTRUCTOR = GdbSerialLibConstructor + + +[Sources.common] + GdbSerialLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + IoLib + OmapLib + +[FixedPcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + diff --git a/PandaBoardPkg/Library/PandaBoardLib/Clock.c b/PandaBoardPkg/Library/PandaBoardLib/Clock.c new file mode 100644 index 000000000..6e3ffbf47 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/Clock.c @@ -0,0 +1,257 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/IoLib.h> +#include <Library/DebugLib.h> + +#include <PandaBoard.h> +#include <Omap4430/Omap4430.h> + +VOID +VolConSetup ( + IN UINTN PmcSlaveAddr, + IN UINTN SmpsAddr, + IN UINTN Data + ) +{ + // Setup VolCon command + MmioWrite32 (PRM_VC_VAL_BYPASS, + ((Data<<PRM_VC_VAL_BYPASS_DATA_POS)| + (SmpsAddr<<PRM_VC_VAL_BYPASS_REGADDR_POS)| + (PmcSlaveAddr)) ); + + // Validate command + MmioOr32 (PRM_VC_VAL_BYPASS, BIT24); + + // Wait for command completion + while( MmioRead32(PRM_VC_VAL_BYPASS) & BIT24 ); +} + +VOID +VolConInit ( + VOID + ) +{ + // Sram Ldo Voltage Control Override (MPU, CORE, IVA) + MmioWrite32 (CONTROL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL, + CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL); + MmioWrite32 (CONTROL_CORE_LDOSRAM_MPU_VOLTAGE_CTRL, + CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL); + MmioWrite32 (CONTROL_CORE_LDOSRAM_CORE_VOLTAGE_CTRL, + CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL); + + // Voltage controller setup + MmioWrite32 (PRM_VC_CFG_I2C_MODE, VC_CFG_I2C_MODE_VAL); + MmioWrite32 (PRM_VC_CFG_I2C_CLK, VC_CFG_I2C_CLK_VAL); +} + +VOID +ClockModuleEnable ( + IN UINTN Addr, + IN UINTN Mode + ) +{ + MmioOr32 (Addr, Mode); + while( (MmioRead32(Addr) & (BIT16|BIT17)) != 0 ); +} + +VOID +ClockInit ( + PANDABOARD_REVISION BoardRevision + ) +{ + // Init Voltage Controller + VolConInit (); + + // Setup CORE, MPU, IVA voltages for OPP100 operation + + ClockModuleEnable (0x4A307838, 0x1); //cm_wkup_gpio1_clkctrl: AUTO + + if( BoardRevision == PANDABOARD_REVISION_PANDAES ) { + // TPS62361 => VDD_MPU + // TWL6030 VCORE2 => VDD_IVA + // TWL6030 VCORE1 => VDD_CORE + + // Setup CORE voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE1_CFG_FORCE_REGADDR, + PMIC_VCORE1_CFG_FORCE_VSEL_VDD_CORE_4460); + + // Clear TPS VSEL0 + MmioAnd32 (GPIO1_BASE + GPIO_OE, ~BIT7); + MmioOr32 (GPIO1_BASE + GPIO_CLEARDATAOUT, BIT7); + + // Setup MPU voltage + VolConSetup(TPS62361_SLAVE_ADDR, + TPS62361_SET1_REG_ADDR, + TPS62361_SET1_REG_VAL); + + // Set TPS VSEL0 + MmioOr32 (GPIO1_BASE + GPIO_SETDATAOUT, BIT7); + } + else { + // TWL6030 VCORE1 => VDD_MPU + // TWL6030 VCORE2 => VDD_IVA + // TWL6030 VCORE3 => VDD_CORE + + // Setup CORE voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE3_CFG_FORCE_REGADDR, + PMIC_VCORE3_CFG_FORCE_VSEL); + + // Setup MPU voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE1_CFG_FORCE_REGADDR, + PMIC_VCORE1_CFG_FORCE_VSEL_VDD_MPU_4430); + } + + // Setup IVA voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE2_CFG_FORCE_REGADDR, + PMIC_VCORE2_CFG_FORCE_VSEL); + + // Accelerate MPU frequency + MmioWrite32 (CKGEN_CM1_CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_MPU_OPP100_VAL); + + // Accelerate CORE clocks + MmioWrite32 (CKGEN_CM1_CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_OPP100_VAL); + + // Start core frequency update + MmioWrite32 ( CKGEN_CM1_CM_SHADOW_FREQ_CONFIG1, + (CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_M2_DIV_OPP100| + CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_DPLL_EN_LOCK| + CM_SHADOW_FREQ_CONFIG1_DLL_RESET_RST| + CM_SHADOW_FREQ_CONFIG1_FREQ_UPDATE_START)); + + // Wait for core frequency update completion + while( (MmioRead32(CKGEN_CM1_CM_SHADOW_FREQ_CONFIG1) & (BIT0)) != 0 ); + + // Setup and lock IVA DPLL + MmioWrite32 (CKGEN_CM1_CM_CLKSEL_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKSEL_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M4_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M4_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M5_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M5_VAL); + MmioWrite32 (CKGEN_CM1_CM_BYPCLK_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_BYCLK_VAL); + MmioWrite32 (CKGEN_CM1_CM_CLKMODE_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKMODE_VAL); + + // Setup and lock ABE DPLL + MmioWrite32 (CKGEN_CM1_CM_CLKSEL_DPLL_ABE, + CKGEN_CM1_CM_CLKSEL_DPLL_ABE_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M2_DPLL_ABE, + CKGEN_CM1_CM_DIV_M2_DPLL_ABE_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M3_DPLL_ABE, + CKGEN_CM1_CM_DIV_M3_DPLL_ABE_VAL); + MmioWrite32 (CKGEN_CM1_CM_CLKMODE_DPLL_ABE, + CKGEN_CM1_CM_CLKMODE_DPLL_ABE_VAL); + + // Setup and lock USB DPLL + MmioWrite32 (CKGEN_CM2_CM_CLKSEL_DPLL_USB, + CKGEN_CM2_CM_CLKSEL_DPLL_USB_VAL); + MmioWrite32 (CKGEN_CM2_CM_DIV_M2_DPLL_USB, + CKGEN_CM2_CM_DIV_M2_DPLL_USB_VAL); + MmioWrite32 (CKGEN_CM2_CM_CLKMODE_DPLL_USB, + CKGEN_CM2_CM_CLKMODE_DPLL_USB_VAL); + + MmioOr32 (0x4A009020, 0x100); //ISS_CLKCTRL_OPTFCLKEN + MmioOr32 (0x4A009120, 0xF00); //DSS_CLKCTRL_OPTFCLKEN + + MmioWrite32 (0x4A008900, 0x2); //cm_mpu_m3_clkstctrl: SW_WKUP + MmioWrite32 (0x4A008F00, 0x2); //cm_ivahd_clkstctrl: SW_WKUP + MmioWrite32 (0x4A004400, 0x2); //cm_dsp_clkstctrl: SW_WKUP + MmioWrite32 (0x4A009100, 0x2); //cm_dss_clkstctrl: SW_WKUP + MmioWrite32 (0x4A009200, 0x2); //cm_sgx_clkstctrl: SW_WKUP + MmioWrite32 (0x4A004500, 0x2); //cm1_abe_clkstctrl: SW_WKUP + MmioWrite32 (0x4A008C00, 0x2); //cm_c2c_clkstctrl: SW_WKUP + MmioWrite32 (0x4A009000, 0x2); //cm_cam_clkstctrl: SW_WKUP + MmioWrite32 (0x4A008A00, 0x2); //cm_sdma_clkstctrl: SW_WKUP + + MmioWrite32 (0x4A008E20, 0x1); //cm_l3instr_l3_3_clkctrl: AUTO + MmioWrite32 (0x4A008E28, 0x1); //cm_l3instr_l3_instr_clkctrl: AUTO + MmioWrite32 (0x4A008E40, 0x1); //cm_l3instr_intrconn_wp1_clkctrl: AUTO + MmioWrite32 (0x4A009338, 0x1); //cm_l3init_hsi_clkctrl: AUTO + + ClockModuleEnable (0x4A004528, 0x2); //cm1_abe_aess_clkctrl: ENABLE + + // TODO: pdm needs clock enabled externally to make it functional + MmioWrite32 (0x4A004530, 0x2); //cm1_abe_pdm_clkctrl: ENABLE + + ClockModuleEnable (0x4A004538, 0x2); //cm1_abe_dmic_clkctrl: ENABLE + ClockModuleEnable (0x4A004540, 0x2); //cm1_abe_mcasp_clkctrl: ENABLE + ClockModuleEnable (0x4A004548, 0x2); //cm1_abe_mcbsp1_clkctrl: ENABLE + ClockModuleEnable (0x4A004550, 0x2); //cm1_abe_mcbsp2_clkctrl: ENABLE + ClockModuleEnable (0x4A004558, 0x2); //cm1_abe_mcbsp3_clkctrl: ENABLE + ClockModuleEnable (0x4A004560, 0x2); //cm1_abe_slimbus_clkctrl: ENABLE + ClockModuleEnable (0x4A004568, 0x2); //cm1_abe_timer5_clkctrl: ENABLE + ClockModuleEnable (0x4A004570, 0x2); //cm1_abe_timer6_clkctrl: ENABLE + ClockModuleEnable (0x4A004578, 0x2); //cm1_abe_timer7_clkctrl: ENABLE + ClockModuleEnable (0x4A004580, 0x2); //cm1_abe_timer8_clkctrl: ENABLE + ClockModuleEnable (0x4A004588, 0x2); //cm1_abe_wdt3_clkctrl: ENABLE + ClockModuleEnable (0x4A009450, 0x2); //cm_l4per_gptimer9_clkctrl: ENABLE + ClockModuleEnable (0x4A009428, 0x2); //cm_l4per_gptimer10_clkctrl: ENABLE + ClockModuleEnable (0x4A009430, 0x2); //cm_l4per_gptimer11_clkctrl: ENABLE + ClockModuleEnable (0x4A009440, 0x2); //cm_l4per_gptimer3_clkctrl: ENABLE + ClockModuleEnable (0x4A009448, 0x2); //cm_l4per_gptimer4_clkctrl: ENABLE + ClockModuleEnable (0x4A009488, 0x2); //cm_l4per_hdq1w_clkctrl: ENABLE + ClockModuleEnable (0x4A0094E0, 0x2); //cm_l4per_mcbsp4_clkctrl: ENABLE + ClockModuleEnable (0x4A0094F8, 0x2); //cm_l4per_mcspi2_clkctrl: ENABLE + ClockModuleEnable (0x4A009500, 0x2); //cm_l4per_mcspi3_clkctrl: ENABLE + ClockModuleEnable (0x4A009508, 0x2); //cm_l4per_mcspi4_clkctrl: ENABLE + ClockModuleEnable (0x4A009520, 0x2); //cm_l4per_mmcsd3_clkctrl: ENABLE + ClockModuleEnable (0x4A009528, 0x2); //cm_l4per_mmcsd4_clkctrl: ENABLE + ClockModuleEnable (0x4A009560, 0x2); //cm_l4per_mmcsd5_clkctrl: ENABLE + ClockModuleEnable (0x4A009540, 0x2); //cm_l4per_uart1_clkctrl: ENABLE + ClockModuleEnable (0x4A009548, 0x2); //cm_l4per_uart2_clkctrl: ENABLE + ClockModuleEnable (0x4A009558, 0x2); //cm_l4per_uart4_clkctrl: ENABLE + ClockModuleEnable (0x4A009438, 0x2); //gptimer2: ENABLE + ClockModuleEnable (0x4A009460, 0x1); //gpio2: AUTO + ClockModuleEnable (0x4A009468, 0x1); //gpio3: AUTO + ClockModuleEnable (0x4A009470, 0x101); //gpio4: AUTO+FCLK + ClockModuleEnable (0x4A009478, 0x1); //gpio5: AUTO + ClockModuleEnable (0x4A009480, 0x1); //gpio6: AUTO + ClockModuleEnable (0x4A0094A8, 0x2); //i2c2: ENABLE + ClockModuleEnable (0x4A0094B0, 0x2); //i2c3: ENABLE + ClockModuleEnable (0x4A0094B8, 0x2); //i2c4: ENABLE + ClockModuleEnable (0x4A0094F0, 0x2); //mcspi1: ENABLE + ClockModuleEnable (0x4A307878, 0x2); //cm_wkup_keyboard_clkctrl: ENABLE + ClockModuleEnable (0x4A009020, 0x2); //cm_cam_iss_clkctrl: ENABLE + ClockModuleEnable (0x4A009028, 0x2); //cm_cam_fdif_clkctrl: ENABLE + ClockModuleEnable (0x4A009120, 0x2); //cm_dss_dss_clkctrl: ENABLE + ClockModuleEnable (0x4A009220, 0x2); //cm_sgx_sgx_clkctrl: ENABLE + ClockModuleEnable (0x4A009328, 0x1040002); //mmchs1: ENABLE + ClockModuleEnable (0x4A009330, 0x1040002); //mmchs2: ENABLE + ClockModuleEnable (0x4A009358, 0xFF02); //cm_l3init_hsusbhost_clkctrl: ENABLE + ClockModuleEnable (0x4A009368, 0x1); //usbtll: AUTO + + MmioWrite32 (0x4A008900, 0x3); //cm_mpu_m3_clkstctrl: HW_AUTO + MmioWrite32 (0x4A008F00, 0x3); //cm_ivahd_clkstctrl: HW_AUTO + MmioWrite32 (0x4A004400, 0x3); //cm_dsp_clkstctrl: HW_AUTO + MmioWrite32 (0x4A009100, 0x3); //cm_dss_clkstctrl: HW_AUTO + MmioWrite32 (0x4A009200, 0x3); //cm_sgx_clkstctrl: HW_AUTO + MmioWrite32 (0x4A004500, 0x3); //cm1_abe_clkstctrl: HW_AUTO + MmioWrite32 (0x4A008C00, 0x3); //cm_c2c_clkstctrl: HW_AUTO + MmioWrite32 (0x4A008A00, 0x3); //cm_sdma_clkstctrl: HW_AUTO + MmioWrite32 (0x4A009400, 0x3); //l4per: HW_AUTO + MmioWrite32 (0x4A009300, 0x3); //l3init: HW_AUTO + MmioWrite32 (0x4A008B00, 0x3); //memif: HW_AUTO + MmioWrite32 (0x4A008D00, 0x3); //l4cfg: HW_AUTO + MmioWrite32 (0x4A009000, 0x0); //cm_cam_clkstctrl: NO_SLEEP +} diff --git a/PandaBoardPkg/Library/PandaBoardLib/PadConfiguration.c b/PandaBoardPkg/Library/PandaBoardLib/PadConfiguration.c new file mode 100644 index 000000000..41dae5b4e --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PadConfiguration.c @@ -0,0 +1,343 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Omap4430/Omap4430.h> +#include <PandaBoard.h> + +PAD_CONFIGURATION PadConfigurationTableSharedCore[] = { + {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ + {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ + {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ + {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ + {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ + {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ + {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ + {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ + {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ + {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ + {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ + {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ + {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)}, /* uart3_tx */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ + {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ + {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ + {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ + {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ + {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182: BOARD_ID0 */ + {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ + {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ + {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ + {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ + {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ + {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ + {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ + {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ + {GPMC_A16, (M3)}, /* gpio_40 */ + {GPMC_A17, (PTD | M3)}, /* gpio_41 */ + {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ + {GPMC_A22, (M3)}, /* gpio_46 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48: BOARD_ID1 (Panda ES only) */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ + {GPMC_NCS0, (M3)}, /* gpio_50 */ + {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ + {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ + {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ + {GPMC_NWP, (M3)}, /* gpio_54 */ + {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ + {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101: BOARD_ID1 (Panda only) */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ + {HDMI_HPD, (M0)}, /* hdmi_hpd */ + {HDMI_CEC, (M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ + {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ + {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ + {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ + {UART2_RTS, (M7)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ + {UART2_TX, (M7)}, /* uart2_tx */ + {HDQ_SIO, (M3)}, /* gpio_127 */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ + {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ + {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ + {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3: BOARD_ID2 (gpio_171) */ + {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 | DIS)}, /* kpd_row1: BOARD_ID4 (gpio_2) */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 | DIS)}, /* kpd_row2: BOARD_ID3 (gpio_3) */ + {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ + {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ + {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ + {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ + {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ + {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ + {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ + {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ + {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ + {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ + {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ + {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ + {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ + {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ + {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ + {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ + {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ + {DPM_EMU16, (M3)}, /* gpio_27 */ + {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ + {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ + {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ +}; + +PAD_CONFIGURATION PadConfigurationTableSharedWkup[] = { + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ + {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +}; + +PAD_CONFIGURATION PadConfigurationTable4430Core[] = { + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ +}; + +PAD_CONFIGURATION PadConfigurationTable4430Wkup[] = { + {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ +}; + +PAD_CONFIGURATION PadConfigurationTable4460Core[] = { + {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ +}; + +PAD_CONFIGURATION PadConfigurationTable4460Wkup[] = { + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ +}; + +VOID +PadConfiguration ( + PANDABOARD_REVISION BoardRevision + ) +{ + UINTN Index; + UINTN NumPinsToConfigure; + + // Calculate number of pins for core domain + NumPinsToConfigure = sizeof(PadConfigurationTableSharedCore) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_CORE_BASE+PadConfigurationTableSharedCore[Index].Off), + PadConfigurationTableSharedCore[Index].Val); + } + + // Calculate number of pins for wkup domain + NumPinsToConfigure = sizeof(PadConfigurationTableSharedWkup) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_WKUP_BASE+PadConfigurationTableSharedWkup[Index].Off), + PadConfigurationTableSharedWkup[Index].Val); + } + + // If PandaBoard-ES + if( BoardRevision == PANDABOARD_REVISION_PANDAES ) { + // Calculate number of pins for core domain + NumPinsToConfigure = sizeof(PadConfigurationTable4460Core) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_CORE_BASE+PadConfigurationTable4460Core[Index].Off), + PadConfigurationTable4460Core[Index].Val); + } + + // Calculate number of pins for wkup domain + NumPinsToConfigure = sizeof(PadConfigurationTable4460Wkup) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_WKUP_BASE+PadConfigurationTable4460Wkup[Index].Off), + PadConfigurationTable4460Wkup[Index].Val); + } + } + else { + // Calculate number of pins for core domain + NumPinsToConfigure = sizeof(PadConfigurationTable4430Core) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_CORE_BASE+PadConfigurationTable4430Core[Index].Off), + PadConfigurationTable4430Core[Index].Val); + } + + // Calculate number of pins for wkup domain + NumPinsToConfigure = sizeof(PadConfigurationTable4430Wkup) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_WKUP_BASE+PadConfigurationTable4430Wkup[Index].Off), + PadConfigurationTable4430Wkup[Index].Val); + } + } + + // EMIF pads + MmioWrite32 (0x4A100638, 0x7c7c7c7c); + MmioWrite32 (0x4A10063C, 0x7c7c7c7c); + MmioWrite32 (0x4A100640, 0x7C787C00); + MmioWrite32 (0x4A100644, 0xA0888C0F); + + MmioWrite32 (0x4A100648, 0x7C7C7C7C); + MmioWrite32 (0x4A10064C, 0x7C7C7C7C); + MmioWrite32 (0x4A100650, 0x7C787C00); + MmioWrite32 (0x4A100654, 0xA0888C0F); + +} diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoard.c b/PandaBoardPkg/Library/PandaBoardLib/PandaBoard.c new file mode 100644 index 000000000..cec10b1a3 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoard.c @@ -0,0 +1,200 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include <Omap4430/Omap4430.h> +#include <PandaBoard.h> + +ARM_CORE_INFO mVersatileExpressMpCoreInfoPandaBoard[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (UINT64)0 + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (UINT64)0 + } +}; + +VOID +PadConfiguration ( + PANDABOARD_REVISION BoardRevision + ); + +VOID +ClockInit ( + PANDABOARD_REVISION BoardRevision + ); + +/** + Detect board revision + + @return Board revision +**/ +PANDABOARD_REVISION +PandaBoardGetBoardRevision ( + VOID + ) +{ + UINT32 Revision; + + // If Chip Id code matches 4460 processor + if( ((MmioRead32(CONTROL_CORE_ID_CODE)>>16)&0xFFF) == 0xb94 ) { + Revision = PANDABOARD_REVISION_PANDAES; + } + else { + // Assume 4430 + Revision = PANDABOARD_REVISION_PANDA; + } + + return Revision; +} + +/** + Remap the memory at 0x0 + + Some platform requires or gives the ability to remap the memory at the address 0x0. + This function can do nothing if this feature is not relevant to your platform. + +**/ +VOID +ArmPlatformBootRemapping ( + VOID + ) +{ + // Do nothing for the PandaBoard +} + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Early board setup + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + PANDABOARD_REVISION Revision; + + // Get chip version + Revision = PandaBoardGetBoardRevision(); + + // Set up Pin muxing. + PadConfiguration (Revision); + + // Set up system clocking + ClockInit (Revision); + + // Make sure GPMC region region 0 is disabled + // Not doing so makes gpmc_init hang early in kernel init + MmioAnd32 (GPMC_CONFIG7_0, ~CSVALID); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Nothing done here, handled by the ROM Configuration Header + +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mVersatileExpressMpCoreInfoPandaBoard) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mVersatileExpressMpCoreInfoPandaBoard; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ +} + diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.S b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.S new file mode 100644 index 000000000..49fcf533a --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.S @@ -0,0 +1,119 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <PandaBoard.h> +#include <AutoGen.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPrePiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) + +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) + +/** + ArmPlatformPrePiBootAction + +**/ +ASM_PFX(ArmPlatformPrePiBootAction): + //relocate the relocator + sub r12,r12 + orr r12,r12,#0x80000000 + mov r3,r12 // relocator target address (0x80000000) + ldr r0, =relocator_start // relocator code start addr + ldr r1, =relocator_end // relocator end addr + sub r1,r1,r0 // compute relocator code size + lsr r1,r1,#0x2 // size in words +reloc_loop_reloc: // copy relocator + ldm r0!,{r2} + stm r3!,{r2} + subs r1,r1,#0x1 + bne reloc_loop_reloc + + // get chip id code + ldr r2,=0x4a002206 // control module id code address + ldrh r2,[r2] // get higher order 16b + lsl r2,r2,#0x14 + ldr r1,=0xb9400000 // compare with 4460 id + cmp r1,r2 // Z bit set if 4460 + + // update dmm conf + mov r0,#0x4e + lsl r0,r0,#0x18 // load DMM LISA base address + ldr r2,=0x482af000 // load MA LISA base address + ldr r1,[r0,#0x40] // get DMM LISA section 0 + str r1,[r0,#0x4c] // update DMM LISA section 3 + streq r1,[r2,#0x4c] // update MA LISA section 3 (when Z=1: 4460 only) + ldr r1,=0xff020100 // prepare LISA section 0 + str r1,[r0,#0x40] // update DMM LISA section 0 + streq r1,[r2,#0x40] // update MA LISA section 0 (when Z set: 4460 only) + bx r12 // jump to relocator + +relocator_start: + // update emif conf. + sub r2,r0,#0x1000000 + sub r1,r2,#0x1000000 + mov r0,#0x10 + str r0,[r1,#0xc] + str r0,[r2,#0xc] + ldr r0,[r1,#0x8] + orr r0,r0,#0x8 + str r0,[r1,#0x8] + str r0,[r2,#0x8] + + // copy + add r1,r12,#0x8000 + add r0,r1,#0x8000 + mov r10,#0x1 + lsl r11,r10,#0x5 +reloc_loop_1M: + lsl r10,r10,#0xA +reloc_loop_4K: + ldm r0!,{r2-r9} + stm r1!,{r2-r9} + subs r10,r10,#1 + bne reloc_loop_4K + add r0,r0,#0x8000 + subs r11,r11,#1 + add r10,r10,#0x1 + bne reloc_loop_1M + bx lr +relocator_end: + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformGetCorePosition): + bx lr + +ASM_PFX(ArmPlatformIsPrimaryCore): + #Bits 8 through 11 are CPU ID + ldr r1, =0xf00 + and r0, r0, r1 + #id for core0 should be 0 + ldr r1, =0x0 + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + mov pc, lr + +ASM_PFX(ArmPlatformPeiBootAction): + mov pc, lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.asm b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.asm new file mode 100755 index 000000000..f5fb53ab5 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.asm @@ -0,0 +1,58 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <PandaBoard.h> +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformIsBootMemoryInitialized + EXPORT ArmPlatformInitializeBootMemory + + PRESERVE8 + AREA PandaBoardHelper, CODE, READONLY + +/** + Called at the early stage of the Boot phase to know if the memory has already been initialized + + Running the code from the reset vector does not mean we start from cold boot. In some case, we + can go through this code with the memory already initialized. + Because this function is called at the early stage, the implementation must not use the stack. + Its implementation must probably done in assembly to ensure this requirement. + + @return Return a non zero value if initialized + +**/ +ArmPlatformIsBootMemoryInitialized + // The system memory is initialized by the PandaBoard firmware + mov r0, #1 + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformInitializeBootMemory + // We must need to go into this function + bx lr + + END diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf new file mode 100755 index 000000000..3028cba23 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf @@ -0,0 +1,55 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardLib + FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + PandaBoardPkg/PandaBoardPkg.dec + +[LibraryClasses] + IoLib + ArmLib +# OmapLib + MemoryAllocationLib + +[Sources.common] + PandaBoard.c + PandaBoardMem.c + PandaBoardHelper.asm | RVCT + PandaBoardHelper.S | GCC + PadConfiguration.c + Clock.c + +[Protocols] + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardMem.c b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardMem.c new file mode 100755 index 000000000..334cb094e --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardMem.c @@ -0,0 +1,102 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> + +#include <PandaBoard.h> + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase = PcdGet32(PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet32(PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet32(PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SOC Registers. L3 interconnects + VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + VirtualMemoryTable[Index].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH; + VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L3_ATTRIBUTES; + + // SOC Registers. L4 interconnects + VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + VirtualMemoryTable[Index].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH; + VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L4_ATTRIBUTES; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +} + +/** + Return the EFI Memory Map of your platform + + This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource + Descriptor HOBs used by DXE core. + + @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an + EFI Memory region. This array must be ended by a zero-filled entry + +**/ +EFI_STATUS +ArmPlatformGetAdditionalSystemMemory ( + OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.c b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 000000000..fa0877a5e --- /dev/null +++ b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,165 @@ +/** @file + Do a generic Cold Reset for PandaBoard specific Warm reset + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include <Uefi.h> + +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Omap4430/Omap4430.h> + + +VOID +ShutdownEfi ( + VOID + ) +{ + EFI_STATUS Status; + UINTN MemoryMapSize; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + UINTN MapKey; + UINTN DescriptorSize; + UINTN DescriptorVersion; + UINTN Pages; + + MemoryMap = NULL; + MemoryMapSize = 0; + do { + Status = gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + if (Status == EFI_BUFFER_TOO_SMALL) { + + Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1; + MemoryMap = AllocatePages (Pages); + + // + // Get System MemoryMap + // + Status = gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + // Don't do anything between the GetMemoryMap() and ExitBootServices() + if (!EFI_ERROR (Status)) { + Status = gBS->ExitBootServices (gImageHandle, MapKey); + if (EFI_ERROR (Status)) { + FreePages (MemoryMap, Pages); + MemoryMap = NULL; + MemoryMapSize = 0; + } + } + } + } while (EFI_ERROR (Status)); + + //Clean and invalidate caches. + WriteBackInvalidateDataCache(); + InvalidateInstructionCache(); + + //Turning off Caches and MMU + ArmDisableDataCache (); + ArmDisableInstructionCache (); + ArmDisableMmu (); +} + +typedef +VOID +(EFIAPI *CALL_STUB)( + VOID +); + + +/** + Resets the entire platform. + + @param ResetType The type of reset to perform. + @param ResetStatus The status code for the reset. + @param DataSize The size, in bytes, of WatchdogData. + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or + EfiResetShutdown the data buffer starts with a Null-terminated + Unicode string, optionally followed by additional binary data. + +**/ +EFI_STATUS +EFIAPI +LibResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN CHAR16 *ResetData OPTIONAL + ) +{ + CALL_STUB StartOfFv; + + if (ResetData != NULL) { + DEBUG((EFI_D_ERROR, "%s", ResetData)); + } + + ShutdownEfi (); + + switch (ResetType) { + case EfiResetWarm: + //Perform warm reset of the system by jumping to the begining of the FV + StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFvBaseAddress); + StartOfFv (); + break; + case EfiResetCold: + case EfiResetShutdown: + default: + //Perform cold reset of the system. + MmioOr32 (PRM_RSTCTRL, PRM_RSTCTRL_RST_GLOBAL_COLD_SW_VAL); + while ((MmioRead32(PRM_RSTST) & PRM_RSTST_GLOBAL_COLD_RST_MASK) != 0x1); + break; + } + + // If the reset didn't work, return an error. + ASSERT (FALSE); + return EFI_DEVICE_ERROR; +} + + + +/** + Initialize any infrastructure required for LibResetSystem () to function. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +LibInitializeResetSystem ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} + diff --git a/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 000000000..31f7e094c --- /dev/null +++ b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,49 @@ +#/** @file +# Reset System lib to make it easy to port new platforms +# +# Copyright (c) 2008, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardResetSystemLib + FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = EfiResetSystemLib + + +[Sources.common] + ResetSystemLib.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[Pcd.common] + gArmTokenSpaceGuid.PcdCpuResetAddress + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress + +[LibraryClasses] + DebugLib + ArmLib + CacheMaintenanceLib + MemoryAllocationLib + UefiRuntimeServicesTableLib + TimerLib + UefiLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress diff --git a/PandaBoardPkg/PandaBoardPkg.dec b/PandaBoardPkg/PandaBoardPkg.dec new file mode 100644 index 000000000..595bcc68d --- /dev/null +++ b/PandaBoardPkg/PandaBoardPkg.dec @@ -0,0 +1,36 @@ +#/** @file +# Panda board package. +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = PandaBoardPkg + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gPandaBoardTokenSpaceGuid = { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } } + diff --git a/PandaBoardPkg/PandaBoardPkg.dsc b/PandaBoardPkg/PandaBoardPkg.dsc new file mode 100644 index 000000000..21a75cfb8 --- /dev/null +++ b/PandaBoardPkg/PandaBoardPkg.dsc @@ -0,0 +1,496 @@ +#/** @file +# Panda board package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = PandaBoardPkg + PLATFORM_GUID = 49aefbb9-652c-4396-ac95-b9363cffce92 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/PandaBoard + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = PandaBoardPkg/PandaBoardPkg.fdf + + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf + + EfiResetSystemLib|PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf + + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + + EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf + + + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scipts accessing system memory. + # +# PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf +# PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + + + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + + SerialPortLib|Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf + SerialPortExtLib|EmbeddedPkg/Library/TemplateSerialPortExtLib/TemplateSerialPortExtLib.inf + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + RealTimeClockLib|Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + +# +# Assume everything is fixed at build +# + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf + + + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + TimerLib|Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf + OmapLib|Omap44xxPkg/Library/OmapLib/OmapLib.inf + OmapDmaLib|Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf + EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf + DebugAgentTimerLib|Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf + + GdbSerialLib|Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf + ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + + # Temp work around for Movt relocation issue. + #PeCoffLib|ArmPkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + + # 1/123 faster than Stm or Vstm version + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + +[LibraryClasses.common.PEI_CORE] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf + + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf + + +[LibraryClasses.ARM] + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + +[BuildOptions] + XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 + + GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a + + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # + # Control what commands are supported from the UI + # Turn these on and off to add features or save size + # + gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE + + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Panda Board" + + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"PandaEdk2" + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + +# DEBUG_ASSERT_ENABLED 0x01 +# DEBUG_PRINT_ENABLED 0x02 +# DEBUG_CODE_ENABLED 0x04 +# CLEAR_MEMORY_ENABLED 0x08 +# ASSERT_BREAKPOINT_ENABLED 0x10 +# ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + +# DEBUG_INIT 0x00000001 // Initialization +# DEBUG_WARN 0x00000002 // Warnings +# DEBUG_LOAD 0x00000004 // Load events +# DEBUG_FS 0x00000008 // EFI File system +# DEBUG_POOL 0x00000010 // Alloc & Free's +# DEBUG_PAGE 0x00000020 // Alloc & Free's +# DEBUG_INFO 0x00000040 // Verbose +# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers +# DEBUG_VARIABLE 0x00000100 // Variable +# DEBUG_BM 0x00000400 // Boot Manager +# DEBUG_BLKIO 0x00001000 // BlkIo Driver +# DEBUG_NET 0x00004000 // SNI Driver +# DEBUG_UNDI 0x00010000 // UNDI Driver +# DEBUG_LOADFILE 0x00020000 // UNDI Driver +# DEBUG_EVENT 0x00080000 // Event messages +# DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + +# +# Optional feature to help prevent EFI memory map fragments +# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob +# Values are in EFI Pages (4K). DXE Core will make sure that +# at least this much of each type of memory can be allocated +# from a single memory range. This way you only end up with +# maximum of two fragements for each type in the memory map +# (the memory used, and the free memory that was prereserved +# but not used). +# + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + +# +# Panda board Specific PCDs +# + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack + + # ARM Gic base addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x48241000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x48240100 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x08000000 + + # Size of the region used by UEFI in permanent memory (Reserved 16MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x01000000 + + # Size of the region reserved for fixed address allocations (Reserved 32MB) + gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x02000000 + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000 + gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000 + + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|26 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|38400000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SD" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/board.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyO2,115200n8 root=/dev/mmcblk0p2 rootwait ro fixrtc nocompcache vram=48M omapfb.vram=0:24M" + + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(E68088EF-D1A4-4336-C1DB-4D3A204730A6)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM OS Loader + # + # PandaBoard machine type required for ARM Linux: + gArmTokenSpaceGuid.PcdArmMachineType|2791 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + ArmPlatformPkg/PrePi/PeiMPCore.inf + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf +# NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + NULL|EmbeddedPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf + } + + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +# +# This version uses semi-hosting console +# EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf { +# <LibraryClasses> +# SerialPortLib|ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf +# } + + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # USB + # + Omap44xxPkg/PciEmulation/PciEmulation.inf + + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf { + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800fffff + } + + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # MMC/SD + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf + + # + # I2C + # + Omap44xxPkg/SmbusDxe/Smbus.inf + + # + # SoC Drivers + # + Omap44xxPkg/Gpio/Gpio.inf + Omap44xxPkg/TimerDxe/TimerDxe.inf + Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf + + # + # Power IC + # + Omap44xxPkg/TWL6030Dxe/TWL6030.inf + + # + # Application + # + EmbeddedPkg/Ebl/Ebl.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + ArmPlatformPkg/Bds/Bds.inf + + # + # Example Application + # + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + diff --git a/PandaBoardPkg/PandaBoardPkg.fdf b/PandaBoardPkg/PandaBoardPkg.fdf new file mode 100644 index 000000000..88881084f --- /dev/null +++ b/PandaBoardPkg/PandaBoardPkg.fdf @@ -0,0 +1,300 @@ +# FLASH layout file for Panda board. +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + + +[FD.PandaBoard_EFI] +BaseAddress = 0x80008000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device. +Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device +ErasePolarity = 1 +BlockSize = 0x1 +NumBlocks = 0x100000 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ +!if $(EDK2_SECOND_STAGE_BOOTOLADER) == 1 +0x00000000|0x00100000 +!else +# 512 bytes of configuration header & 8 bytes of image header +0x00000000|0x00000208 + +0x00000208|0x000FFDF8 +!endif +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x1 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # MMC/SD + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf + + # + # I2C + # + INF Omap44xxPkg/SmbusDxe/Smbus.inf + + # + # SoC Drivers + # + INF Omap44xxPkg/Gpio/Gpio.inf + INF Omap44xxPkg/TimerDxe/TimerDxe.inf + INF Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf + + # + # Power IC + # + INF Omap44xxPkg/TWL6030Dxe/TWL6030.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # USB Support (not supported currently) + # + + INF Omap44xxPkg/PciEmulation/PciEmulation.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellBinPkg/UefiShell/UefiShell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.S b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.S new file mode 100644 index 000000000..24714969c --- /dev/null +++ b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.S @@ -0,0 +1,85 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#include <AsmMacroIoLib.h> +#include <Library/PcdLib.h> + +.text +.align 3 + +.globl ASM_PFX(CEntryPoint) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +ASM_PFX(_ModuleEntryPoint): + + // TODO: Disable L2 cache (need handle PL310) +// mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register +// bic r0, r0, #0x00000002 // disable L2 cache +// mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register + + //Enable Strict alignment checking & Instruction cache + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + // Enable NEON register in case folks want to use them for optimizations (CopyMem) + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly + + + // Set CPU vectors to start of DRAM + LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base + mcr p15, 0, r0, c12, c0, 0 + isb // Sync changes to control registers + + // Fill vector table with branchs to current pc (jmp $) + ldr r1, ShouldNeverGetHere + movs r2, #0 +FillVectors: + str r1, [r0, r2] + adds r2, r2, #4 + cmp r2, #32 + bne FillVectors + + /* before we call C code, lets setup the stack pointer in internal RAM */ +stack_pointer_setup: + + // + // Set stack based on PCD values. Need to do it this way to make C code work + // when it runs from FLASH. + // + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */ + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */ + add r4, r2, r3 + + //Enter SVC mode and set up SVC stack pointer + mov r0,#0x13|0x80|0x40 + msr CPSR_c,r0 + mov r13,r4 + + // Call C entry point + LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) /* memory size arg1 */ + LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */ + blx ASM_PFX(CEntryPoint) /* Assume C code is thumb */ + +ShouldNeverGetHere: + /* _CEntryPoint should never return */ + b ShouldNeverGetHere + diff --git a/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.asm b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.asm new file mode 100644 index 000000000..81dfeda4a --- /dev/null +++ b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.asm @@ -0,0 +1,89 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ + +#include <AsmMacroIoLib.h> +#include <Library/PcdLib.h> +#include <AutoGen.h> + INCLUDE AsmMacroIoLib.inc + + IMPORT CEntryPoint + EXPORT _ModuleEntryPoint + + PRESERVE8 + AREA ModuleEntryPoint, CODE, READONLY + + +_ModuleEntryPoint + + // TODO: Disable L2 cache (need handle PL310) +// mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register +// bic r0, r0, #0x00000002 // disable L2 cache +// mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register + + //Enable Strict alignment checking & Instruction cache + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + // Enable NEON register in case folks want to use them for optimizations (CopyMem) + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + msr FPEXC,r0 + + // Set CPU vectors to start of DRAM + LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base + mcr p15, 0, r0, c12, c0, 0 + isb // Sync changes to control registers + + // Fill vector table with branchs to current pc (jmp $) + ldr r1, ShouldNeverGetHere + movs r2, #0 +FillVectors + str r1, [r0, r2] + adds r2, r2, #4 + cmp r2, #32 + bne FillVectors + + /* before we call C code, lets setup the stack pointer in internal RAM */ +stack_pointer_setup + + // + // Set stack based on PCD values. Need to do it this way to make C code work + // when it runs from FLASH. + // + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 + add r4, r2, r3 + + //Enter SVC mode and set up SVC stack pointer + mov r5,#0x13|0x80|0x40 + msr CPSR_c,r5 + mov r13,r4 + + // Call C entry point + LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 + LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0 + blx CEntryPoint // Assume C code is thumb + +ShouldNeverGetHere + /* _CEntryPoint should never return */ + b ShouldNeverGetHere + + END + diff --git a/PandaBoardPkg/Sec/Cache.c b/PandaBoardPkg/Sec/Cache.c new file mode 100644 index 000000000..8c85b898c --- /dev/null +++ b/PandaBoardPkg/Sec/Cache.c @@ -0,0 +1,79 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> + +#include <Library/ArmLib.h> +#include <Library/PrePiLib.h> +#include <Library/PcdLib.h> + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +// SoC registers. L3 interconnects +#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000 +#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + +// SoC registers. L4 interconnects +#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000 +#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + +VOID +InitCache ( + IN UINT32 MemoryBase, + IN UINT32 MemoryLength + ) +{ + UINT32 CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5]; + VOID *TranslationTableBase; + UINTN TranslationTableSize; + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // DDR + MemoryTable[0].PhysicalBase = MemoryBase; + MemoryTable[0].VirtualBase = MemoryBase; + MemoryTable[0].Length = MemoryLength; + MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + + // SOC Registers. L3 interconnects + MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH; + MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES; + + // SOC Registers. L4 interconnects + MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH; + MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES; + + // End of Table + MemoryTable[3].PhysicalBase = 0; + MemoryTable[3].VirtualBase = 0; + MemoryTable[3].Length = 0; + MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); + + BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData); +} diff --git a/PandaBoardPkg/Sec/Clock.c b/PandaBoardPkg/Sec/Clock.c new file mode 100644 index 000000000..9d5a73a51 --- /dev/null +++ b/PandaBoardPkg/Sec/Clock.c @@ -0,0 +1,44 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Omap4430/Omap4430.h> +#include <Omap4430/Omap4430Rom.h> + +VOID +ClockInit ( + VOID + ) +{ + // TODO: clocks configuration code clean up + + // CORE, PER DPLLs are configured part of Configuration header which OMAP4 ROM parses. + + // Turn on functional & interface clocks to MMC1 and I2C1 modules. + MmioOr32(0x4a009328, 0x03070002); + + //Enable DMTIMER3 with SYS_CLK source + MmioOr32(0x4A009440, 0x2); + + //Enable DMTIMER4 with SYS_CLK source + MmioOr32(0x4A009448, 0x2); + + // Enable UART3 clocks + RomEnableClocks (2, 2); + + // Enable watchdog interface clocks + RomEnableClocks (6, 1); + +} diff --git a/PandaBoardPkg/Sec/LzmaDecompress.h b/PandaBoardPkg/Sec/LzmaDecompress.h new file mode 100644 index 000000000..2216cac86 --- /dev/null +++ b/PandaBoardPkg/Sec/LzmaDecompress.h @@ -0,0 +1,103 @@ +/** @file + LZMA Decompress Library header file + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __LZMA_DECOMPRESS_H___ +#define __LZMA_DECOMPRESS_H___ + +/** + Examines a GUIDed section and returns the size of the decoded buffer and the + size of an scratch buffer required to actually decode the data in a GUIDed section. + + Examines a GUIDed section specified by InputSection. + If GUID for InputSection does not match the GUID that this handler supports, + then RETURN_UNSUPPORTED is returned. + If the required information can not be retrieved from InputSection, + then RETURN_INVALID_PARAMETER is returned. + If the GUID of InputSection does match the GUID that this handler supports, + then the size required to hold the decoded buffer is returned in OututBufferSize, + the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field + from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute. + + If InputSection is NULL, then ASSERT(). + If OutputBufferSize is NULL, then ASSERT(). + If ScratchBufferSize is NULL, then ASSERT(). + If SectionAttribute is NULL, then ASSERT(). + + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required + if the buffer specified by InputSection were decoded. + @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space + if the buffer specified by InputSection were decoded. + @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes + field of EFI_GUID_DEFINED_SECTION in the PI Specification. + + @retval RETURN_SUCCESS The information about InputSection was returned. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection. + +**/ +RETURN_STATUS +EFIAPI +LzmaGuidedSectionGetInfo ( + IN CONST VOID *InputSection, + OUT UINT32 *OutputBufferSize, + OUT UINT32 *ScratchBufferSize, + OUT UINT16 *SectionAttribute + ); + +/** + Decompress a LZAM compressed GUIDed section into a caller allocated output buffer. + + Decodes the GUIDed section specified by InputSection. + If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned. + If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned. + If the GUID of InputSection does match the GUID that this handler supports, then InputSection + is decoded into the buffer specified by OutputBuffer and the authentication status of this + decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the + data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise, + the decoded data will be placed in caller allocated buffer specified by OutputBuffer. + + If InputSection is NULL, then ASSERT(). + If OutputBuffer is NULL, then ASSERT(). + If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT(). + If AuthenticationStatus is NULL, then ASSERT(). + + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation. + @param[out] ScratchBuffer A caller allocated buffer that may be required by this function + as a scratch buffer to perform the decode operation. + @param[out] AuthenticationStatus + A pointer to the authentication status of the decoded output buffer. + See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI + section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must + never be set by this handler. + + @retval RETURN_SUCCESS The buffer specified by InputSection was decoded. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded. + +**/ +RETURN_STATUS +EFIAPI +LzmaGuidedSectionExtraction ( + IN CONST VOID *InputSection, + OUT VOID **OutputBuffer, + OUT VOID *ScratchBuffer, OPTIONAL + OUT UINT32 *AuthenticationStatus + ); + +#endif // __LZMADECOMPRESS_H__ + diff --git a/PandaBoardPkg/Sec/PadConfiguration.c b/PandaBoardPkg/Sec/PadConfiguration.c new file mode 100644 index 000000000..796571192 --- /dev/null +++ b/PandaBoardPkg/Sec/PadConfiguration.c @@ -0,0 +1,31 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Omap4430/Omap4430.h> +#include <Omap4430/Omap4430Rom.h> + +VOID +PadConfiguration ( + VOID + ) +{ + // TODO: pad configuration + + // Configure UART3 pads + RomCtrlConfigurePads (2, 2); + +} diff --git a/PandaBoardPkg/Sec/Sec.c b/PandaBoardPkg/Sec/Sec.c new file mode 100644 index 000000000..4046c9b47 --- /dev/null +++ b/PandaBoardPkg/Sec/Sec.c @@ -0,0 +1,204 @@ +/** @file + C Entry point for the SEC. First C code after the reset vector. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> + +#include <Library/DebugLib.h> +#include <Library/PrePiLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Library/ArmLib.h> +#include <Library/PeCoffGetEntryPointLib.h> +#include <Library/DebugAgentLib.h> +#include <Ppi/GuidedSectionExtraction.h> +#include <Guid/LzmaDecompress.h> +#include <Omap4430/Omap4430.h> +#include <Omap4430/Omap4430Rom.h> +#include "LzmaDecompress.h" + +VOID +PadConfiguration ( + VOID + ); + +VOID +ClockInit ( + VOID + ); + +VOID +TimerInit ( + VOID + ) +{ + UINTN Timer = FixedPcdGet32(PcdOmap44xxFreeTimer); + UINT32 TimerBaseAddress = TimerBase(Timer); + + // Un-register USB IRQs + RomIrqUnRegister (92); + RomIrqUnRegister (93); + + // Register Timer3 Irq + RomIrqRegister (0x55aa55aa, 39, 0); + + // Register Timer4 Irq + RomIrqRegister (0x55aa55aa, 40, 0); + + // Set count & reload registers + MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000); + MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000); + + // Disable interrupts + MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE); + + // Start Timer + MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + +} + +VOID +UartInit ( + VOID + ) +{ + UINTN Uart = FixedPcdGet32(PcdOmap44xxConsoleUart); + UINT32 UartBaseAddress = UartBase(Uart); + + // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers. + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE); + + // Put device in configuration mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE); + + // Programmable divisor N = 48Mhz/16/115200 = 26 + MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor + MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor + + // Enter into UART operational mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8); + + // Force DTR and RTS output to active + MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE); + + // Clear & enable fifos + MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); + + // Restore MODE_SELECT + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X); +} + +VOID +GpmcConfiguration ( + VOID + ) +{ + // Make sure all chip selects are disabled + // Kernel makes a wrong assumption about CS0 being already configured by ROM + MmioWrite32 (0x50000078, 0xF00); + +} + +VOID +InitCache ( + IN UINT32 MemoryBase, + IN UINT32 MemoryLength + ); + +EFI_STATUS +EFIAPI +ExtractGuidedSectionLibConstructor ( + VOID + ); + +EFI_STATUS +EFIAPI +LzmaDecompressLibConstructor ( + VOID + ); + +UINTN mGlobalVariableBase = 0; + +VOID +CEntryPoint ( + IN VOID *MemoryBase, + IN UINTN MemorySize, + IN VOID *StackBase, + IN UINTN StackSize + ) +{ + VOID *HobBase; + + // Set up system clocking + ClockInit (); + + // Disable watchdog timer + RomWdtimerDisable (); + + // Build a basic HOB list + HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize)); + CreateHobList (MemoryBase, MemorySize, HobBase, StackBase); + + // Set up Pin muxing + PadConfiguration (); + + // Setup gpmc + GpmcConfiguration (); + + // Start up a free running timer so that the timer lib will work + TimerInit (); + + // Enable program flow prediction, if supported. + ArmEnableBranchPrediction (); + + // Initialize CPU cache + InitCache ((UINT32)MemoryBase, (UINT32)MemorySize); + + // Add memory allocation hob for relocated FD + BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData); + + // Add the FVs to the hob list + BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize)); + + // Start talking + UartInit (); + + InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + + DEBUG ((EFI_D_ERROR, "UART Enabled\n")); + + // SEC phase needs to run library constructors by hand. + ExtractGuidedSectionLibConstructor (); + LzmaDecompressLibConstructor (); + + // Build HOBs to pass up our version of stuff the DXE Core needs to save space + BuildPeCoffLoaderHob (); + BuildExtractSectionHob ( + &gLzmaCustomDecompressGuid, + LzmaGuidedSectionGetInfo, + LzmaGuidedSectionExtraction + ); + + // Assume the FV that contains the SEC (our code) also contains a compressed FV. + DecompressFirstFv (); + + // Load the DXE Core and transfer control to it + LoadDxeCoreFromFv (NULL, 0); + + // DXE Core should always load and never return + ASSERT (FALSE); +} + diff --git a/PandaBoardPkg/Sec/Sec.inf b/PandaBoardPkg/Sec/Sec.inf new file mode 100644 index 000000000..ec8834e47 --- /dev/null +++ b/PandaBoardPkg/Sec/Sec.inf @@ -0,0 +1,73 @@ + +#/** @file +# SEC - Reset vector code that jumps to C and loads DXE core +# +# Copyright (c) 2008, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardSec + FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + + +[Sources.ARM] + Arm/ModuleEntryPoint.S | GCC + Arm/ModuleEntryPoint.asm | RVCT + +[Sources.ARM] + Sec.c + Cache.c + PadConfiguration.c + Clock.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + ArmLib + IoLib + ExtractGuidedSectionLib + LzmaDecompressLib + OmapLib + PeCoffGetEntryPointLib + DebugAgentLib + MemoryAllocationLib + PrePiHobListPointerLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize + gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase + gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase + gEmbeddedTokenSpaceGuid.PcdMemoryBase + gEmbeddedTokenSpaceGuid.PcdMemorySize + + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress + diff --git a/PandaBoardPkg/Tools/GNUmakefile b/PandaBoardPkg/Tools/GNUmakefile new file mode 100644 index 000000000..b86a1d6bf --- /dev/null +++ b/PandaBoardPkg/Tools/GNUmakefile @@ -0,0 +1,44 @@ +# +# Makefile +# +# Copyright(c) 2010 Texas Instruments. All rights reserved. +# +# Texas Instruments, <www.ti.com> +# Bastien Allibert <b-allibert@ti.com> +# Olivier Deprez <o-deprez@ti.com> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name Texas Instruments nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +CC = gcc +CFLAGS = -g + +chtool: chtool.c + $(CC) $(CCFLAGS) $(LDFLAGS) -o chtool chtool.c + +clean: + rm -f chtool diff --git a/PandaBoardPkg/Tools/ch_omap4.h b/PandaBoardPkg/Tools/ch_omap4.h new file mode 100644 index 000000000..2a74abe41 --- /dev/null +++ b/PandaBoardPkg/Tools/ch_omap4.h @@ -0,0 +1,173 @@ +/* + 2 * ch_omap4.h + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +#ifndef _CH_OMAP4_H +#define _CH_OMAP4_H + +/* Define here all the data fields for each item */ +CH_Field OMAP4_CHSETTINGS_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C1}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x04,"Flags","ClockSettings",0}, + {0x000C,0x04,"CM_CLKSEL_CORE","ClockSettings",0}, + {0x0010,0x04,"CM_DLL_CTRL","ClockSettings",0}, + {0x0014,0x04,"CM_AUTOIDLE_DPLL_MPU","ClockSettings",0}, + {0x0018,0x04,"CM_CLKSEL_DPLL_MPU","ClockSettings",0}, + {0x001C,0x04,"CM_DIV_M2_DPLL_MPU","ClockSettings",0}, + {0x0020,0x04,"CM_AUTOIDLE_DPLL_CORE","ClockSettings",0}, + {0x0024,0x04,"CM_CLKSEL_DPLL_CORE","ClockSettings",0}, + {0x0028,0x04,"CM_DIV_M2_DPLL_CORE","ClockSettings",0}, + {0x002C,0x04,"CM_DIV_M3_DPLL_CORE","ClockSettings",0}, + {0x0030,0x04,"CM_DIV_M4_DPLL_CORE","ClockSettings",0}, + {0x0034,0x04,"CM_DIV_M5_DPLL_CORE","ClockSettings",0}, + {0x0038,0x04,"CM_DIV_M6_DPLL_CORE","ClockSettings",0}, + {0x003C,0x04,"CM_DIV_M7_DPLL_CORE","ClockSettings",0}, + {0x0040,0x04,"CM_AUTOIDLE_DPLL_PER","ClockSettings",0}, + {0x0044,0x04,"CM_CLKSEL_DPLL_PER","ClockSettings",0}, + {0x0048,0x04,"CM_DIV_M2_DPLL_PER","ClockSettings",0}, + {0x004C,0x04,"CM_DIV_M3_DPLL_PER","ClockSettings",0}, + {0x0050,0x04,"CM_DIV_M4_DPLL_PER","ClockSettings",0}, + {0x0054,0x04,"CM_DIV_M5_DPLL_PER","ClockSettings",0}, + {0x0058,0x04,"CM_DIV_M6_DPLL_PER","ClockSettings",0}, + {0x005C,0x04,"CM_DIV_M7_DPLL_PER","ClockSettings",0}, + {0x0060,0x04,"CM_AUTOIDLE_DPLL_USB","ClockSettings",0}, + {0x0064,0x04,"CM_CLKSEL_DPLL_USB","ClockSettings",0}, + {0x0068,0x04,"CM_DIV_M2_DPLL_USB","ClockSettings",0} +}; +CH_Field OMAP4_CHRAM_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C2}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x04,"SdramConfigEMIF1","SDRAM Configuration Register",0}, + {0x000C,0x04,"SdramRefreshEMIF1","SDRAM Refresh Control Register",0}, + {0x0010,0x04,"SdramTim1EMIF1","SDRAM Timing 1 Register",0}, + {0x0014,0x04,"SdramTim2EMIF1","SDRAM Timing 2 Register",0}, + {0x0018,0x04,"SdramTim3EMIF1","SDRAM Timing 3 Register",0}, + {0x001C,0x04,"PwrMgtCtrlEMIF1","Power mgt control Register",0}, + {0x0020,0x04,"DdrPhyCtrl1EMIF1","DDR PHY Control 1 Register",0}, + {0x0024,0x04,"DdrPhyCtrl2EMIF1","DDR PHY Control 2 Register",0}, + {0x0028,0x01,"ModeReg1EMIF1","Mode register MR1",0}, + {0x0029,0x01,"ModeReg2EMIF1","Mode register MR2",0}, + {0x002A,0x01,"ModeReg3EMIF1","Mode register MR3",0}, + {0x002B,0x01,"Reserved","Reserved",0}, + + {0x002C,0x04,"SdramConfigEMIF2","SDRAM Configuration Register",0}, + {0x0030,0x04,"SdramRefreshEMIF2","SDRAM Refresh Control Register",0}, + {0x0034,0x04,"SdramTim1EMIF2","SDRAM Timing 1 Register",0}, + {0x0038,0x04,"SdramTim2EMIF2","SDRAM Timing 2 Register",0}, + {0x003C,0x04,"SdramTim3EMIF2","SDRAM Timing 3 Register",0}, + {0x0040,0x04,"PwrMgtCtrlEMIF2","Power mgt control Register",0}, + {0x0044,0x04,"DdrPhyCtrl1EMIF2","DDR PHY Control 1 Register",0}, + {0x0048,0x04,"DdrPhyCtrl2EMIF2","DDR PHY Control 2 Register",0}, + {0x004C,0x01,"ModeReg1EMIF2","Mode register MR1",0}, + {0x004D,0x01,"ModeReg2EMIF2","Mode register MR2",0}, + {0x004E,0x01,"ModeReg3EMIF2","Mode register MR3",0}, + {0x004F,0x01,"Reserved","Reserved",0}, + + {0x0050,0x04,"DMMLisaMap0","DMM LISA section 0 mapping",0}, + {0x0054,0x04,"Flags","Configure the chip selects",0} +}; +CH_Field OMAP4_CHFLASH_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C3}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x02,"GPMC_SYSCONFIG_LSB","Register Value",0}, + {0x000A,0x02,"GPMC_IRQENABLE_LSB","Register Value",0}, + {0x000C,0x02,"GPMC_TIMEOUT_CONTROL_LSB","Register Value",0}, + + {0x000E,0x02,"GPMC_CONFIG_LSB","Register Value",0}, + {0x0010,0x04,"GPMC_CONFIG1_0","Register Value",0}, + {0x0014,0x04,"GPMC_CONFIG2_0","Register Value",0}, + {0x0018,0x04,"GPMC_CONFIG3_0","Register Value",0}, + {0x001C,0x04,"GPMC_CONFIG4_0","Register Value",0}, + {0x0020,0x04,"GPMC_CONFIG5_0","Register Value",0}, + {0x0024,0x04,"GPMC_CONFIG6_0","Register Value",0}, + {0x0028,0x04,"GPMC_CONFIG7_0","Register Value",0}, + + {0x002C,0x04,"GPMC_PREFETCH_CONFIG1","Register Value",0}, + {0x0030,0x02,"GPMC_PREFETCH_CONFIG2_LSB","Register Value",0}, + {0x0032,0x02,"GPMC_PREFETCH_CONTROL_LSB","Register Value",0}, + {0x0034,0x02,"GPMC_ECC_CONFIG","Register Value",0}, + {0x0036,0x02,"GPMC_ECC_CONTROL","Register Value",0}, + {0x0038,0x04,"GPMC_ECC_SIZE_CONFIG_LSB","Register Value",0}, + {0x003C,0x04,"Enable_A1_A10","Enable A1-A10 pads",0} +}; +CH_Field OMAP4_CHMMCSD_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C4}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x02,"MMC_SYSCTL_MSW","MMC_SYSCTL_MSW",0}, + {0x000A,0x02,"MMC_SYSCTL_LSW","MMC_SYSCTL_LSW",0}, + + {0x000C,0x04,"BusWidth","BusWidth",0} +}; + +/* Now define here the TOC entry for each item */ +CH_Item_t OMAP4_CHSETTINGS_Item = { {0x0,0x6C,{0,0,0},"CHSETTINGS"}, + OMAP4_CHSETTINGS_Fields, + sizeof(OMAP4_CHSETTINGS_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP4_CHRAM_Item = { {0x0,0x58,{0,0,0},"CHRAM"}, + OMAP4_CHRAM_Fields, + sizeof(OMAP4_CHRAM_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP4_CHFLASH_Item = { {0x0,0x40,{0,0,0},"CHFLASH"}, + OMAP4_CHFLASH_Fields, + sizeof(OMAP4_CHFLASH_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP4_CHMMCSD_Item = { {0x0,0x10,{0,0,0},"CHMMCSD"}, + OMAP4_CHMMCSD_Fields, + sizeof(OMAP4_CHMMCSD_Fields)/sizeof(CH_Field) }; + +/* Make sure to list here each defined item */ +CH_Item_t* OMAP4_ItemsList[] = { &OMAP4_CHSETTINGS_Item, + &OMAP4_CHRAM_Item, + &OMAP4_CHFLASH_Item, + &OMAP4_CHMMCSD_Item }; + +/* Define here your top platform entity, pointing to the item list */ +const OMAP_Platform_t CH_OMAP4_Platform = {"OMAP4",512,OMAP4_ItemsList,sizeof(OMAP4_ItemsList)/sizeof(CH_Item_t*)}; + +#endif // _CH_OMAP4_H diff --git a/PandaBoardPkg/Tools/ch_omap5.h b/PandaBoardPkg/Tools/ch_omap5.h new file mode 100644 index 000000000..1086c5f03 --- /dev/null +++ b/PandaBoardPkg/Tools/ch_omap5.h @@ -0,0 +1,212 @@ +/* + 2 * ch_omap5.h + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +#ifndef _CH_OMAP5_H +#define _CH_OMAP5_H + +/* Define here all the data fields for each item */ +CH_Field OMAP5_CHSETTINGS_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C1}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"Flags","ClockSettings",0}, + //HAL_CKGEN_General_t + {0x000C,0x04,"CM_CLKSEL_CORE","ClockSettings",0}, + {0x0010,0x04,"CM_BYPCLK_MPU","ClockSettings",0}, + {0x0014,0x04,"CM_BYPCLK_IVA","ClockSettings",0}, + {0x0018,0x04,"CM_MPU_CLK_CTRL","ClockSettings",0}, + {0x001C,0x04,"CM_CLKSEL_USB","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t MPU + {0x0020,0x04,"CM_CLKMODE_DPLL_MPU","ClockSettings",0}, + {0x0024,0x04,"CM_AUTOIDLE_DPLL_MPU","ClockSettings",0}, + {0x0028,0x04,"CM_CLKSEL_DPLL_MPU","ClockSettings",0}, + {0x002C,0x04,"CM_DIV_M2_DPLL_MPU","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t CORE + {0x0030,0x04,"CM_CLKMODE_DPLL_CORE","ClockSettings",0}, + {0x0034,0x04,"CM_AUTOIDLE_DPLL_CORE","ClockSettings",0}, + {0x0038,0x04,"CM_CLKSEL_DPLL_CORE","ClockSettings",0}, + {0x003C,0x04,"CM_DIV_M2_DPLL_CORE","ClockSettings",0}, + {0x0040,0x04,"CM_DIV_M3_DPLL_CORE","ClockSettings",0}, + {0x0044,0x04,"CM_DIV_H11_DPLL_CORE","ClockSettings",0}, + {0x0048,0x04,"CM_DIV_H12_DPLL_CORE","ClockSettings",0}, + {0x004C,0x04,"CM_DIV_H13_DPLL_CORE","ClockSettings",0}, + {0x0050,0x04,"CM_DIV_H14_DPLL_CORE","ClockSettings",0}, + {0x0054,0x04,"CM_DIV_H22_DPLL_CORE","ClockSettings",0}, + {0x0058,0x04,"CM_DIV_H23_DPLL_CORE","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t PER5 + {0x005C,0x04,"CM_CLKMODE_DPLL_PER","ClockSettings",0}, + {0x0060,0x04,"CM_AUTOIDLE_DPLL_PER","ClockSettings",0}, + {0x0064,0x04,"CM_CLKSEL_DPLL_PER","ClockSettings",0}, + {0x0068,0x04,"CM_DIV_M2_DPLL_PER","ClockSettings",0}, + {0x006C,0x04,"CM_DIV_M3_DPLL_PER","ClockSettings",0}, + {0x0070,0x04,"CM_DIV_H11_DPLL_PER","ClockSettings",0}, + {0x0074,0x04,"CM_DIV_H12_DPLL_PER","ClockSettings",0}, + {0x0078,0x04,"CM_DIV_H14_DPLL_PER","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t USB1 + {0x007C,0x04,"CM_CLKMODE_DPLL_USB","ClockSettings",0}, + {0x0080,0x04,"CM_AUTOIDLE_DPLL_USB","ClockSettings",0}, + {0x0084,0x04,"CM_CLKSEL_DPLL_USB","ClockSettings",0}, + {0x0088,0x04,"CM_DIV_M2_DPLL_USB","ClockSettings",0} +}; +CH_Field OMAP5_CHRAM_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C2}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"SdramConfig","SDRAM Configuration Register",0}, + {0x000C,0x04,"SdramConfig2","SDRAM Configuration Register",0}, + {0x0010,0x04,"SdramRefresh","SDRAM Refresh Control Register",0}, + {0x0014,0x04,"SdramRefreshShdw","SDRAM Refresh Control Shadow Register",0}, + {0x0018,0x04,"SdramTim1","SDRAM Timing 1 Register",0}, + {0x001C,0x04,"SdramTim2","SDRAM Timing 2 Register",0}, + {0x0020,0x04,"SdramTim3","SDRAM Timing 3 Register",0}, + {0x0024,0x04,"SdramTim1Shdw","SDRAM Timing 1 Shadow Register",0}, + {0x0028,0x04,"SdramTim2Shdw","SDRAM Timing 2 Shadow Register",0}, + {0x002C,0x04,"SdramTim3Shdw","SDRAM Timing 3 Shadow Register",0}, + {0x0030,0x04,"PwrMgtCtrl","Power mgt control Register",0}, + {0x0034,0x04,"PwrMgtCtrlShdw","Power mgt control Shadow Register",0}, + {0x0038,0x04,"DdrPhyCtrl1","DDR PHY Control 1 Register",0}, + {0x003C,0x04,"DdrPhyCtrl2","DDR PHY Control 2 Register",0}, + {0x0040,0x04,"DdrPhyCtrl1Shdw","DDR PHY Control 1 Register",0}, + {0x0044,0x04,"ExtPhyCtrl1","",0}, + {0x0048,0x04,"ExtPhyCtrl2","",0}, + {0x004C,0x04,"ExtPhyCtrl3","",0}, + {0x0050,0x04,"ExtPhyCtrl4","",0}, + {0x0054,0x04,"ExtPhyCtrl5","",0}, + {0x0058,0x04,"ExtPhyCtrl6","",0}, + {0x005C,0x04,"ExtPhyCtrl7","",0}, + {0x0060,0x04,"ExtPhyCtrl8","",0}, + {0x0064,0x04,"ExtPhyCtrl9","",0}, + {0x0068,0x04,"ExtPhyCtrl10","",0}, + {0x006C,0x04,"ExtPhyCtrl11","",0}, + {0x0070,0x04,"ExtPhyCtrl12","",0}, + {0x0074,0x04,"ExtPhyCtrl13","",0}, + {0x0078,0x04,"ExtPhyCtrl14","",0}, + {0x007C,0x04,"ExtPhyCtrl15","",0}, + {0x0080,0x04,"ExtPhyCtrl16","",0}, + {0x0084,0x04,"ExtPhyCtrl17","",0}, + {0x0088,0x04,"ExtPhyCtrl18","",0}, + {0x008C,0x04,"ExtPhyCtrl19","",0}, + {0x0090,0x04,"ExtPhyCtrl20","",0}, + {0x0094,0x04,"ExtPhyCtrl21","",0}, + {0x0098,0x04,"ExtPhyCtrl22","",0}, + {0x009C,0x04,"ExtPhyCtrl23","",0}, + {0x00A0,0x04,"ExtPhyCtrl24","",0}, + {0x00A4,0x04,"ExtPhyCtrl25","",0}, + {0x00A8,0x04,"ExtPhyCtrl26","",0}, + {0x00AC,0x04,"ExtPhyCtrl27","",0}, + {0x00B0,0x04,"ExtPhyCtrl28","",0}, + {0x00B4,0x04,"ExtPhyCtrl29","",0}, + {0x00B8,0x04,"ExtPhyCtrl30","",0}, + {0x00BC,0x04,"ModeReg","",0}, + {0x00C0,0x04,"CoreFreqConfigM2Div","",0}, + {0x00C4,0x04,"DMMLisaMap0","DMM LISA section 0 mapping",0}, + {0x00C8,0x04,"Flags","Configure the chip selects",0} +}; + +CH_Field OMAP5_CHFLASH_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C3}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x02,"GPMC_SYSCONFIG_LSB","",0}, + {0x000A,0x02,"GPMC_IRQENABLE_LSB","",0}, + {0x000C,0x02,"GPMC_TIMEOUT_CONTROL_LSB","",0}, + {0x000E,0x02,"GPMC_CONFIG_LSB","",0}, + {0x0010,0x04,"GPMC_CONFIG1","",0}, + {0x0014,0x04,"GPMC_CONFIG2","",0}, + {0x0018,0x04,"GPMC_CONFIG3","",0}, + {0x001C,0x04,"GPMC_CONFIG4","",0}, + {0x0020,0x04,"GPMC_CONFIG5","",0}, + {0x0024,0x04,"GPMC_CONFIG6","",0}, + {0x0028,0x04,"GPMC_CONFIG7","",0}, + {0x002C,0x04,"GPMC_PREFETCH_CONFIG1","",0}, + {0x0030,0x02,"GPMC_PREFETCH_CONFIG2_LSB","",0}, + {0x0032,0x02,"GPMC_PREFETCH_CONTROL_LSB","",0}, + {0x0034,0x02,"GPMC_ECC_CONFIG","",0}, + {0x0036,0x02,"GPMC_ECC_CONTROL","",0}, + {0x0038,0x04,"GPMC_ECC_SIZE_CONFIG_LSB","",0}, + {0x003C,0x04,"Enable_A1_A10","Enable A1-A10 pads",0} +}; +CH_Field OMAP5_CHMMCSD_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C4}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"CLOCK","",0}, + {0x000C,0x04,"BusWidth","",0} +}; +CH_Field OMAP5_CHSATA_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C5}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"MultiSectorReadEn","",0} +}; + +/* Now define here the TOC entry for each item */ +CH_Item_t OMAP5_CHSETTINGS_Item = { {0x0,0x8C,{0,0,0},"CHSETTINGS"}, + OMAP5_CHSETTINGS_Fields, + sizeof(OMAP5_CHSETTINGS_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHRAM_Item = { {0x0,0xCC,{0,0,0},"CHRAM"}, + OMAP5_CHRAM_Fields, + sizeof(OMAP5_CHRAM_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHFLASH_Item = { {0x0,0x40,{0,0,0},"CHFLASH"}, + OMAP5_CHFLASH_Fields, + sizeof(OMAP5_CHFLASH_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHMMCSD_Item = { {0x0,0x10,{0,0,0},"CHMMCSD"}, + OMAP5_CHMMCSD_Fields, + sizeof(OMAP5_CHMMCSD_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHSATA_Item = { {0x0,0x0C,{0,0,0},"CHSATA"}, + OMAP5_CHSATA_Fields, + sizeof(OMAP5_CHSATA_Fields)/sizeof(CH_Field) }; + +/* Make sure to list here each defined item */ +CH_Item_t* OMAP5_ItemsList[] = { &OMAP5_CHSETTINGS_Item, + &OMAP5_CHRAM_Item, + &OMAP5_CHFLASH_Item, + &OMAP5_CHMMCSD_Item, + &OMAP5_CHSATA_Item }; + +/* Define here your top platform entity, pointing to the item list */ +const OMAP_Platform_t CH_OMAP5_Platform = {"OMAP5",512,OMAP5_ItemsList,sizeof(OMAP5_ItemsList)/sizeof(CH_Item_t*)}; + +#endif // _CH_OMAP5_H diff --git a/PandaBoardPkg/Tools/ch_types.h b/PandaBoardPkg/Tools/ch_types.h new file mode 100644 index 000000000..5f18e1d03 --- /dev/null +++ b/PandaBoardPkg/Tools/ch_types.h @@ -0,0 +1,81 @@ +/* + 2 * ch_types.h + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +#ifndef _CH_TYPES_H +#define _CH_TYPES_H + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef signed int bool_t; + +typedef struct { + uint32_t Offset; + uint32_t Size; + uint8_t Name[64]; + uint8_t *Description; + uint32_t Value; +} CH_Field; + +typedef struct { + uint32_t Start; + uint32_t Size; + uint32_t Reserved[3]; + uint8_t Filename[12]; +} CH_ItemTOC_t; + +typedef struct { + CH_ItemTOC_t TOC; + CH_Field *fields; + uint32_t numberOfFields; +} CH_Item_t; + +typedef struct { + uint8_t Name[16]; + uint32_t ConfigurationHeaderSize; + CH_Item_t** SupportedItemsList; + uint32_t NumberOfSupportedItems; +} OMAP_Platform_t; + +typedef enum { + BIN_FILE, + C_FILE +} outputfile_t; + +#endif // _CH_TYPES_H diff --git a/PandaBoardPkg/Tools/chtool.c b/PandaBoardPkg/Tools/chtool.c new file mode 100644 index 000000000..f127122a6 --- /dev/null +++ b/PandaBoardPkg/Tools/chtool.c @@ -0,0 +1,1064 @@ +/* + 2 * chtool.c + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +/*------------------------------ Include Files -------------------------------*/ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/stat.h> +#include <ctype.h> + +#include "ch_types.h" +#include "ch_omap4.h" +#include "ch_omap5.h" + +/*------------------------------ Local Definitions ---------------------------*/ + + +/*------------------------------ Local Types ---------------------------------*/ +typedef enum { + NO_IMAGE, + PREPENDED_CH, + MERGED_TOCS +} OutMode_t; +typedef struct { + char* infile; + char* outfile; + char* imagefile; + OutMode_t OutMode; + bool_t removeCH; + outputfile_t out_type; + OMAP_Platform_t* platform; +} Params_t; + +/*------------------------------ Local Variables -----------------------------*/ +const OMAP_Platform_t* LV_plist[] = {&CH_OMAP4_Platform,&CH_OMAP5_Platform}; + +/*------------------------------ Local Constants -----------------------------*/ +#define CHTOOL_VERSION "0.4" +#define CH_TRUE 1 +#define CH_FALSE 0 + +/*------------------------------ Local Functions Declarations ----------------*/ +int32_t CheckArguments(int argc, char* argv[],Params_t* params); +void PrintPlatformSettings(OMAP_Platform_t* p); +void PrintHelp(char *progname); +int32_t FileExtension(const char *file,const char *pattern); +int32_t dat2bin(Params_t *p); +int32_t bin2dat(Params_t *p); +int32_t RemoveCH(Params_t *p); +int32_t CreateImageFile(Params_t *p); +uint8_t CheckPlatformCompatibilityWithCHFormat(uint8_t *CH,uint32_t FileSize,OMAP_Platform_t* omap); + +/*------------------------------ Global Functions ----------------------------*/ +/*------------------------------ Local Functions -----------------------------*/ + + +/*------------------------------------------------------------------------------ +* FUNCTION : Main +* +* DESCRIPTION: The function is the top function of the tool, simply calling +* first the arguments chechker and then the appropriate +* function, either image generation or extraction. +* +* +* PARAMETERS : argc - number of arguments +* argv - arguments values +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int main(int argc, char* argv[]) +{ + Params_t params; + + if (CheckArguments(argc,argv,¶ms) != 0) + { + return 0; + } + + // TODO : the job + if (FileExtension(params.infile,"dat") == 0) + { + int32_t err_code; + err_code = dat2bin(¶ms); + if (err_code == 0) + { + if (params.OutMode != NO_IMAGE) + { + CreateImageFile(¶ms); + } + } + } + else if (FileExtension(params.outfile,"dat") == 0) + { + int32_t err_code; + err_code = bin2dat(¶ms); + if ((err_code == 0)&&(params.removeCH == CH_TRUE)) + { + // Remove configuration header from input bin file + RemoveCH(¶ms); + } + } + else + { + printf("Unrecognized file extension...\n"); + } + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : CheckArguments +* +* DESCRIPTION: This function is in charge of checking the command-line +* arguments given by the user and display the help page +* in case of troubles. +* +* +* PARAMETERS : argc - number of arguments +* argv - arguments values +* params - an empty data structure to store the parameters +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t CheckArguments(int argc, char* argv[],Params_t* params) +{ + int32_t i,j,k; + + params->infile = NULL; + params->outfile = NULL; + params->imagefile = NULL; + params->OutMode = NO_IMAGE; + params->removeCH = CH_FALSE; + params->out_type = BIN_FILE; + params->platform = NULL; + + if (argc == 1) + { + PrintHelp(argv[0]); + return -1; + } + + for (i=1 ; i<argc ; i++) + { + if (strcmp(argv[i],"-p")==0) + { + int match=0; + for (j=0 ; j<(sizeof(LV_plist)/sizeof(const OMAP_Platform_t *)) ; j++) + { + int len = strlen(argv[i+1]); + for(k=0;k<len;k++) + { + argv[i+1][k] = toupper(argv[i+1][k]); + } + if (strcmp(LV_plist[j]->Name,argv[i+1])==0) + { + params->platform = (OMAP_Platform_t*) (LV_plist[j]); + match=1; + } + } + if (match==0) + { + printf("ERROR : Platform %s is not supported...\n",argv[i+1]); + return -1; + } + i++; + } + else if (strcmp(argv[i],"-c")==0) + { + params->out_type = C_FILE; + } + else if (strcmp(argv[i],"-rmch")==0) + { + params->removeCH = CH_TRUE; + } + else if (strcmp(argv[i],"-m")==0) + { + params->imagefile = argv[i+1]; + if (params->outfile == NULL) + { + params->outfile = "tmp.bin"; + } + params->OutMode = MERGED_TOCS; + i++; + } + else if (strcmp(argv[i],"-i")==0) + { + params->infile = argv[i+1]; + i++; + } + else if (strcmp(argv[i],"-o")==0) + { + params->outfile = argv[i+1]; + i++; + } + else if (strcmp(argv[i],"-O")==0) + { + params->imagefile = argv[i+1]; + if (params->outfile == NULL) + { + params->outfile = "tmp.bin"; + } + params->OutMode = PREPENDED_CH; + i++; + } + else if (strcmp(argv[i],"-v")==0) + { + if (params->platform != NULL) + { + PrintPlatformSettings(params->platform); + } + } + else if (strcmp(argv[i],"-h")==0) + { + PrintHelp(argv[0]); + return -1; + } + else + { + printf("Option %s is not supported...\n",argv[i]); + printf("Type '%s -h' for more a list of supported options\n",argv[0]); + return -1; + } + } + + if (params->infile == NULL) + { + printf("ERROR : Please provide an input file\n"); + return -1; + } + if (params->outfile == NULL) + { + printf("ERROR : Please provide an output file\n"); + return -1; + } + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : PrintPlatformSettings +* +* DESCRIPTION: This function is in charge of printing to console all +* the possible parameters supported by a specified platform +* +* +* PARAMETERS : p - pointer to the data structure describing the platform +* +* RETURNS : +* +*-----------------------------------------------------------------------------*/ +void PrintPlatformSettings(OMAP_Platform_t* p) +{ + int32_t i,j; + printf("Platform %s\n",p->Name); + + for(i=0 ; i<p->NumberOfSupportedItems ; i++) + { + CH_Item_t* it = p->SupportedItemsList[i]; + printf("\tItem %s (size 0x%.4X)\n",it->TOC.Filename,it->TOC.Size); + for (j=0 ; j<it->numberOfFields ; j++) + { + CH_Field f = it->fields[j]; + printf("\t\t0x%.4X %-4d %-32s %-40s 0x%-4.4X\n",f.Offset,f.Size,f.Name,f.Description,f.Value); + } + } + printf("\n\n"); +} + +/*------------------------------------------------------------------------------ +* FUNCTION : PrintHelp +* +* DESCRIPTION: This function prints the help page to console +* +* +* PARAMETERS : progname - string containing the program name +* +* RETURNS : +* +*-----------------------------------------------------------------------------*/ +void PrintHelp(char *progname) +{ + int32_t i; + printf("\n"); + printf("Version " CHTOOL_VERSION "\n\n"); + + printf("Usage : %s <options>\n\n",progname); + + printf("Options :\n"); + printf("\t-p <platform_name> : selects the target platform. Supported platforms : "); + for (i=0 ; i<(sizeof(LV_plist)/sizeof(const OMAP_Platform_t *)) ; i++) + { + printf("%s ",LV_plist[i]->Name); + } + printf("\n"); + printf("\t-i <input_CH_file> : input file can be either a *.bin file (for target) or a *.dat file (containing parameters)\n"); + printf("\t-o <output_CH_file> : output file can be either a *.bin file (for target) or a *.dat file (containing parameters)\n"); + printf("\t-m <merge_file> : merges the provided signed image's TOC with the configuration header settings\n"); + printf("\t-O <image_file> : prepend the output CH binary to the provided binary image file\n"); + printf("\t-c : generate c file conforming to Topsim format, instead of the usual binary file\n"); + printf("\t-rmch : remove the input file's configuration header\n"); + printf("\t-v : verbose mode prints to screen all the configuration header fields for the selected platform\n"); + printf("\t-h : prints help\n"); + printf("\n\n"); + + printf("Supported platform(s) : "); + for (i=0 ; i<(sizeof(LV_plist)/sizeof(const OMAP_Platform_t *)) ; i++) + { + printf("%s ",LV_plist[i]->Name); + } + printf("\n\n\n"); +} + +/*------------------------------------------------------------------------------ +* FUNCTION : FileExtension +* +* DESCRIPTION: This function extracts the extension from a filename +* and compares it with a specified pattern +* +* +* PARAMETERS : file - string containing the file name +* pattern - pattern to be compared with the file extension +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t FileExtension(const char *file,const char *pattern) +{ + int32_t i,j; + for (i=strlen(file)-1 ; i>=0 ; i--) + { + if (file[i] == '.') + { + i++; + break; + } + } + if (i == 0) + { + // No extension found... + return -1; + } + if (strlen(pattern) != (strlen(file) - i)) + { + // Extension length do not match + return -1; + } + for (j=0 ; j<strlen(pattern) ; j++) + { + if (pattern[j] != file[i+j]) + { + // Mismatch in extension... + return -1; + } + } + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : dat2bin +* +* DESCRIPTION: This function generates a binary file containing a +* Configuration Header image from a set of parameters given +* by the user through an input file +* +* +* PARAMETERS : p - parameters given to the program (including +* input and output filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t dat2bin(Params_t *p) +{ + FILE *inf; + FILE *outf; + char myline[128]; + char myword0[128]; + char myword1[128]; + OMAP_Platform_t *omap = p->platform; + CH_Item_t *item = NULL; + uint8_t *CH; + uint8_t *CHt; + uint32_t idx; + uint32_t nItems=0; + uint32_t tmpoffset=0; + + // Open files + inf = fopen(p->infile,"rb"); + outf = fopen(p->outfile,"wb"); + + if ((inf == NULL) || (outf == NULL)) + { + if (inf != NULL) + { + fclose(inf); + } + if (outf != NULL) + { + fclose(outf); + } + return -1; + } + + // If platform is not specified in command-line arguments, try to see if the target is given in the *.dat file + if (omap == NULL) + { + while(fscanf(inf,"%s",myline) != EOF) + { + int32_t i,j; + for (i=0 ; myline[i] != '\0' ; i++) + { + if ((myline[i] == ';') || (myline[i] == '#')) + { + break; + } + if (myline[i] == '=') + { + myline[i] = ' '; + sscanf(myline,"%s %s",myword0,myword1); + if (strcmp(myword0,"TARGET")==0) + { + for(j=0 ; j<sizeof(LV_plist)/sizeof(OMAP_Platform_t*) ; j++) + { + if (strcmp(myword1,LV_plist[j]->Name) == 0) + { + omap = (OMAP_Platform_t*)LV_plist[j]; + p->platform = omap; + } + } + } + break; + } + } + } + fseek(inf,0,SEEK_SET); + } + + // Check that a platform is specified (for output format choice) + if (omap == NULL) + { + printf("ERROR : Platform must be specified, either in command-line or in provided parameter file\n"); + fclose(inf); + fclose(outf); + return -1; + } + + // Allocate Configuration Header memory space + CH = (uint8_t *)malloc(omap->ConfigurationHeaderSize * sizeof(uint8_t)); + memset(CH,0,omap->ConfigurationHeaderSize * sizeof(uint8_t)); + + // Count the number of valid items in image + while(fscanf(inf,"%s",myline) != EOF) + { + int32_t i,j; + for (i=0 ; myline[i] != '\0' ; i++) + { + if (myline[i] == '=') + { + // If we find a '=', then it is not an item section beginning, so break + break; + } + } + if (myline[i] == '\0') + { + // we came to the end of the line w/o finding a '='.... it seems to be a new item section starting point + for (j=0 ; j<omap->NumberOfSupportedItems ; j++) + { + if (strcmp(omap->SupportedItemsList[j]->TOC.Filename,myline)==0) + { + nItems++; + break; + } + } + } + } + //printf("Found %d valid items in input file...\n",nItems); + + /* Come back to the beginning of the file */ + fseek(inf,0,SEEK_SET); + while(fscanf(inf,"%s",myline) != EOF) + { + int32_t i,j; + uint32_t val; + + for (i=0 ; myline[i] != '\0' ; i++) + { + if (myline[i] == '=') + { + myline[i] = ' '; + + sscanf(myline,"%s %s",myword0,myword1); + if (strcmp(myword0,"TARGET")==0) + { + // Ignore here... only informative + } + else + { + // Set item attribute + if ((myword1[0] == '0') && (myword1[1] == 'x')) + { + sscanf(myline,"%s 0x%X",myword0,&val); + } + else + { + sscanf(myline,"%s %d",myword0,&val); + } + + //printf("%s <- 0x%X\n",myword0,val); + + if (item != NULL) + { + for (j=0 ; j<item->numberOfFields ; j++) + { + CH_Field f = item->fields[j]; + if (strcmp(f.Name,myword0)==0) + { + int32_t k; + // Write it in little endian !!! + //printf("fieldSize=%d\n",f.Size); + for (k=0 ; k<f.Size ; k++) + { + uint32_t address = item->TOC.Start + f.Offset + k; + if (address < omap->ConfigurationHeaderSize) + { + CH[address] = (uint8_t)(val & 0xFF); + } + else + { + printf("ERROR : trying to write on address %d but Configuration Header length is %d. Ignoring...\n",address,omap->ConfigurationHeaderSize); + } + //printf("0x%.2X ",val & 0xFF); + val >>= 8; + } + break; + } + } + if (j == item->numberOfFields) + { + //printf("WARNING - Could not find field %s in %s item. This input will be ignored...\n",myword0,item->TOC.Filename); + } + } + } + break; + } + } + + if (myline[i] == '\0') + { + + // Change item + for (j=0 ; j<omap->NumberOfSupportedItems ; j++) + { + if (strcmp(omap->SupportedItemsList[j]->TOC.Filename,myline)==0) + { + //itemN=j; + //itemOffset = (nItems+1)*sizeof(CH_ItemTOC_t) + tmpoffset; + item = omap->SupportedItemsList[j]; + //item->TOC.Start = itemOffset; + item->TOC.Start = (nItems+1)*sizeof(CH_ItemTOC_t) + tmpoffset; + + //printf("ITEM %s (number %d) : Start=0x%.4X ; Size=%d...\n",myline,itemN,item->TOC.Start,item->TOC.Size); + tmpoffset += (omap->SupportedItemsList[j]->TOC.Size); + + break; + } + } + if (j==omap->NumberOfSupportedItems) + { + //printf("ERROR : Item %s is not supported. Please check your parameter file...\n",myline); + } + } + } + + // ... close the input file + fclose(inf); + + // Now, write the TOC ... + for (CHt=CH, idx=0 ; idx<omap->NumberOfSupportedItems ; idx++) + { + if (omap->SupportedItemsList[idx]->TOC.Start != 0) + { + memcpy(CHt, omap->SupportedItemsList[idx], sizeof(CH_ItemTOC_t)); + CHt += sizeof(CH_ItemTOC_t); + } + } + memset(CHt,0xFF,sizeof(CH_ItemTOC_t)); + + if (p->out_type == C_FILE) + { + int32_t i,j; + const char *c_header = "#include \"GlobalTypes.h\"\n\n__align(4) const unsigned char LC_Toc[] = \n{\n"; + const char *c_tail = "};\n\n/*================================ End Of File ==============================*/\n"; + fwrite(c_header,sizeof(uint8_t),strlen(c_header),outf); + for(i=0 ; i<32 ; i++) + { + for(j=0 ; j<16 ; j++) + { + if ((i == 31) && (j == 15)) + { + fprintf(outf,"0x%.2x",CH[(i<<4)|j]); + } + else + { + fprintf(outf,"0x%.2x, ",CH[(i<<4)|j]); + } + } + fprintf(outf,"\n"); + } + fwrite(c_tail,sizeof(uint8_t),strlen(c_tail),outf); + } + else + { + // Write everything to the output file in standard binary format + fwrite(CH,sizeof(uint8_t),omap->ConfigurationHeaderSize,outf); + } + + // ... close the output file + fclose(outf); + + // Free Configuration Header memory space + free(CH); + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : bin2dat +* +* DESCRIPTION: This function extracts all the parameters stored in a binary +* file containing a Configuration Header image and stores them +* into an output file +* +* +* PARAMETERS : p - parameters given to the program (including +* input and output filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t bin2dat(Params_t *p) +{ + FILE *inf; + FILE *outf; + struct stat FileStat; + uint32_t FileSize; + OMAP_Platform_t *omap; + uint8_t *CH; + int32_t i,j,k; + uint8_t MatchFound; + + // Open the files + inf = fopen(p->infile,"rb"); + outf = fopen(p->outfile,"wb"); + + if ((inf == NULL) || (outf == NULL)) + { + if (inf != NULL) + { + fclose(inf); + } + if (outf != NULL) + { + fclose(outf); + } + return -1; + } + + // Stat the input file to get the input inage size + fstat(fileno(inf), &FileStat); + FileSize = (uint32_t) FileStat.st_size; + //printf("Input file size is %dbytes\n",FileSize); + + // Fill an temporary buffer with the file content + CH = (uint8_t *)malloc(FileSize * sizeof(uint8_t)); + fread(CH,FileSize,sizeof(uint8_t),inf); + + // Close the input file + fclose(inf); + + if (p->platform == NULL) + { + // Try to guess the target by parsing the TOC + // Browse the supported platform list and take the first platform matching these : + // - The input image size matches the expected configuration header size for the platform + // - All item names (CHSETTINGS, CHRAM,...) contained in the input image are supported by the platform + // - For each of these items, the item data size must match the expected size + for (MatchFound=0,i=0 ; (MatchFound==0)&&(i<(sizeof(LV_plist) / sizeof(OMAP_Platform_t*))) ; i++) + { + omap = (OMAP_Platform_t*) LV_plist[i]; + MatchFound = CheckPlatformCompatibilityWithCHFormat(CH,FileSize,omap); + } + + if (MatchFound==1) + { + printf("Found platform compatibility with %s...\n",omap->Name); + p->platform = omap; + } + else + { + printf("Could not find a compatible platform for this image\n"); + return -1; + } + } + else + { + omap = p->platform; + MatchFound = CheckPlatformCompatibilityWithCHFormat(CH,FileSize,omap); + if (MatchFound==0) + { + printf("Compatibility test with %s platform's Configuration Header format FAILED\n", omap->Name); + return -1; + } + } + + if (MatchFound != 0) + { + CH_Item_t *item; + CH_ItemTOC_t *toc; + + //OK, do the job ! + fprintf(outf,"TARGET=%s\n",omap->Name); + + // Point to the first TOC entry of the input image + toc = (CH_ItemTOC_t *)CH; + while(toc->Start != 0xFFFFFFFF) + { + for(i=0 ; i<omap->NumberOfSupportedItems ; i++) + { + if (strcmp(omap->SupportedItemsList[i]->TOC.Filename,toc->Filename) == 0) + { + item = omap->SupportedItemsList[i]; + break; + } + } + // Print the item name + fprintf(outf,"\n%s\n",toc->Filename); + + // Then reverse all the items + for(j=0 ; j<item->numberOfFields ; j++) + { + uint32_t value = 0; + uint8_t *pvalue = (uint8_t *)&value; + CH_Field f = item->fields[j]; + + for(k=0 ; k<f.Size ; k++) + { + pvalue[k] = CH[toc->Start + f.Offset + k]; + } + + //printf("Field %s value is 0x%.8X\n",f.Name,value); + fprintf(outf,"%s=0x%.8X\n",f.Name,value); + } + + // Then move to next TOC entry of the input image + toc++; + } + } + + // Free the temporary buffer space + free(CH); + + // Close the output file + fclose(outf); + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : bin2dat +* +* DESCRIPTION: This function extracts all the parameters stored in a binary +* file containing a Configuration Header image and stores them +* into an output file +* +* +* PARAMETERS : p - parameters given to the program (including +* input and output filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t RemoveCH(Params_t *p) +{ + FILE *f; + struct stat FileStat; + uint32_t FileSize; + + // Open the files + f = fopen(p->infile,"rb"); + + if (f == NULL) + { + return -1; + } + + // Stat the input file to get the input inage size + fstat(fileno(f), &FileStat); + FileSize = (uint32_t) FileStat.st_size; + //printf("Input file size is %dbytes\n",FileSize); + + if (p->platform != NULL) + { + uint8_t *buffer = (uint8_t *)malloc(FileSize * sizeof(uint8_t)); + if (buffer == NULL) + { + fclose(f); + return -1; + } + + fread((void *)buffer,sizeof(uint8_t),FileSize,f); + fclose(f); + f = fopen(p->infile,"wb"); + if (f == NULL) + { + free(buffer); + return -1; + } + + fwrite((void *)(buffer + p->platform->ConfigurationHeaderSize),sizeof(uint8_t),FileSize - p->platform->ConfigurationHeaderSize,f); + free(buffer); + } + + fclose(f); + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : CreateImageFile +* +* DESCRIPTION: This function merges configuration header's TOC with +* a provided signed image's TOC. +* +* +* PARAMETERS : p - parameters given to the program (including +* config header and signed image filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t CreateImageFile(Params_t *p) +{ + FILE *chf; + FILE *sif; + struct stat FileStat; + uint32_t ch_size,si_size; + uint8_t *CH; + uint8_t *SI; + CH_ItemTOC_t *toc_entry; + uint32_t ch_tocsize; + uint32_t si_tocsize; + uint32_t new_tocsize; + uint32_t ch_itemsize; + + + // Open the files + chf = fopen(p->outfile,"rb"); /* config header file */ + sif = fopen(p->imagefile,"rb"); /* signed image file */ + + if ((chf == NULL) || (sif == NULL)) + { + if (chf != NULL) + { + fclose(chf); + } + if (sif != NULL) + { + fclose(sif); + } + return -1; + } + + // Stat the CH file to get the CH image size + fstat(fileno(chf), &FileStat); + ch_size = (uint32_t) FileStat.st_size; + + // Fill an temporary buffer with the CH file content + CH = (uint8_t *)malloc(ch_size * sizeof(uint8_t)); + fread(CH,ch_size,sizeof(uint8_t),chf); + + // Close the CH file + fclose(chf); + + // Stat the signed image file to get the signed image size + fstat(fileno(sif), &FileStat); + si_size = (uint32_t) FileStat.st_size; + + // Fill an temporary buffer with the CH file content + SI = (uint8_t *)malloc(si_size * sizeof(uint8_t)); + fread(SI,si_size,sizeof(uint8_t),sif); + + // Close the CH file + fclose(sif); + + // Now, analyze SI file's TOC to get its size + si_tocsize=0; + for(toc_entry=(CH_ItemTOC_t *)SI ; (toc_entry->Start != 0xFFFFFFFF) ; toc_entry++) + { + si_tocsize += (sizeof(CH_ItemTOC_t)); + } + + // Now, analyze CH file's TOC and TOC items to get their sizes + ch_tocsize=0; + ch_itemsize=0; + for(toc_entry=(CH_ItemTOC_t *)CH ; (toc_entry->Start != 0xFFFFFFFF) ; toc_entry++) + { + ch_tocsize += (sizeof(CH_ItemTOC_t)); + ch_itemsize += toc_entry->Size; + } + + switch (p->OutMode) + { + case MERGED_TOCS: + new_tocsize = ch_tocsize + sizeof(CH_ItemTOC_t) + si_tocsize; + if (new_tocsize > p->platform->ConfigurationHeaderSize) + { + printf("WARNING : Configuration header and image TOC are too big (%d bytes) to fit in the first %d bytes. Program will attempt to prepend CH to image binary file",new_tocsize,p->platform->ConfigurationHeaderSize); + p->OutMode = PREPENDED_CH; + } + else + { + break; + } + case PREPENDED_CH: + new_tocsize = ch_tocsize + sizeof(CH_ItemTOC_t); + if (new_tocsize > p->platform->ConfigurationHeaderSize) + { + printf("ERROR : This configuration header is too big (%d bytes) to be prepended to the image file. Maximum supported size is %d bytes.\n",new_tocsize,p->platform->ConfigurationHeaderSize); + return -1; + } + break; + default: + printf("ERROR : This output mode is not supported.\n"); + return -1; + break; + } + + /* Open the output file (signed image file) */ + sif = fopen(p->imagefile,"wb"); /* signed image file */ + + /* Process */ + switch (p->OutMode) + { + case MERGED_TOCS: + for(toc_entry=(CH_ItemTOC_t *)CH ; (toc_entry->Start != 0xFFFFFFFF) ; toc_entry++) + { + // Add a constant offset to each config header TOC entry, equivalent to the signed image TOC size (overhead of muxing) + toc_entry->Start += si_tocsize; + } + fwrite(CH,sizeof(uint8_t),ch_tocsize,sif); /* copy configuration header's TOC */ + fwrite(SI,sizeof(uint8_t),si_tocsize + sizeof(CH_ItemTOC_t),sif); /* copy signed image's TOC + the TOCEND entry */ + fwrite((void *)(CH + ch_tocsize + sizeof(CH_ItemTOC_t)),sizeof(uint8_t),ch_itemsize,sif); /* copy configuration header's items */ + fwrite((void *)(SI + si_tocsize + sizeof(CH_ItemTOC_t)),sizeof(uint8_t),p->platform->ConfigurationHeaderSize - (new_tocsize + ch_itemsize),sif); /* Add some padding between configuratino header items and signed image items */ + fwrite((void *)(SI + p->platform->ConfigurationHeaderSize),sizeof(uint8_t),si_size - p->platform->ConfigurationHeaderSize,sif); /* Copy signed image items */ + break; + case PREPENDED_CH: + fwrite(CH,sizeof(uint8_t),p->platform->ConfigurationHeaderSize,sif); /* copy configuration header */ + fwrite(SI,sizeof(uint8_t),si_size,sif); /* copy signed image */ + break; + default: + break; + } + + // All changes are done, close the signed image file... + fclose(sif); + + // Free allocated space for input files + free(CH); + free(SI); + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : CheckPlatformCompatibilityWithCHFormat +* +* DESCRIPTION: This function analyze a Configuration Header image and +* tries to determine its compatibility with a given platform, +* based on the TOC entries and on their respective size +* +* +* PARAMETERS : CH - input Configuration Header image +* Filesize - input Configuration Header image size +* omap - platform to be checked for compatibility +* +* RETURNS : 1 in case of compatibility +* 0 in case of incompatibility +* +*-----------------------------------------------------------------------------*/ +uint8_t CheckPlatformCompatibilityWithCHFormat(uint8_t *CH,uint32_t FileSize,OMAP_Platform_t* omap) +{ + uint8_t MatchFound=0; + int j,k; + + CH_ItemTOC_t *toc; + + /* commented the following line since file size comparison is not meaningfull when people provides + not only the config header but also the code image */ + //if (FileSize == omap->ConfigurationHeaderSize) + { + for(j=0,toc=(CH_ItemTOC_t *)CH ; toc->Start != 0xFFFFFFFF ; toc++,j++) + { + for(MatchFound=0,k=0 ; k<omap->NumberOfSupportedItems ; k++) + { + if (strcmp(omap->SupportedItemsList[k]->TOC.Filename,toc->Filename)==0) + { + if (omap->SupportedItemsList[k]->TOC.Size == toc->Size) + { + MatchFound=1; + } + break; + } + } + if (MatchFound==0) + { + break; + } + } + } + return MatchFound; +} + +/*-------------------------------End of File ---------------------------------*/ diff --git a/PandaBoardPkg/Tools/makefile b/PandaBoardPkg/Tools/makefile new file mode 100755 index 000000000..fe5eea853 --- /dev/null +++ b/PandaBoardPkg/Tools/makefile @@ -0,0 +1,22 @@ +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +all: GenerateImage replace + +GenerateImage: generate_image.c + $(CC) $(CCFLAGS) $(LDFLAGS) -o GenerateImage.exe generate_image.c + +replace: replace.c + $(CC) $(CCFLAGS) $(LDFLAGS) -o replace.exe replace.c + +clean: + del GenerateImage.exe generate_image.obj replace.exe replace.obj diff --git a/PandaBoardPkg/Tools/mkheader.pl b/PandaBoardPkg/Tools/mkheader.pl new file mode 100755 index 000000000..8e0e81883 --- /dev/null +++ b/PandaBoardPkg/Tools/mkheader.pl @@ -0,0 +1,39 @@ +#!/usr/bin/perl + +my $size = -s "$ARGV[0]"; +#my $addr = 0x80008000; +my $addr = 0x80008208; + +open OUTPUT_FILE, ">$ARGV[1]"; +open INPUT_FILE, "<$ARGV[0]"; + +binmode OUTPUT_FILE; +binmode INPUT_FILE; + +$size-=0x200; +$size-=8; + +print OUTPUT_FILE chr($size&0xFF); +$size>>=8; +print OUTPUT_FILE chr($size&0xFF); +$size>>=8; +print OUTPUT_FILE chr($size&0xFF); +$size>>=8; +print OUTPUT_FILE chr($size&0xFF); + +print OUTPUT_FILE chr($addr&0xFF); +$addr>>=8; +print OUTPUT_FILE chr($addr&0xFF); +$addr>>=8; +print OUTPUT_FILE chr($addr&0xFF); +$addr>>=8; +print OUTPUT_FILE chr($addr&0xFF); + +seek INPUT_FILE, 520, 0; + +while(<INPUT_FILE>) { + print OUTPUT_FILE $_; +} + +close OUTPUT_FILE; +close INPUT_FILE; diff --git a/PandaBoardPkg/b.bat b/PandaBoardPkg/b.bat new file mode 100755 index 000000000..af4a8cbdc --- /dev/null +++ b/PandaBoardPkg/b.bat @@ -0,0 +1,68 @@ +@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@REM Example usage of this script. default is a DEBUG build +@REM b +@REM b clean +@REM b release +@REM b release clean +@REM b -v -y build.log + +ECHO OFF +@REM Setup Build environment. Sets WORKSPACE and puts build in path +CALL ..\edksetup.bat + +@REM Set for tools chain. Currently RVCT31 +SET TARGET_TOOLS=RVCT31 +SET TARGET=DEBUG + +@if /I "%1"=="RELEASE" ( + @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it + SET TARGET=RELEASE + shift /1 +) + +SET BUILD_ROOT=%WORKSPACE%\Build\PandaBoard\%TARGET%_%TARGET_TOOLS% + +@REM Build the Panda Board firmware and creat an FD (FLASH Device) Image. +CALL build -p PandaBoardPkg\PandaBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8 +@if ERRORLEVEL 1 goto Exit + +@if /I "%1"=="CLEAN" goto Clean + +@REM +@REM Ram starts at 0x80000000 +@REM OMAP TRM defines 0x80008208 as the entry point +@REM The reset vector is caught by the mask ROM in the OMAP so that is why this entry +@REM point looks so strange. +@REM OMAP TRM section 26.4.8 has Image header information. (missing in OMAP TRM) +@REM +@cd Tools + +ECHO Building tools... +CALL nmake + +ECHO Patching image with ConfigurationHeader.dat +CALL GenerateImage -D ..\ConfigurationHeader.dat -E 0x80008208 -I %BUILD_ROOT%\FV\PANDABOARD_EFI.fd -O %BUILD_ROOT%\FV\PandaBoard_EFI_flashboot.fd + +ECHO Patching ..\Debugger_scripts ... +SET DEBUGGER_SCRIPT=..\Debugger_scripts +@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do ( + @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW %WORKSPACE% +) + +cd .. +:Exit +EXIT /B + +:Clean +cd Tools +CALL nmake clean +cd .. diff --git a/PandaBoardPkg/ba.bat b/PandaBoardPkg/ba.bat new file mode 100755 index 000000000..e3a3b9395 --- /dev/null +++ b/PandaBoardPkg/ba.bat @@ -0,0 +1,68 @@ +@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@REM Example usage of this script. default is a DEBUG build +@REM b +@REM b clean +@REM b release +@REM b release clean +@REM b -v -y build.log + +ECHO OFF +@REM Setup Build environment. Sets WORKSPACE and puts build in path +CALL ..\edksetup.bat + +@REM Set for tools chain. Currently ARMGCC +SET TARGET_TOOLS=ARMGCC +SET TARGET=DEBUG + +@if /I "%1"=="RELEASE" ( + @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it + SET TARGET=RELEASE + shift /1 +) + +SET BUILD_ROOT=%WORKSPACE%\Build\PandaBoard\%TARGET%_%TARGET_TOOLS% + +@REM Build the Panda Board firmware and creat an FD (FLASH Device) Image. +CALL build -p PandaBoardPkg\PandaBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8 +@if ERRORLEVEL 1 goto Exit + +@if /I "%1"=="CLEAN" goto Clean + +@REM +@REM Ram starts at 0x80000000 +@REM OMAP TRM defines 0x80008208 as the entry point +@REM The reset vector is caught by the mask ROM in the OMAP so that is why this entry +@REM point looks so strange. +@REM OMAP TRM section 26.4.8 has Image header information. (missing in OMAP TRM) +@REM +@cd Tools + +ECHO Building tools... +CALL nmake + +ECHO Patching image with ConfigurationHeader.dat +CALL GenerateImage -D ..\ConfigurationHeader.dat -E 0x80008208 -I %BUILD_ROOT%\FV\PANDABOARD_EFI.fd -O %BUILD_ROOT%\FV\PandaBoard_EFI_flashboot.fd + +ECHO Patching ..\Debugger_scripts ... +SET DEBUGGER_SCRIPT=..\Debugger_scripts +@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do ( + @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW %WORKSPACE% +) + +cd .. +:Exit +EXIT /B + +:Clean +cd Tools +CALL nmake clean +cd .. diff --git a/PandaBoardPkg/build.sh b/PandaBoardPkg/build.sh new file mode 100755 index 000000000..dc4b9067d --- /dev/null +++ b/PandaBoardPkg/build.sh @@ -0,0 +1,164 @@ +#!/bin/bash +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +set -e +shopt -s nocasematch + +function process_debug_scripts { + if [[ -d $1 ]]; then + for filename in `ls $1` + do + sed -e "s@ZZZZZZ@$BUILD_ROOT@g" -e "s@WWWWWW@$WORKSPACE@g" \ + "$1/$filename" \ + > "$BUILD_ROOT/$filename" + + #For ARMCYGWIN, we have to change /cygdrive/c to c: + if [[ $TARGET_TOOLS == RVCT31CYGWIN ]] + then + mv "$BUILD_ROOT/$filename" "$BUILD_ROOT/$filename"_temp + sed -e "s@/cygdrive/\(.\)@\1:@g" \ + "$BUILD_ROOT/$filename"_temp \ + > "$BUILD_ROOT/$filename" + rm -f "$BUILD_ROOT/$filename"_temp + fi + done + fi +} + + +# +# Setup workspace if it is not set +# +if [ -z "${WORKSPACE:-}" ] +then + echo Initializing workspace + cd .. +# Uses an external BaseTools project +# export EDK_TOOLS_PATH=`pwd`/../BaseTools +# Uses the BaseTools in edk2 + export EDK_TOOLS_PATH=`pwd`/BaseTools + source edksetup.sh BaseTools +else + echo Building from: $WORKSPACE +fi + +# +# Pick a default tool type for a given OS if no toolchain already defined +# +if [ X"$TOOLCHAIN" != X"" ] +then + TARGET_TOOLS="$TOOLCHAIN" +fi + +if [ -z "${TARGET_TOOLS:-}" ] +then + case `uname` in + CYGWIN*) + TARGET_TOOLS=RVCT31CYGWIN + ;; + Linux*) + if [[ ! -z `locate arm-linux-gnueabi-gcc` ]]; then + TARGET_TOOLS=ARMLINUXGCC + else + TARGET_TOOLS=ARMGCC + fi + ;; + Darwin*) + Major=$(uname -r | cut -f 1 -d '.') + if [[ $Major == 9 ]] + then + # Not supported by this open source project + TARGET_TOOLS=XCODE31 + else + TARGET_TOOLS=XCODE32 + fi + ;; + esac +fi + +TARGET=DEBUG +BUILD_TARGET=DEBUG +args=($@) + +for (( i=0; i<$#; i++ )) +do + if [[ "${args[$i]}" == "-b" ]] + then + TARGET=${args[$i+1]} + BUILD_TARGET=$TARGET + if [[ "$TARGET" == "RELEASE" ]] + then + BUILD_TARGET="$BUILD_TARGET -D DEBUG_TARGET=RELEASE" + fi + i=$i+1 + else + other_args="$other_args ${args[$i]}" + fi +done + +BUILD_ROOT=$WORKSPACE/Build/PandaBoard/"$TARGET"_"$TARGET_TOOLS" +GENERATE_IMAGE=$WORKSPACE/PandaBoardPkg/Tools/chtool +FLASH_BOOT=$BUILD_ROOT/FV/PandaBoard_EFI_flashboot.fd + +if [[ ! -e $EDK_TOOLS_PATH/Source/C/bin ]]; +then + # build the tools if they don't yet exist + echo Building tools: $EDK_TOOLS_PATH + make -C $EDK_TOOLS_PATH +else + echo using prebuilt tools +fi + +# +# Build the edk2 PandaBoard code +# +build -p $WORKSPACE/PandaBoardPkg/PandaBoardPkg.dsc -a ARM -t $TARGET_TOOLS -b $BUILD_TARGET $other_args + +for arg in "$@" +do + if [[ $arg == clean ]]; then + # no need to post process if we are doing a clean + exit + elif [[ $arg == cleanall ]]; then + make -C $EDK_TOOLS_PATH clean + make -C $WORKSPACE/PandaBoardPkg/Tools clean + exit + + fi +done + + +# +# Build the tool used to patch the FLASH image to work with the Panda board ROM +# +if [[ ! -e $GENERATE_IMAGE ]]; +then + make -C $WORKSPACE/PandaBoardPkg/Tools +fi + +echo Patching FD to work with PandaBoard ROM +rm -f $FLASH_BOOT + +# +# Ram starts at 0x80000000 +# OMAP TRM defines 0x80008000 as the entry point +# The reset vector is caught by the mask ROM in the OMAP so that is why this entry +# point looks so strange. +# OMAP TRM section 26.4.8 has Image header information. (missing in OMAP TRM) +# +$WORKSPACE/PandaBoardPkg/Tools/mkheader.pl $BUILD_ROOT/FV/PANDABOARD_EFI.fd $FLASH_BOOT +$GENERATE_IMAGE -p OMAP4 -i $WORKSPACE/PandaBoardPkg/ConfigurationHeader.dat -O $FLASH_BOOT +rm -f $WORKSPACE/PandaBoardPkg/tmp.bin +cp $FLASH_BOOT $BUILD_ROOT/FV/MLO + +echo Creating debugger scripts +process_debug_scripts $WORKSPACE/PandaBoardPkg/Debugger_scripts + diff --git a/PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch b/PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch new file mode 100644 index 000000000..15b4d7f9a --- /dev/null +++ b/PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch @@ -0,0 +1,35 @@ +From 9a22e1fed42e2ece74ae06546bc300bd0202e1ad Mon Sep 17 00:00:00 2001 +From: Olivier Deprez <o-deprez@ti.com> +Date: Fri, 1 Mar 2013 16:03:11 +0100 +Subject: [PATCH] Add call to early prepi init in ModuleEntryPoint + +omap4 requires an early call to an inner asm function to work +around a rom mask issue tied to dram initialization. +--- + ArmPlatformPkg/PrePi/ModuleEntryPoint.S | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S +index c0c20a9..66f0701 100755 +--- a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S ++++ b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S +@@ -24,12 +24,16 @@ + GCC_ASM_IMPORT(CEntryPoint) + GCC_ASM_IMPORT(ArmReadMpidr) + GCC_ASM_IMPORT(ArmPlatformStackSet) ++GCC_ASM_IMPORT(ArmPlatformPrePiBootAction) + GCC_ASM_EXPORT(_ModuleEntryPoint) + + StartupAddr: .word CEntryPoint + + + ASM_PFX(_ModuleEntryPoint): ++ // Perform early PrePi init ++ bl ASM_PFX(ArmPlatformPrePiBootAction) ++ + // Get ID of this CPU in Multicore system + bl ASM_PFX(ArmReadMpidr) + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) +-- +1.7.9.5 + diff --git a/PandaBoardPkg/patches/0001-fixes-sd-card-identification-on-panda.patch b/PandaBoardPkg/patches/0001-fixes-sd-card-identification-on-panda.patch new file mode 100644 index 000000000..a48c0e0f9 --- /dev/null +++ b/PandaBoardPkg/patches/0001-fixes-sd-card-identification-on-panda.patch @@ -0,0 +1,31 @@ +From 8d5bd220aee4a0b6e4c1dc9b3b54fe1b30c30e32 Mon Sep 17 00:00:00 2001 +From: Olivier Deprez <o-deprez@ti.com> +Date: Mon, 25 Jun 2012 11:06:31 +0200 +Subject: [PATCH] fixes sd card identification on panda + +It is observed with few SD cards that the protocol is hanging after issuing cmd5 and before cmd8. +Adding a small delay inbetween recovers and driver bring up is continuing without problem. +--- +EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 6 ++++++ + 1 files changed, 6 insertions(+), 0 deletions(-) + +diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c +index 47f4aeb..f8d2cc4 100644 +--- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c ++++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c +@@ -229,6 +229,12 @@ MmcIdentificationMode ( + + // Are we using SDIO ? + Status = MmcHost->SendCommand (MmcHost, MMC_CMD5, 0); ++ ++#if 1 // Added for Panda Board ++ /* It seems few SD cards need some time to recover from this command? */ ++ MicroSecondDelay(1000); ++#endif ++ + if (Status == EFI_SUCCESS) { + DEBUG((EFI_D_ERROR, "MmcIdentificationMode(MMC_CMD5): Error - SDIO not supported.\n")); + return EFI_UNSUPPORTED; +-- +1.7.4.1 + diff --git a/PandaBoardPkg/patches/0001-remove-ASSERT-because-serial-not-yet-initialized.patch b/PandaBoardPkg/patches/0001-remove-ASSERT-because-serial-not-yet-initialized.patch new file mode 100644 index 000000000..a2f76c7da --- /dev/null +++ b/PandaBoardPkg/patches/0001-remove-ASSERT-because-serial-not-yet-initialized.patch @@ -0,0 +1,27 @@ +From e6b3ca0f765545b94e74de75d67b3c830f354c70 Mon Sep 17 00:00:00 2001 +From: Olivier Deprez <o-deprez@ti.com> +Date: Thu, 9 Aug 2012 16:12:40 +0200 +Subject: [PATCH] remove ASSERT because serial not yet initialized + +In CEntryPoint, this ASSERT statement calls serial print functions when serial port has not been initialized yet +This is causing board hand on panda board. +--- +ArmPlatformPkg/PrePi/PrePi.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c +index 11396d1..05385cc 100755 +--- a/ArmPlatformPkg/PrePi/PrePi.c ++++ b/ArmPlatformPkg/PrePi/PrePi.c +@@ -209,7 +209,7 @@ CEntryPoint ( + } + + // Write VBAR - The Vector table must be 32-byte aligned +- ASSERT (((UINT32)PrePiVectorTable & ((1 << 5)-1)) == 0); ++ //ASSERT (((UINT32)PrePiVectorTable & ((1 << 5)-1)) == 0); + ArmWriteVBar ((UINT32)PrePiVectorTable); + + // If not primary Jump to Secondary Main +-- +1.7.0.4 + diff --git a/PandaBoardPkg/readme.txt b/PandaBoardPkg/readme.txt new file mode 100644 index 000000000..fee17d8fb --- /dev/null +++ b/PandaBoardPkg/readme.txt @@ -0,0 +1,179 @@ +A. Overview +=========== + +The Panda packages are hosted on http://gitorious.org/omap-romcode/omap-edk2 +This repository contains the latest developments concerning UEFI on PandaBoard. +Contact: o-deprez@ti.com + +Patches from omap-edk2 tree are regularly merged on need basis to +http://git.linaro.org/gitweb?p=arm/uefi/uefi-next.git by Linaro maintainer. + +B. Environment setup +==================== + + 1. Toolchain + ------------ + +PandaBoardPkg was built/tested using gcc version 4.6 on an Ubuntu Precise machine. + +For a list of possible toolchains visit: +http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=ArmPkg/Toolchain + + 2. Install necessary package + ---------------------------- + +Install uuid-dev package if not present already: + +sudo apt-get install uuid-dev + +C. Building +=========== + +Build information is found on uefi-next summary page: +http://git.linaro.org/gitweb?p=arm/uefi/uefi-next.git;a=summary + +After cloning the Linaro EDK2 tree and before compiling the PandaBoardPkg, +you must apply following patch to ArmPlatformPkg: + + git apply PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch + +Compilation is done with following command: + + cd PandaBoardPkg + ./build.sh -b RELEASE + +Note: the Debug version is compiled by invoking build.sh without parameters or: + + ./build.sh -b DEBUG + +D. Running EDK2 on Panda +======================== + + 1. UEFI Shell + ------------- + +If you just intend to see how UEFI boots up and make a try with the shell, you +can do a raw copy of the firmware image to an SD card (e.g. /dev/sdc): + + dd if=edk2/Build/PandaBoard/RELEASE_ARMGCC/FV/MLO of=/dev/sdc + +Open your favorite serial terminal e.g. + minicom -b 115200 -D /dev/ttyS0 -8 --color=on -w -o + +Plug serial and power cables. + +After few seconds, the following boot menu shall pop up: + + [1] Linux from SD + - VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0 + x19FC0)/uImage + - Initrd: VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x0000000 + 0,0x3F,0x19FC0)/uInitrd + - Arguments: console=ttyO2,115200n8 root=/dev/mmcblk0p2 earlyprintk root + wait ro fixrtc nocompcache vram=48M omapfb.vram=0:24M + - LoaderType: Linux kernel with global FDT + ----------------------- + Global FDT Config + - VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0 + x19FC0)/board.dtb + ----------------------- + [a] Boot Manager + [b] Shell + Start: + +From there, type 'b' for starting the shell. + + 2. Starting a Linux kernel + -------------------------- + +Check following page: http://releases.linaro.org/13.01/ubuntu/panda + +The easiest way is to get a full boot+filesystem image: +wget http://releases.linaro.org/13.01/ubuntu/boards/panda/panda-quantal_developer_20130128-58.img.gz + +Unzip and dd to an sd card as described on Linaro's website. + +Note: on OMAP, usage of earlyprintk statement on kernel command line looks incompatible with device tree. +Indeed early print routines use legacy machine type id to identify which uart module to use. +In case of device tree based boot the machine type passed to kernel entry by Bds is 0xFFFFFFFF, +which is unknown to earlyprintk routines and result in a hang. + +E. Boards tested +================ + +PandaBoard Rev EA2 - EBL and linux boot (PANDA_EDK2_080912) +PandaBoard Rev A3 - Shell and linux boot (PANDA_EDK2_030113) +PandaBoard ES Rev B1 - Shell (PANDA_EDK2_030113) + +Note: Panda ES did not fully boot up linaro 13.01 image thru UEFI (stuck at L2 cache init). + +F. chtool +========= + +The PandaBoardPkg/Tools directory contains a tool called chtool for creating +a Configuration Header block for use with the ROM Code boot sequence (in this port +it serves as configuration of OMAP DPLLs, system clocks, and initlization of external SDRAM). + +This tool is tracked in the following tree: git://gitorious.org/omap-romcode/chtool.git + +The version of chtool present in PandaBoardPkg is v0.4. + +G. History +========== + +03/01/2013 PANDA_EDK2_030113 + Added patch early PrePi init patch to ArmPlatformPkg + Board revision + Cleaned up Pad conf + Cleaned up setup clocks acceleration + Enable 1GB support + Add usb host support + Use null sd card's uuid + +01/28/2013 PANDA_EDK2_012813 + Created an edk2 top dir, moved packages in this dir + +11/21/2012 PANDA_EDK2_112112 + Add TWL6030 PMIC support + Update GPMC base address + Remove unused drivers (Flash, MMCHSDxe, InterruptDxe, SemihostFs) + Change PcdCoreCount to 2 + Change default boot type to Fdt + Update linux machine type to PandaBoard + +11/09/2012 PANDA_EDK2_110912 + Fix build.sh removing tmp.bin temporary file + Fix SerialPollGetControl with returning correct Control parm + Comment out Semihostfs from PandaBoardPkg.fdf + +08/09/2012 PANDA_EDK2_080912 + Boots linux "OMAP Ubuntu Core" kernel + +06/25/2012 PANDA_EDK2_062512 + First drop able to boot EBL + +H. Resources +============ + +Panda Board - TI OMAP4 +*http://pandaboard.org + +Beagle Board - TI OMAP3 +*http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=BeagleBoardPkg + +ArmPlatformPkg - Generic package for ARM platforms +*http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=ArmPlatformPkg + +I. To do/next steps +=================== + +-Enable Network +-Enable display/gui +-Add a CHMMCSD item in ROM's Configuration Header to accelerate image copy from SD to external RAM + +-DONE 03/01/2013 Enable USB host capability +-DONE 03/01/2013 Enable >512MiB external SDRAM +-DONE 03/01/2013 Clean PandaBoardLib for: detection of PandaBoard revision, pad conf, clocks speed up (if necessary) +-DONE 11/21/2012 Add PMIC management e.g. for SD card detection +-DONE 08/09/2012 Boot up linux kernel +-DONE 08/09/2012 Switch to linaro-uefi-2012.04 tag |