1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
|
#/** @file
# ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = ArmPkg
PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[LibraryClasses.common]
ArmLib|Include/Library/ArmLib.h
SemihostLib|Include/Library/Semihosting.h
UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
[Guids.common]
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
## ARM MPCore table
# Include/Guid/ArmMpCoreInfo.h
gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
[Ppis]
## Include/Ppi/ArmMpCoreInfo.h
gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
[Protocols.common]
gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }
[PcdsFeatureFlag.common]
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
# On ARM Architecture with the Security Extension, the address for the
# Vector Table can be mapped anywhere in the memory map. It means we can
# point the Exception Vector Table to its location in CpuDxe.
# By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)
gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
# it has been configured by the CPU DXE
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
# Define if the spin-table mechanism is used by the secondary cores when booting
# Linux (instead of PSCI)
gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
# This PCD will free the unallocated buffers if their size reach this threshold.
# We set the default value to 512MB.
gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
#
# ARM Secure Firmware PCDs
#
gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
#
# ARM Normal (or Non Secure) Firmware PCDs
#
gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
#
# ARM Hypervisor Firmware PCDs
#
gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
# Use ClusterId + CoreId to identify the PrimaryCore
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
# The Primary Core is ClusterId[0] & CoreId[0]
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
#
# ARM L2x0 PCDs
#
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
#
# BdsLib
#
gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
# Maximum file size for TFTP servers that do not support 'tsize' extension
gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
[PcdsFixedAtBuild.ARM]
#
# ARM Security Extension
#
# Secure Configuration Register
# - BIT0 : NS - Non Secure bit
# - BIT1 : IRQ Handler
# - BIT2 : FIQ Handler
# - BIT3 : EA - External Abort
# - BIT4 : FW - F bit writable
# - BIT5 : AW - A bit writable
# - BIT6 : nET - Not Early Termination
# - BIT7 : SCD - Secure Monitor Call Disable
# - BIT8 : HCE - Hyp Call enable
# - BIT9 : SIF - Secure Instruction Fetch
# 0x31 = NS | EA | FW
gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
# By default we do not do a transition to non-secure mode
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
# If the fixed FDT address is not available, then it should be loaded below the kernel.
# The recommendation from the Linux kernel is to have the FDT below 16KB.
# (see the kernel doc: Documentation/arm/Booting)
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
# The FDT blob must be loaded at a 64bit aligned address.
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
# Non Secure Access Control Register
# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
# - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
# - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
# 0xC00 = cp10 | cp11
gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
[PcdsFixedAtBuild.AARCH64]
#
# AArch64 Security Extension
#
# Secure Configuration Register
# - BIT0 : NS - Non Secure bit
# - BIT1 : IRQ Handler
# - BIT2 : FIQ Handler
# - BIT3 : EA - External Abort
# - BIT4 : FW - F bit writable
# - BIT5 : AW - A bit writable
# - BIT6 : nET - Not Early Termination
# - BIT7 : SCD - Secure Monitor Call Disable
# - BIT8 : HCE - Hyp Call enable
# - BIT9 : SIF - Secure Instruction Fetch
# - BIT10: RW - Register width control for lower exception levels
# - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
# - BIT12: TWI - Trap WFI
# - BIT13: TWE - Trap WFE
# 0x501 = NS | HCE | RW
gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
# By default we do transition to EL2 non-secure mode with Stack for EL2.
# Mode Description Bits
# NS EL2 SP2 all interrupts disabled = 0x3c9
# NS EL1 SP1 all interrupts disabled = 0x3c5
# Other modes include using SP0 or switching to Aarch32, but these are
# not currently supported.
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
# If the fixed FDT address is not available, then it should be loaded above the kernel.
# The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
# (see the kernel doc: Documentation/arm64/booting.txt)
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
# The FDT blob must be loaded at a 2MB aligned address.
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
#
# These PCDs are also defined as 'PcdsDynamic' to be redefined when using UEFI in a
# context of virtual machine.
#
[PcdsFixedAtBuild.common, PcdsDynamic.common]
# System Memory (DRAM): These PCDs define the region of in-built system memory
# Some platforms can get DRAM extensions, these additional regions will be declared
# to UEFI by ArmPlatformLib
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
#
# ARM Architectural Timer
#
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
# ARM Architectural Timer Interrupt(GIC PPI) numbers
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
#
# ARM Generic Interrupt Controller
#
gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
|
