diff options
| author | qhuang8 <qhuang8@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-05-19 03:30:22 +0000 |
|---|---|---|
| committer | qhuang8 <qhuang8@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-05-19 03:30:22 +0000 |
| commit | 24cd83a779ffb6786dabb8b34b59ab6ef1a8c24f (patch) | |
| tree | cff0aca6f87127ae43ae930685880967b72ffbf4 /PerformancePkg | |
| parent | 0ef42f8819ca33153b651e31f9f8c895b05cb323 (diff) | |
Remove unicode code in source code.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10515 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'PerformancePkg')
| -rw-r--r-- | PerformancePkg/Library/TscTimerLib/TscTimerLib.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/PerformancePkg/Library/TscTimerLib/TscTimerLib.c b/PerformancePkg/Library/TscTimerLib/TscTimerLib.c index d3e3e8ac6..4af635607 100644 --- a/PerformancePkg/Library/TscTimerLib/TscTimerLib.c +++ b/PerformancePkg/Library/TscTimerLib/TscTimerLib.c @@ -15,7 +15,7 @@ duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if
the processor core changes frequency. This is the architectural behavior moving forward.
- A Processor’s support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].
+ A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].
Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
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