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path: root/arch/arm/boot/dts/vexpress-v2p-ca15-tc2.dts
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/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 A7x3
 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
 *
 * This DTB describes the big (A15x2) cluster only!
 * Make sure that you have the following lines in your board.txt:
 *
 *     SCC: 0x018 0x00001FFF
 *     SCC: 0x700 0x00320003
 *
 * HBI-0249A
 */

/dts-v1/;

/memreserve/ 0xff000000 0x01000000;

/ {
	model = "V2P-CA15_CA7";
	arm,hbi = <0x249>;
	compatible = "arm,vexpress,v2p-ca15,tc2", "arm,vexpress,v2p-ca15", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	clusters {
		#address-cells = <1>;
		#size-cells = <0>;

		cluster0: cluster@0 {
			reg = <0>;
			cores {
				#address-cells = <1>;
				#size-cells = <0>;

				core0: core@0 {
					reg = <0>;
				};

				core1: core@1 {
					reg = <1>;
				};

			};
		};

		cluster1: cluster@1 {
			reg = <1>;
			cores {
				#address-cells = <1>;
				#size-cells = <0>;

				core2: core@0 {
					reg = <0>;
				};

				core3: core@1 {
					reg = <1>;
				};

				core4: core@2 {
					reg = <2>;
				};
			};
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			cluster = <&cluster0>;
			core = <&core0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			cluster = <&cluster0>;
			core = <&core1>;
			clock-frequency = <1000000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			cluster = <&cluster1>;
			core = <&core2>;
			clock-frequency = <800000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			cluster = <&cluster1>;
			core = <&core3>;
			clock-frequency = <800000000>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			cluster = <&cluster1>;
			core = <&core4>;
			clock-frequency = <800000000>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};

	wdt@2a490000 {
		compatible = "arm,sp805", "arm,primecell";
		reg = <0x2a490000 0x1000>;
		interrupts = <98>;
	};

	hdlcd@2b000000 {
		compatible = "arm,hdlcd";
		reg = <0x2b000000 0x1000>;
		interrupts = <0 85 4>;
		mode = "1024x768-16@60";
		arm,vexpress-osc = <5>;
		framebuffer = <0xff000000 0x01000000>;
	};

	memory-controller@2b0a0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0x2b0a0000 0x1000>;
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x2c001000 0x1000>,
		      <0x2c002000 0x1000>,
		      <0x2c004000 0x2000>,
		      <0x2c006000 0x2000>;
		interrupts = <1 9 0xf04>;

		gic-cpuif@0 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <0>;
			cpu = <&cpu0>;
		};
		gic-cpuif@1 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <1>;
			cpu = <&cpu1>;
		};
		gic-cpuif@2 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <2>;
			cpu = <&cpu2>;
		};

		gic-cpuif@3 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <3>;
			cpu = <&cpu3>;
		};

		gic-cpuif@4 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <4>;
			cpu = <&cpu4>;
		};
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0x7ffd0000 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
	};

	dma@7ffb0000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x7ff00000 0x1000>;
		interrupts = <0 92 4>,
			     <0 88 4>,
			     <0 89 4>,
			     <0 90 4>,
			     <0 91 4>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		broken-for-sched-clock = <1>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
	};

	motherboard {
		ranges = <0 0 0x08000000 0x04000000>,
			 <1 0 0x14000000 0x04000000>,
			 <2 0 0x18000000 0x04000000>,
			 <3 0 0x1c000000 0x04000000>,
			 <4 0 0x0c000000 0x04000000>,
			 <5 0 0x10000000 0x04000000>;

		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};
};

/include/ "vexpress-v2m-rs1.dtsi"