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* ARM Generic Interrupt Controller
ARM SMP cores are often associated with a GIC, providing per processor
interrupts (PPI), shared processor interrupts (SPI) and software
generated interrupts (SGI).
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
Secondary GICs are cascaded into the upward interrupt controller and do not
have PPIs or SGIs.
Main node required properties:
- compatible : should be one of:
"arm,cortex-a15-gic"
"arm,cortex-a9-gic"
"arm,cortex-a7-gic"
"arm,arm11mp-gic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 3.
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
interrupts.
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
range [0-15].
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
the interrupt is wired to that CPU. Only valid for PPI interrupts.
- reg : Specifies base physical address(s) and size of the GIC registers. The
first region is the GIC distributor register base and size. The 2nd region is
the GIC cpu interface register base and size.
Optional
- interrupts : Interrupt source of the parent interrupt controller on
secondary GICs, or VGIC maintainance interrupt on primary GIC (see
below).
- cpu-offset : per-cpu offset within the distributor and cpu interface
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
Example:
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
* GIC virtualization extensions (VGIC)
For ARM cores that support the virtualization extensions, additional
properties must be described (they only exist if the GIC is the
primary interrupt controller).
Required properties:
- reg : Additional regions specifying the base physical address and
size of the VGIC registers. The first additional region is the GIC
virtual interface control register base and size. The 2nd additional
region is the GIC virtual cpu interface register base and size.
- interrupts : VGIC maintainance interrupt.
Example:
interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
<0x2c002000 0x1000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
interrupts = <1 9 0xf04>;
};
* ARM Generic Interrupt Controller CPU Interfaces
ARM GIC device tree nodes contain subnodes representing its CPU interfaces.
The main properties required by CPU interface nodes are:
- compatible : "arm,gic-cpuif"
- cpuif-id : specifies the CPU IF HW identifier
- cpu : a phandle to the respective CPU node
Example:
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0x0 {
device_type = "cpu";
reg = <0x0>;
};
CPU1: cpu@0x1 {
device_type = "cpu";
reg = <0x1>;
};
CPU2: cpu@0x100 {
device_type = "cpu";
reg = <0x100>;
};
CPU3: cpu@0x101 {
device_type = "cpu";
reg = <0x101>;
};
};
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
gic-cpuif@0x0 {
compatible = "arm,gic-cpuif";
cpuif-id = <0x0>;
cpu = <&CPU0>;
};
gic-cpuif@0x1 {
compatible = "arm,gic-cpuif";
cpuif-id = <0x1>;
cpu = <&CPU1>;
};
gic-cpuif@0x2 {
compatible = "arm,gic-cpuif";
cpuif-id = <0x2>;
cpu = <&CPU2>;
};
gic-cpuif@0x3 {
compatible = "arm,gic-cpuif";
cpuif-id = <0x3>;
cpu = <&CPU3>;
};
};
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