From 41eae9c4945ef9a9029f604f77df1a0da401e051 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 14 Feb 2012 12:09:10 +0000 Subject: ARMv7: Do not clean the PTE if coherent page table walk is supported This patch adds a check for the ID_MMFR3[23:20] bits (coherent walk) and only cleans the D-cache corresponding to a PTE if coherent page table walks are not supported. Signed-off-by: Catalin Marinas --- arch/arm/mm/proc-v7-3level.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/mm/proc-v7-3level.S') diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 8de0f1dd154..6b306057be9 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -70,7 +70,9 @@ ENTRY(cpu_v7_set_pte_ext) tst r3, #1 << (55 - 32) @ L_PTE_DIRTY orreq r2, #L_PTE_RDONLY 1: strd r2, r3, [r0] - mcr p15, 0, r0, c7, c10, 1 @ flush_pte + mrc p15, 0, r3, c0, c1, 7 @ read ID_MMFR3 + tst r3, #0xf << 20 @ check the coherent walk bits + mcreq p15, 0, r0, c7, c10, 1 @ clean D-cache to PoU #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext) -- cgit v1.2.3