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/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPD_PRIVATE_H__
#define __SPD_PRIVATE_H__
#include <context.h>
#include <arch.h>
#include <psci.h>
#include <tsp.h>
/*******************************************************************************
* Secure Payload PM state information e.g. SP is suspended, uninitialised etc
******************************************************************************/
#define TSP_STATE_OFF 0
#define TSP_STATE_ON 1
#define TSP_STATE_SUSPEND 2
/*******************************************************************************
* Secure Payload execution state information i.e. aarch32 or aarch64
******************************************************************************/
#define TSP_AARCH32 MODE_RW_32
#define TSP_AARCH64 MODE_RW_64
/*******************************************************************************
* The SPD should know the type of Secure Payload.
******************************************************************************/
#define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP
#define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP
#define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP
/*******************************************************************************
* Secure Payload migrate type information as known to the SPD. We assume that
* the SPD is dealing with an MP Secure Payload.
******************************************************************************/
#define TSP_MIGRATE_INFO TSP_TYPE_MP
/*******************************************************************************
* Number of cpus that the present on this platform. TODO: Rely on a topology
* tree to determine this in the future to avoid assumptions about mpidr
* allocation
******************************************************************************/
#define TSPD_CORE_COUNT PLATFORM_CORE_COUNT
/*******************************************************************************
* Constants that allow assembler code to preserve callee-saved registers of the
* C runtime context while performing a security state switch.
******************************************************************************/
#define TSPD_C_RT_CTX_X19 0x0
#define TSPD_C_RT_CTX_X20 0x8
#define TSPD_C_RT_CTX_X21 0x10
#define TSPD_C_RT_CTX_X22 0x18
#define TSPD_C_RT_CTX_X23 0x20
#define TSPD_C_RT_CTX_X24 0x28
#define TSPD_C_RT_CTX_X25 0x30
#define TSPD_C_RT_CTX_X26 0x38
#define TSPD_C_RT_CTX_X27 0x40
#define TSPD_C_RT_CTX_X28 0x48
#define TSPD_C_RT_CTX_X29 0x50
#define TSPD_C_RT_CTX_X30 0x58
#define TSPD_C_RT_CTX_SIZE 0x60
#define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT)
#ifndef __ASSEMBLY__
/* AArch64 callee saved general purpose register context structure. */
DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
/*
* Compile time assertion to ensure that both the compiler and linker
* have the same double word aligned view of the size of the C runtime
* register context.
*/
CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs), \
assert_spd_c_rt_regs_size_mismatch);
/*******************************************************************************
* Structure which helps the SPD to maintain the per-cpu state of the SP.
* 'state' - collection of flags to track SP state e.g. on/off
* 'mpidr' - mpidr to associate a context with a cpu
* 'c_rt_ctx' - stack address to restore C runtime context from after returning
* from a synchronous entry into the SP.
* 'cpu_ctx' - space to maintain SP architectural state
******************************************************************************/
typedef struct {
uint32_t state;
uint64_t mpidr;
uint64_t c_rt_ctx;
cpu_context cpu_ctx;
} tsp_context;
/* TSPD power management handlers */
extern const spd_pm_ops tspd_pm;
/*******************************************************************************
* Function & Data prototypes
******************************************************************************/
extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
extern uint64_t tspd_synchronous_sp_entry(tsp_context *tsp_ctx);
extern void __dead2 tspd_synchronous_sp_exit(tsp_context *tsp_ctx, uint64_t ret);
extern int32_t tspd_init_secure_context(uint64_t entrypoint,
uint32_t rw,
uint64_t mpidr,
tsp_context *tsp_ctx);
extern tsp_context tspd_sp_context[TSPD_CORE_COUNT];
extern entry_info *tsp_entry_info;
#endif /*__ASSEMBLY__*/
#endif /* __SPD_PRIVATE_H__ */
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