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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-06-03 09:52:26 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-06-24 10:55:55 +0100
commit9edc89171f798495d4cb03b8e4cfa4b146ef1e1b (patch)
treef36677e43cd7429dab2d27972dd4c4a7e308cbd8
parente869310f67344cd1f2b531cff38fa8cb4d319d58 (diff)
downloadarm-trusted-firmware-9edc89171f798495d4cb03b8e4cfa4b146ef1e1b.tar.gz
fvp: Fix register name in 'plat_print_gic_regs' macro
The 'plat_print_gic_regs' macro was accessing the GICC_CTLR register using the GICD_CTLR offset. This still generates the right code in the end because GICD_CTLR == GICC_CTLR but this patch fixes it for the logic of the code. Change-Id: I7b17af50e587f07bec0e4c933e346088470c96f3
-rw-r--r--plat/fvp/include/plat_macros.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index bdd402d..d2e7cbc 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -47,7 +47,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
- ldr w2, [x0, #GICD_CTLR]
+ ldr w2, [x0, #GICC_CTLR]
sub sp, sp, #GIC_REG_SIZE
stp x1, x2, [sp] /* we store the gic registers as 64 bit */
adr x0, gic_regs