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authordanh-arm <dan.handley@arm.com>2014-06-24 16:48:18 +0100
committerdanh-arm <dan.handley@arm.com>2014-06-24 16:48:18 +0100
commit9d302ed22f6990cbb3f720bf42893b2a0d332b7d (patch)
tree35c6ebca3e0d0e888f0cb35f05b0f462a0817f53
parenta28daa0d6a00333193dbc12ff9e749390aa606d2 (diff)
parent9edc89171f798495d4cb03b8e4cfa4b146ef1e1b (diff)
downloadarm-trusted-firmware-9d302ed22f6990cbb3f720bf42893b2a0d332b7d.tar.gz
Merge pull request #150 from sandrine-bailleux/sb/fix-plat-print-gic-regs
fvp: Fix register name in 'plat_print_gic_regs' macro
-rw-r--r--plat/fvp/include/plat_macros.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index bdd402d..d2e7cbc 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -47,7 +47,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
- ldr w2, [x0, #GICD_CTLR]
+ ldr w2, [x0, #GICC_CTLR]
sub sp, sp, #GIC_REG_SIZE
stp x1, x2, [sp] /* we store the gic registers as 64 bit */
adr x0, gic_regs