diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2014-02-07 15:50:57 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-02-17 18:51:44 +0000 |
| commit | 65f0730ba34d5e22d3372cef76f048339d9c4588 (patch) | |
| tree | 0c16bd611d7a799605241d5bad451e925b0e7f44 | |
| parent | 74cbb839838d770064f0c83010609a134b22f2f8 (diff) | |
Fix spilled-over BL1 exception vector
The SynchronousExceptionA64 vector has gone beyond the 32-instruction
limit for individual exception vector. This patch splits and relocates
the exception handler so that it fits into the 32-instruction window.
Change-Id: Ic60c4fc3f09a1cb071d63ff0e58353ecaecbb62f
| -rw-r--r-- | bl1/aarch64/early_exceptions.S | 102 |
1 files changed, 55 insertions, 47 deletions
diff --git a/bl1/aarch64/early_exceptions.S b/bl1/aarch64/early_exceptions.S index bc3e946..ef47f9e 100644 --- a/bl1/aarch64/early_exceptions.S +++ b/bl1/aarch64/early_exceptions.S @@ -114,15 +114,66 @@ SynchronousExceptionA64: * here. * --------------------------------------------- */ + b process_exception + + .align 7 +IrqA64: + mov x0, #IRQ_AARCH64 + bl plat_report_exception + b IrqA64 + + .align 7 +FiqA64: + mov x0, #FIQ_AARCH64 + bl plat_report_exception + b FiqA64 + + .align 7 +SErrorA64: + mov x0, #SERROR_AARCH64 + bl plat_report_exception + b SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x0 - 0x180 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA32: + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + b SynchronousExceptionA32 + + .align 7 +IrqA32: + mov x0, #IRQ_AARCH32 + bl plat_report_exception + b IrqA32 + + .align 7 +FiqA32: + mov x0, #FIQ_AARCH32 + bl plat_report_exception + b FiqA32 + + .align 7 +SErrorA32: + mov x0, #SERROR_AARCH32 + bl plat_report_exception + b SErrorA32 + + .align 7 + +process_exception: sub sp, sp, #0x40 stp x0, x1, [sp, #0x0] stp x2, x3, [sp, #0x10] stp x4, x5, [sp, #0x20] stp x6, x7, [sp, #0x30] + mov x19, x0 mov x20, x1 mov x21, x2 - mov x0, #SYNC_EXCEPTION_AARCH64 bl plat_report_exception @@ -145,6 +196,7 @@ SynchronousExceptionA64: ubfx x0, x21, #MODE_EL_SHIFT, #2 cmp x0, #MODE_EL3 b.ne skip_mmu_teardown + /* --------------------------------------------- * If BL31 is to be executed in EL3 as well * then turn off the MMU so that it can perform @@ -167,55 +219,11 @@ skip_mmu_teardown: ldp x0, x1, [sp, #0x0] add sp, sp, #0x40 eret + panic: + wfi b panic - .align 7 -IrqA64: - mov x0, #IRQ_AARCH64 - bl plat_report_exception - b IrqA64 - .align 7 -FiqA64: - mov x0, #FIQ_AARCH64 - bl plat_report_exception - b FiqA64 - - .align 7 -SErrorA64: - mov x0, #SERROR_AARCH64 - bl plat_report_exception - b SErrorA64 - - /* ----------------------------------------------------- - * Lower EL using AArch32 : 0x0 - 0x180 - * ----------------------------------------------------- - */ - .align 7 -SynchronousExceptionA32: - mov x0, #SYNC_EXCEPTION_AARCH32 - bl plat_report_exception - b SynchronousExceptionA32 - - .align 7 -IrqA32: - mov x0, #IRQ_AARCH32 - bl plat_report_exception - b IrqA32 - - .align 7 -FiqA32: - mov x0, #FIQ_AARCH32 - bl plat_report_exception - b FiqA32 - - .align 7 -SErrorA32: - mov x0, #SERROR_AARCH32 - bl plat_report_exception - b SErrorA32 - - .align 7 /* ----------------------------------------------------- * BL1 redefines this function to print the fact that * BL2 has done its job and BL31 is about to be loaded. |