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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-01 14:34:59 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-06-04 15:37:36 +0100
commitfee39236d254fb3103d0ec9e1c82eeda95558fcc (patch)
tree76a89613578760382252d03c3345abb90aba39b5
parent4c54d5c53ffdd1f635983bd8e9711501880738e4 (diff)
downloadarm-trusted-firmware-fee39236d254fb3103d0ec9e1c82eeda95558fcc.tar.gz
juno: Fix the disable_mmu code
Remove the hard coding of all the MMU related registers with 0 and disable MMU by clearing the M and C bit in SCTLR_ELx. Also remove use of partially qualified asm helper functions. Change-Id: I383083f93a0a53143e58f146faf7755198f6a6ca
-rw-r--r--plat/juno/aarch64/plat_common.c17
1 files changed, 12 insertions, 5 deletions
diff --git a/plat/juno/aarch64/plat_common.c b/plat/juno/aarch64/plat_common.c
index 5de9e42..cd64598 100644
--- a/plat/juno/aarch64/plat_common.c
+++ b/plat/juno/aarch64/plat_common.c
@@ -89,11 +89,18 @@ void enable_mmu()
void disable_mmu(void)
{
- /* Zero out the MMU related registers */
- write_mair(0);
- write_tcr(0);
- write_ttbr0(0);
- write_sctlr(0);
+ unsigned long sctlr;
+ unsigned long current_el = read_current_el();
+
+ if (GET_EL(current_el) == MODE_EL3) {
+ sctlr = read_sctlr_el3();
+ sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
+ write_sctlr_el3(sctlr);
+ } else {
+ sctlr = read_sctlr_el1();
+ sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
+ write_sctlr_el1(sctlr);
+ }
/* Flush the caches */
dcsw_op_all(DCCISW);