aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAchin Gupta <achin.gupta@arm.com>2014-06-08 19:03:38 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-06-08 21:12:15 +0100
commitedb3f9209c15bb4ede32a9e74093c2fa3529441e (patch)
tree4f34046de32d4013f21e97e5ab01fee35c07a6f8
parentc6af727f3c974f7f656003aed6a9ac8d483b46c8 (diff)
downloadarm-trusted-firmware-edb3f9209c15bb4ede32a9e74093c2fa3529441e.tar.gz
Add support for selected Cortex-A57 r0p0 errata
This patch ensures that workarounds for erratas #806969, #813420 & #814670 that affect Cortex-A57 r0p0 as described in the errata notice document are implemented after every reset on each cpu. Change-Id: I37ee16bafa623c405197925c5a0e66811d4c50ae
-rw-r--r--include/lib/aarch64/arch.h21
-rw-r--r--lib/aarch64/cpu_helpers.S20
2 files changed, 33 insertions, 8 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index d89b4fe..01eb155 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -35,8 +35,12 @@
/*******************************************************************************
* MIDR bit definitions
******************************************************************************/
+#define MIDR_VAR_MASK 0xf
+#define MIDR_REV_MASK 0xf
#define MIDR_PN_MASK 0xfff
-#define MIDR_PN_SHIFT 0x4
+#define MIDR_VAR_SHIFT 20
+#define MIDR_REV_SHIFT 0
+#define MIDR_PN_SHIFT 4
#define MIDR_PN_AEM 0xd0f
#define MIDR_PN_A57 0xd07
#define MIDR_PN_A53 0xd03
@@ -68,6 +72,7 @@
* Implementation defined sysreg encodings
******************************************************************************/
#define CPUECTLR_EL1 S3_1_C15_C2_1
+#define CPUACTLR_EL1 S3_1_C15_C2_0
/*******************************************************************************
* Generic timer memory mapped registers & offsets
@@ -126,9 +131,6 @@
#define SCTLR_EXCEPTION_BITS (0x3 << 6)
#define SCTLR_EE_BIT (1 << 25)
-/* CPUECTLR definitions */
-#define CPUECTLR_SMP_BIT (1 << 6)
-
/* CPACR_El1 definitions */
#define CPACR_EL1_FPEN(x) (x << 20)
#define CPACR_EL1_FP_TRAP_EL0 0x1
@@ -395,6 +397,17 @@
#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
/*******************************************************************************
+ * Imp. Def. register defines.
+ ******************************************************************************/
+/* CPUECTLR definitions */
+#define CPUECTLR_SMP_BIT (1 << 6)
+
+/* A57 CPUACTLR definitions */
+#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
+#define CPUACTLR_DIS_DMB_NULL (1 << 58)
+#define CPUACTLR_DCC_AS_DCCI (1 << 44)
+
+/*******************************************************************************
* Definitions of register offsets and fields in the CNTCTLBase Frame of the
* system level implementation of the Generic Timer.
******************************************************************************/
diff --git a/lib/aarch64/cpu_helpers.S b/lib/aarch64/cpu_helpers.S
index b8be340..008d39d 100644
--- a/lib/aarch64/cpu_helpers.S
+++ b/lib/aarch64/cpu_helpers.S
@@ -40,15 +40,27 @@ func cpu_reset_handler
* ---------------------------------------------
*/
mrs x0, midr_el1
- lsr x0, x0, #MIDR_PN_SHIFT
- and x0, x0, #MIDR_PN_MASK
- cmp x0, #MIDR_PN_A57
+ lsr x1, x0, #MIDR_PN_SHIFT
+ and x1, x1, #MIDR_PN_MASK
+ cmp x1, #MIDR_PN_A57
b.eq a57_setup_begin
- cmp x0, #MIDR_PN_A53
+ cmp x1, #MIDR_PN_A53
b.eq smp_setup_begin
b smp_setup_end
a57_setup_begin:
+ ubfx x1, x0, #MIDR_VAR_SHIFT, #4
+ cmp x1, #0 // Major Revision 0
+ b.ne smp_setup_begin
+ ubfx x1, x0, #MIDR_REV_SHIFT, #4
+ cmp x1, #0 // Minor Revision 0
+ b.ne smp_setup_begin
+ mov x1, #CPUACTLR_NO_ALLOC_WBWA
+ orr x1, x1, #CPUACTLR_DIS_DMB_NULL
+ orr x1, x1, #CPUACTLR_DCC_AS_DCCI
+ mrs x0, CPUACTLR_EL1
+ orr x0, x0, x1
+ msr CPUACTLR_EL1, x0
mov x0, #0x082
msr s3_1_c11_c0_2, x0