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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-23 13:03:21 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-06-04 15:37:36 +0100
commit8a40778c7509c15f3251950f42e1ea7162b4ed9c (patch)
tree4afdeb6c171cf7fc4b1fdb83260123927fdb0ab8
parentb78f25bf3d6761b9da0dba441c3e6d9ae651f7ff (diff)
downloadarm-trusted-firmware-8a40778c7509c15f3251950f42e1ea7162b4ed9c.tar.gz
Enable Debug and SError exceptions on warm boot path
Enable Debug and SError exceptions: - when receiving an SMC; - when a CPU is physically powered up (upon resumption from suspend or in response to a PSCI cpu_on call) Change-Id: I7e5613e34034be6ed68ec9e2aef4de66aa5ac65e
-rw-r--r--bl31/aarch64/runtime_exceptions.S6
-rw-r--r--services/std_svc/psci/psci_entry.S6
2 files changed, 12 insertions, 0 deletions
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index a11cd71..51575a6 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -44,6 +44,12 @@
* -----------------------------------------------------
*/
.macro handle_sync_exception
+ /* ---------------------------------------------
+ * Enable Debug and SError interrupts
+ * ---------------------------------------------
+ */
+ msr daifclr, #(DAIF_ABT_BIT | DAIF_DBG_BIT)
+
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
mrs x30, esr_el3
ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S
index bc8d900..3954ab1 100644
--- a/services/std_svc/psci/psci_entry.S
+++ b/services/std_svc/psci/psci_entry.S
@@ -71,6 +71,12 @@ psci_aff_common_finish_entry:
isb
/* ---------------------------------------------
+ * Enable Debug and SError interrupts
+ * ---------------------------------------------
+ */
+ msr daifclr, #(DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+ /* ---------------------------------------------
* Use SP_EL0 for the C runtime stack.
* ---------------------------------------------
*/