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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-27 13:06:57 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-06-05 17:39:40 +0100
commit0897d02c06d2c4d770f60379601ca2feab01115d (patch)
treeee36cd92cd78fa3f33d32ba599c89b125da019ee
parent0babea93d314159314c7d7094436b436d3261f2d (diff)
downloadarm-trusted-firmware-0897d02c06d2c4d770f60379601ca2feab01115d.tar.gz
juno: Define the extents of all bootloader images
Define: - Extents of BL1 RO and RW sections - BL2 limit address - BL3-1 limit address - BL3-2 limit address Change-Id: Id86243c4d5b1f769a9b0d5a639665c3cb5e14aee
-rw-r--r--plat/juno/platform.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/plat/juno/platform.h b/plat/juno/platform.h
index 97505de..927efd3 100644
--- a/plat/juno/platform.h
+++ b/plat/juno/platform.h
@@ -171,16 +171,27 @@
#define SYS_LED_EL_SHIFT 0x1
#define SYS_LED_EC_SHIFT 0x3
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
+ * addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE (FLASH_BASE + BL1_ROM_BYPASS_OFFSET)
+#define BL1_RO_LIMIT (FLASH_BASE + FLASH_SIZE)
+#define BL1_RW_BASE TZRAM_BASE
+#define BL1_RW_LIMIT BL31_BASE
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xd000)
+#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* BL3-1 specific defines.
******************************************************************************/
#define BL31_BASE (TZRAM_BASE + 0x8000)
+#define BL31_LIMIT BL32_BASE
/*******************************************************************************
* BL3-0 specific defines.
@@ -195,6 +206,7 @@
#define TSP_SEC_MEM_BASE TZRAM_BASE
#define TSP_SEC_MEM_SIZE TZRAM_SIZE
#define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000)
+#define BL32_LIMIT BL2_BASE
/*******************************************************************************
* Platform specific page table and MMU setup constants