juno: Update memory map and use generic MMU code

Signed-off-by: Jon Medhurst <tixy@linaro.org>

4 files changed, 64 insertions, 85 deletions

diff --git a/plat/juno/aarch64/plat_common.c b/plat/juno/aarch64/plat_common.c
index 8fed957..1adea5b 100644
--- a/plat/juno/aarch64/plat_common.c
+++ b/plat/juno/aarch64/plat_common.c
@@ -28,37 +28,16 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <string.h>
-#include <assert.h>
 #include <arch_helpers.h>
 #include <platform.h>
-#include <bl_common.h>
-/* Included only for error codes */
-#include <psci.h>
+#include <xlat_tables.h>
+
 
 unsigned char platform_normal_stacks[PLATFORM_STACK_SIZE][PLATFORM_CORE_COUNT]
 __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
 		section("tzfw_normal_stacks")));
 
-/*******************************************************************************
- * This array holds the characteristics of the differences between the three
- * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
- * boot at each boot stage by the primary before enabling the MMU (to allow cci
- * configuration) & used thereafter. Each BL will have its own copy to allow
- * independent operation.
- ******************************************************************************/
-static unsigned long platform_config[CONFIG_LIMIT];
-
-/*******************************************************************************
- * An internal global pointer of the level 1 translation tables which should not
- * change once setup by the primary cpu during a cold boot.
- *******************************************************************************/
-unsigned long l1_xlation_table __aligned(PLATFORM_CACHE_LINE_SIZE)
-__attribute__ ((section("tzfw_coherent_mem")));
-
-/*******************************************************************************
- * Enable the MMU assuming that the pagetables have already been created
- *******************************************************************************/
+
 void enable_mmu()
 {
 	unsigned long mair, tcr, ttbr, sctlr;
@@ -112,36 +91,43 @@ void disable_mmu(void)
 	return;
 }
 
-/*******************************************************************************
- * Setup the pagetables as per the platform memory map & initialize the mmu
- *******************************************************************************/
+static const mmap_region mmap[] = {
+	{ TZROM_BASE,		TZROM_SIZE,		MT_MEMORY | MT_RO | MT_SECURE },
+//	{ TZRAM_BASE,		TZRAM_SIZE,		MT_MEMORY | MT_RW | MT_SECURE },  /* configure_mmu() meminfo arg sets subset of this */
+	{ TZDRAM_BASE,		TZDRAM_SIZE,		MT_MEMORY | MT_RW | MT_SECURE },
+	{ FLASH_BASE,		FLASH_SIZE,		MT_MEMORY | MT_RO | MT_SECURE },
+	{ EMMC_BASE,		EMMC_SIZE,		MT_MEMORY | MT_RO | MT_SECURE },
+	{ PSRAM_BASE,		PSRAM_SIZE,		MT_MEMORY | MT_RW | MT_SECURE }, /* Used for 'TZDRAM' */
+	{ IOFPGA_BASE,		IOFPGA_SIZE,		MT_DEVICE | MT_RW | MT_SECURE },
+//	{ NSROM_BASE,		NSROM_SIZE,		MT_MEMORY | MT_RW | MT_NS },	 /* Eats a page table so leave it out for now */
+	{ DEVICE0_BASE,		DEVICE0_SIZE,		MT_DEVICE | MT_RW | MT_SECURE },
+	{ NSRAM_BASE,		NSRAM_SIZE,		MT_MEMORY | MT_RW | MT_NS },
+	{ DEVICE1_BASE,		DEVICE1_SIZE,		MT_DEVICE | MT_RW | MT_SECURE },
+	{ DRAM_BASE,		DRAM_SIZE,		MT_MEMORY | MT_RW | MT_NS },
+	{0}
+};
+
 void configure_mmu(meminfo *mem_layout,
 		   unsigned long ro_start,
 		   unsigned long ro_limit,
 		   unsigned long coh_start,
 		   unsigned long coh_limit)
 {
-	assert(IS_PAGE_ALIGNED(ro_start));
-	assert(IS_PAGE_ALIGNED(ro_limit));
-	assert(IS_PAGE_ALIGNED(coh_start));
-	assert(IS_PAGE_ALIGNED(coh_limit));
-
-	l1_xlation_table = fill_xlation_tables(mem_layout,
-					       ro_start,
-					       ro_limit,
-					       coh_start,
-					       coh_limit);
+	mmap_add_region(mem_layout->total_base, mem_layout->total_size,
+				MT_MEMORY | MT_RW | MT_SECURE);
+	mmap_add_region(ro_start, ro_limit - ro_start,
+				MT_MEMORY | MT_RO | MT_SECURE);
+	mmap_add_region(coh_start, coh_limit - coh_start,
+				MT_DEVICE | MT_RW | MT_SECURE);
+
+	mmap_add(mmap);
+
+	init_xlat_tables();
+
 	enable_mmu();
 	return;
 }
 
-/* Simple routine which returns a configuration variable value */
-unsigned long platform_get_cfgvar(unsigned int var_id)
-{
-	assert(var_id < CONFIG_LIMIT);
-	return platform_config[var_id];
-}
-
 unsigned long plat_get_ns_image_entrypoint(void)
 {
 	return NS_IMAGE_OFFSET;
diff --git a/plat/juno/plat_io_storage.c b/plat/juno/plat_io_storage.c
index 77520f5..4c3ff1d 100644
--- a/plat/juno/plat_io_storage.c
+++ b/plat/juno/plat_io_storage.c
@@ -54,8 +54,8 @@ static void *const memmap_init_params;
 static io_dev_handle memmap_dev_handle;
 
 static io_block_spec fip_block_spec = {
-	.offset = FLASH0_BASE,
-	.length = FLASH0_SIZE
+	.offset = FLASH_BASE,
+	.length = FLASH_SIZE
 };
 
 static io_file_spec bl2_file_spec = {
diff --git a/plat/juno/platform.h b/plat/juno/platform.h
index 9265c2b..3656a51 100644
--- a/plat/juno/platform.h
+++ b/plat/juno/platform.h
@@ -83,46 +83,45 @@
  * Platform memory map related constants
  ******************************************************************************/
 #define TZROM_BASE		0x00000000
-#define TZROM_SIZE		0x04000000
+#define TZROM_SIZE		0x00010000
 
 #define TZRAM_BASE		0x04000000
-#define TZRAM_SIZE		0x40000
+#define TZRAM_SIZE		0x00040000
 
-#define FLASH0_BASE		0x08000000
-#define FLASH0_SIZE		TZROM_SIZE
+#define FLASH_BASE		0x08000000
+#define FLASH_SIZE		0x04000000
 
-#define FLASH1_BASE		0x0c000000
-#define FLASH1_SIZE		0x04000000
+#define EMMC_BASE		0x0c000000
+#define EMMC_SIZE		0x04000000
 
 #define PSRAM_BASE		0x14000000
-#define PSRAM_SIZE		0x04000000
+#define PSRAM_SIZE		0x02000000
 
-#define VRAM_BASE		0x18000000
-#define VRAM_SIZE		0x02000000
+#define IOFPGA_BASE		0x1c000000
+#define IOFPGA_SIZE		0x03000000
 
-/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE		0x1a000000
-#define DEVICE0_SIZE		0x12200000
+#define NSROM_BASE		0x1f000000
+#define NSROM_SIZE		0x00001000
 
-#define DEVICE1_BASE		0x2f000000
-#define DEVICE1_SIZE		0x200000
+/* Following covers Columbus Peripherals excluding NSROM and NSRAM */
+#define DEVICE0_BASE		0x20000000
+#define DEVICE0_SIZE		0x0e000000
 
 #define NSRAM_BASE		0x2e000000
-#define NSRAM_SIZE		0x10000
+#define NSRAM_SIZE		0x00008000
 
-/* Location of trusted dram on the base fvp */
-#define TZDRAM_BASE		0x06000000
-#define TZDRAM_SIZE		0x02000000
+/* Following covers Juno Peripherals and PCIe expansion area */
+#define DEVICE1_BASE		0x40000000
+#define DEVICE1_SIZE		0x40000000
+
+/* Use PSRAM for 'TZDRAM' */
+#define TZDRAM_BASE		PSRAM_BASE
+#define TZDRAM_SIZE		PSRAM_SIZE
 #define MBOX_OFF		0x1000
 #define AFFMAP_OFF		0x1200
 
-#define DRAM_BASE              0x80000000ull
-#define DRAM_SIZE              0x80000000ull
-
-#define PCIE_EXP_BASE		0x40000000
-#define TZRNG_BASE		0x7fe60000
-#define TZNVCTR_BASE		0x7fe70000
-#define TZROOTKEY_BASE		0x7fe80000
+#define DRAM_BASE		0x80000000
+#define DRAM_SIZE		0x80000000
 
 /* Memory mapped Generic timer interfaces  */
 #define SYS_CNTCTL_BASE		0x2a430000
@@ -142,7 +141,7 @@
 /*******************************************************************************
  * BL2 specific defines.
  ******************************************************************************/
-#define BL2_BASE			0x0402D000
+#define BL2_BASE			0x0402a000
 
 /*******************************************************************************
  * BL3-1 specific defines.
@@ -152,20 +151,10 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define EL3_ADDR_SPACE_SIZE		(1ull << 32)
-#define EL3_NUM_PAGETABLES		2
-#define EL3_TROM_PAGETABLE		0
-#define EL3_TRAM_PAGETABLE		1
-
 #define ADDR_SPACE_SIZE			(1ull << 32)
+#define MAX_XLAT_TABLES			5
+#define MAX_MMAP_REGIONS		16
 
-#define NUM_L2_PAGETABLES		2
-#define GB1_L2_PAGETABLE		0
-#define GB2_L2_PAGETABLE		1
-
-#define NUM_L3_PAGETABLES		2
-#define TZRAM_PAGETABLE			0
-#define NSRAM_PAGETABLE			1
 
 /*******************************************************************************
  * CCI-400 related constants
diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk
index 6924e81..16c7f76 100644
--- a/plat/juno/platform.mk
+++ b/plat/juno/platform.mk
@@ -34,6 +34,7 @@ PLAT_INCLUDES		:=	-Idrivers/arm/interconnect/cci-400	\
 
 PLAT_BL1_C_VPATH	:=	drivers/arm/interconnect/cci-400	\
 				drivers/arm/peripherals/pl011		\
+				lib/arch/${ARCH}			\
 				lib/semihosting				\
 				lib/stdlib				\
 				drivers/io
@@ -42,6 +43,7 @@ PLAT_BL1_S_VPATH	:=	lib/semihosting/${ARCH}
 
 PLAT_BL2_C_VPATH	:=	drivers/arm/interconnect/cci-400	\
 				drivers/arm/peripherals/pl011		\
+				lib/arch/${ARCH}			\
 				lib/stdlib				\
 				lib/semihosting				\
 				drivers/io
@@ -50,6 +52,7 @@ PLAT_BL2_S_VPATH	:=	lib/semihosting/${ARCH}
 
 PLAT_BL31_C_VPATH	:=	drivers/arm/interconnect/cci-400	\
 				drivers/arm/peripherals/pl011		\
+				lib/arch/${ARCH}			\
 				lib/semihosting				\
 				lib/stdlib				\
 				drivers/power				\
@@ -65,7 +68,8 @@ PLAT_BL_COMMON_SOURCES	:=	semihosting_call.S			\
 				plat_io_storage.c			\
 				io_semihosting.c			\
 				io_fip.c				\
-				io_memmap.c
+				io_memmap.c				\
+				xlat_tables.c
 
 BL1_SOURCES		+=	bl1_plat_setup.c			\
 				bl1_plat_helpers.S			\