diff options
| author | Jon Medhurst <tixy@linaro.org> | 2014-01-28 03:06:43 +0000 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-03-12 16:03:32 +0000 |
| commit | 0be17c44cad9e427a066197830f37c8d9c62987e (patch) | |
| tree | 2f4251cff073b6f670c11994ace20330c31b8f36 | |
| parent | 29dfa23b0f7fcc9ce22107974d45612b26754c76 (diff) | |
juno: Initialise NIC-400
Signed-off-by: Jon Medhurst <tixy@linaro.org>
| -rw-r--r-- | plat/juno/bl1_plat_setup.c | 36 | ||||
| -rw-r--r-- | plat/juno/platform.h | 4 |
2 files changed, 39 insertions, 1 deletions
diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c index 995cd7f..6873ed8 100644 --- a/plat/juno/bl1_plat_setup.c +++ b/plat/juno/bl1_plat_setup.c @@ -102,12 +102,48 @@ void bl1_early_platform_setup(void) console_init(PL011_UART0_BASE); } + +#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) + +#define SOC_NIC400_S5_BIT_UART1 (1u << 12) + +static void init_nic400(void) +{ + /* + * NIC-400 Access Control Initialization + * + * Define access privileges by setting each corresponding bit to: + * 0 = Secure access only + * 1 = Non-secure access allowed + */ + + /* + * Allow non-secure access to some SOC regions, excluding UART1, which + * remains secure. Note: This is a NIC-400 device on the SOC + */ + mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(0), ~0); // USB_EHCI + mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(1), ~0); // TLX_MASTER + mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(2), ~0); // USB_OHCI + mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(3), ~0); + mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(4), ~0); // PCIe + mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(5), ~SOC_NIC400_S5_BIT_UART1); + + /* + * Allow non-secure access to some CSS regions. + * Note: This is a NIC-400 device on the CSS + */ + mmio_write_32(CSS_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(8), ~0); +} + + /******************************************************************************* * Function which will perform any remaining platform-specific setup that can * occur after the MMU and data cache have been enabled. ******************************************************************************/ void bl1_platform_setup(void) { + init_nic400(); + /* Initialise the IO layer and register platform IO devices */ io_setup(); diff --git a/plat/juno/platform.h b/plat/juno/platform.h index a1abccc..27b3269 100644 --- a/plat/juno/platform.h +++ b/plat/juno/platform.h @@ -106,9 +106,10 @@ #define NSROM_BASE 0x1f000000 #define NSROM_SIZE 0x00001000 -/* Following covers Columbus Peripherals excluding NSROM and NSRAM */ +/* Following covers Columbus Peripherals excluding NSROM and NSRAM */ #define DEVICE0_BASE 0x20000000 #define DEVICE0_SIZE 0x0e000000 +#define CSS_NIC400_BASE 0x2a000000 #define NSRAM_BASE 0x2e000000 #define NSRAM_SIZE 0x00008000 @@ -116,6 +117,7 @@ /* Following covers Juno Peripherals and PCIe expansion area */ #define DEVICE1_BASE 0x40000000 #define DEVICE1_SIZE 0x40000000 +#define SOC_NIC400_BASE 0x7fd00000 #define DRAM_BASE 0x80000000 #define DRAM_SIZE 0x80000000 |