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path: root/daemon/events-Cortex-A17.xml
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  <counter_set name="ARMv7_Cortex_A17_cnt" count="6"/>
  <category name="Cortex-A17" counter_set="ARMv7_Cortex_A17_cnt" per_cpu="yes" supports_event_based_sampling="yes">
    <event counter="ARMv7_Cortex_A17_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache. Includes the speculative linefills in the count."/>
    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB. Includes the speculative requests in the count."/>
    <event event="0x03" title="Cache" name="Data refill" description="Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache. Counts the number of allocations performed in the Data Cache because of a read or a write."/>
    <event event="0x04" title="Cache" name="Data access" description="Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache. This includes speculative reads."/>
    <event event="0x05" title="Cache" name="Data TLB refill" description="Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB. This does not include micro TLB misses because of PLD, PLI, CP15 Cache operation by MVA and CP15 VA to PA operations."/>
    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
    <event event="0x09" title="Exception" name="Taken" description="Exception taken. Counts the number of exceptions architecturally taken."/>
    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Change to ContextID retired. Counts the number of instructions architecturally executed writing into the ContextID register."/>
    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted. Counts the number of mispredicted or not-predicted branches executed. This includes the branches which are flushed because of a previous load/store which aborts late."/>
    <event event="0x12" title="Branch" name="Potential prediction" description="Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor. This includes the branches which are flushed because of a previous load/store which aborts late."/>
    <event event="0x13" title="Memory" name="Memory access" description="Level 1 data memory access"/>
    <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
    <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache eviction"/>
    <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
    <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
    <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache write-back. Data transfers made as a result of a coherency request from the Level 2 caches to outside of the Level 1 and Level 2 caches are not counted. Write-backs made as a result of CP15 cache maintenance operations are counted."/>
    <event event="0x19" title="Bus" name="Access" description="Bus accesses. Single transfer bus accesses on either of the ACE read or write channels might increment twice in one cycle if both the read and write channels are active simultaneously.Operations that utilise the bus that do not explicitly transfer data, such as barrier or coherency operations are counted as bus accesses."/>
    <event event="0x1b" title="Instruction" name="Speculative" description="Instructions speculatively executed"/>
    <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table register (TTBR0 or TTBR1)"/>
    <event event="0x1d" title="Bus" name="Cycle" description="Bus cycle"/>
    <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
    <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
    <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
    <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
    <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache write-back - Victim"/>
    <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache write-back - Cleaning and coherency"/>
    <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
    <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal Cacheable"/>
    <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not Cacheable"/>
    <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
    <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
    <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
    <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
    <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
    <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
    <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
    <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
    <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
    <event event="0x6f" title="Intrinsic" name="STREX" description="Exclusive instruction speculatively executed - STREX"/>
    <event event="0x70" title="Instruction" name="Load" description="Load instruction speculatively executed"/>
    <event event="0x71" title="Instruction" name="Store" description="Store instruction speculatively executed"/>
    <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
    <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Data processing"/>
    <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
    <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
    <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
    <event event="0x78" title="Branch" name="Immediate" description="Branch speculatively executed - Immediate branch"/>
    <event event="0x79" title="Procedure" name="Return" description="Branch speculatively executed - Procedure return"/>
    <event event="0x7a" title="Branch" name="Indirect" description="Branch speculatively executed - Indirect branch"/>
    <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
    <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
    <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
    <event event="0x81" title="Exception" name="Undefined" description="Exception taken - Undefined Instruction"/>
    <event event="0x8a" title="Exception" name="Hypervisor call" description="Exception taken - Hypervisor Call"/>
    <event event="0xc0" title="Instruction" name="Stalled Linefill" description="Instruction side stalled due to a linefill"/>
    <event event="0xc1" title="Instruction" name="Stalled Page Table Walk" description="Instruction side stalled due to a translation table walk"/>
    <event event="0xc2" title="Cache" name="4 Ways Read" description="Number of set of 4 ways read in the instruction cache - Tag RAM"/>
    <event event="0xc3" title="Cache" name="Ways Read" description="Number of ways read in the instruction cache - Data RAM"/>
    <event event="0xc4" title="Cache" name="BATC Read" description="Number of ways read in the instruction BTAC RAM"/>
    <event event="0xca" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local Cortex-A17 cluster, rather than accessing the L2 cache or issuing an external read. It increments on each transaction, rather than on each beat of data."/>
    <event event="0xd3" title="Slots" name="Load-Store Unit" description="Duration during which all slots in the Load-Store Unit are busy"/>
    <event event="0xd8" title="Slots" name="Load-Store Issue Queue" description="Duration during which all slots in the Load-Store Issue queue are busy"/>
    <event event="0xd9" title="Slots" name="Data Processing Issue Queue" description="Duration during which all slots in the Data Processing issue queue are busy"/>
    <event event="0xda" title="Slots" name="Data Engine Issue Queue" description="Duration during which all slots in the Data Engine issue queue are busy"/>
    <event event="0xdb" title="NEON" name="Flush" description="Number of NEON instruction which fail their condition code and lead to a flush of the DE pipe"/>
    <event event="0xdc" title="Hypervisor" name="Traps" description="Number of Trap to hypervisor"/>
    <event event="0xde" title="PTM" name="EXTOUT 0" description="PTM EXTOUT 0"/>
    <event event="0xdf" title="PTM" name="EXTOUT 1" description="PTM EXTOUT 1"/>
    <event event="0xe0" title="MMU" name="Table Walk" description="Duration during which the MMU handle a translation table walk"/>
    <event event="0xe1" title="MMU" name="Stage1 Table Walk" description="Duration during which the MMU handle a Stage1 translation table walk"/>
    <event event="0xe2" title="MMU" name="Stage2 Table Walk" description="Duration during which the MMU handle a Stage2 translation table walk"/>
    <event event="0xe3" title="MMU" name="LSU Table Walk" description="Duration during which the MMU handle a translation table walk requested by the Load Store Unit"/>
    <event event="0xe4" title="MMU" name="Instruction Table Walk" description="Duration during which the MMU handle a translation table walk requested by the Instruction side"/>
    <event event="0xe5" title="MMU" name="Preload Table Walk" description="Duration during which the MMU handle a translation table walk requested by a Preload instruction or Prefetch request"/>
    <event event="0xe6" title="MMU" name="cp15 Table Walk" description="Duration during which the MMU handle a translation table walk requested by a CP15 operation (maintenance by MVA and VA-to-PA operation)"/>
    <event event="0xe7" title="Cache" name="L1 PLD TLB refill" description="Level 1 PLD TLB refill"/>
    <event event="0xe8" title="Cache" name="L1 CP15 TLB refill" description="Level 1 CP15 TLB refill"/>
    <event event="0xe9" title="Cache" name="L1 TLB flush" description="Level 1 TLB flush"/>
    <event event="0xea" title="Cache" name="L2 TLB access" description="Level 2 TLB access"/>
    <event event="0xeb" title="Cache" name="L2 TLB miss" description="Level 2 TLB miss"/>
  </category>