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-rw-r--r--daemon/events-L2C-310.xml30
1 files changed, 15 insertions, 15 deletions
diff --git a/daemon/events-L2C-310.xml b/daemon/events-L2C-310.xml
index 4da4d1d..923fb90 100644
--- a/daemon/events-L2C-310.xml
+++ b/daemon/events-L2C-310.xml
@@ -1,18 +1,18 @@
<counter_set name="L2C-310_cnt" count="2"/>
<category name="L2C-310" counter_set="L2C-310_cnt" per_cpu="no">
- <event event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
- <event event="0x2" title="L2 Cache" name="DRH" description="Data read hit"/>
- <event event="0x3" title="L2 Cache" name="DRREQ" description="Data read request"/>
- <event event="0x4" title="L2 Cache" name="DWHIT" description="Data write hit"/>
- <event event="0x5" title="L2 Cache" name="DWREQ" description="Data write request"/>
- <event event="0x6" title="L2 Cache" name="DWTREQ" description="Data write request with write-through attribute"/>
- <event event="0x7" title="L2 Cache" name="IRHIT" description="Instruction read hit"/>
- <event event="0x8" title="L2 Cache" name="IRREQ" description="Instruction read request"/>
- <event event="0x9" title="L2 Cache" name="WA" description="Write allocate"/>
- <event event="0xa" title="L2 Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
- <event event="0xb" title="L2 Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>
- <event event="0xc" title="L2 Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>
- <event event="0xd" title="L2 Cache" name="SRRCVD" description="Speculative read received"/>
- <event event="0xe" title="L2 Cache" name="SRCONF" description="Speculative read confirmed"/>
- <event event="0xf" title="L2 Cache" name="EPFRCVD" description="Prefetch hint received"/>
+ <event event="0x1" title="L2 Cache" name="CastOUT" description="Eviction, CastOUT, of a line from the L2 cache"/>
+ <event event="0x2" title="L2 Cache" name="Data Read Hit" description="Data read hit in the L2 cache"/>
+ <event event="0x3" title="L2 Cache" name="Data Read Request" description="Data read lookup to the L2 cache. Subsequently results in a hit or miss"/>
+ <event event="0x4" title="L2 Cache" name="Data Write Hit" description="Data write hit in the L2 cache"/>
+ <event event="0x5" title="L2 Cache" name="Data Write Request" description="Data write lookup to the L2 cache. Subsequently results in a hit or miss"/>
+ <event event="0x6" title="L2 Cache" name="Data Write-Through Request" description="Data write lookup to the L2 cache with Write-Through attribute. Subsequently results in a hit or miss"/>
+ <event event="0x7" title="L2 Cache" name="Instruction Read Hit" description="Instruction read hit in the L2 cache"/>
+ <event event="0x8" title="L2 Cache" name="Instruction Read Request" description="Instruction read lookup to the L2 cache. Subsequently results in a hit or miss"/>
+ <event event="0x9" title="L2 Cache" name="Write Allocate Miss" description="Allocation into the L2 cache caused by a write, with Write-Allocate attribute, miss"/>
+ <event event="0xa" title="L2 Cache" name="Internal Prefetch Allocate" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
+ <event event="0xb" title="L2 Cache" name="Prefitch Hit" description="Prefetch hint hits in the L2 cache"/>
+ <event event="0xc" title="L2 Cache" name="Prefitch Allocate" description="Prefetch hint allocated into the L2 cache"/>
+ <event event="0xd" title="L2 Cache" name="Speculative Read Received" description="Speculative read received"/>
+ <event event="0xe" title="L2 Cache" name="Speculative Read Confirmed" description="Speculative read confirmed"/>
+ <event event="0xf" title="L2 Cache" name="Prefetch Hint Received" description="Prefetch hint received"/>
</category>