diff options
| -rw-r--r-- | daemon/PerfDriver.cpp | 1 | ||||
| -rw-r--r-- | daemon/defaults.xml | 5 | ||||
| -rw-r--r-- | daemon/events-Cortex-A72.xml | 87 | ||||
| -rw-r--r-- | driver/gator.h | 1 | ||||
| -rw-r--r-- | driver/gator_main.c | 7 |
5 files changed, 101 insertions, 0 deletions
diff --git a/daemon/PerfDriver.cpp b/daemon/PerfDriver.cpp index ee90284..42cbff6 100644 --- a/daemon/PerfDriver.cpp +++ b/daemon/PerfDriver.cpp @@ -57,6 +57,7 @@ static const struct gator_cpu gator_cpus[] = { { 0x06f, "Krait S4 Pro", "Krait", 4 }, { 0xd03, "Cortex-A53", "ARM_Cortex-A53", 6 }, { 0xd07, "Cortex-A57", "ARM_Cortex-A57", 6 }, + { 0xd08, "Cortex-A72", "ARM_Cortex-A72", 6 }, { 0xd0f, "AArch64", "ARM_AArch64", 6 }, }; diff --git a/daemon/defaults.xml b/daemon/defaults.xml index 086eca1..bdd907e 100644 --- a/daemon/defaults.xml +++ b/daemon/defaults.xml @@ -44,6 +44,11 @@ <configuration counter="ARM_Cortex-A57_cnt1" event="0x16"/> <configuration counter="ARM_Cortex-A57_cnt2" event="0x10"/> <configuration counter="ARM_Cortex-A57_cnt3" event="0x19"/> + <configuration counter="ARM_Cortex-A72_ccnt" event="0x11"/> + <configuration counter="ARM_Cortex-A72_cnt0" event="0x8"/> + <configuration counter="ARM_Cortex-A72_cnt1" event="0x16"/> + <configuration counter="ARM_Cortex-A72_cnt2" event="0x10"/> + <configuration counter="ARM_Cortex-A72_cnt3" event="0x19"/> <configuration counter="Scorpion_ccnt" event="0xff"/> <configuration counter="Scorpion_cnt0" event="0x08"/> <configuration counter="Scorpion_cnt1" event="0x10"/> diff --git a/daemon/events-Cortex-A72.xml b/daemon/events-Cortex-A72.xml new file mode 100644 index 0000000..cdbc753 --- /dev/null +++ b/daemon/events-Cortex-A72.xml @@ -0,0 +1,87 @@ + <counter_set name="ARM_Cortex_A72_cnt" count="6"/> + <category name="Cortex-A72" counter_set="ARM_Cortex_A72_cnt" per_cpu="yes" supports_event_based_sampling="yes"> + <event counter="ARM_Cortex_A72_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/> + <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> + <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> + <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> + <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> + <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> + <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> + <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/> + <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> + <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> + <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> + <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/> + <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> + <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/> + <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/> + <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/> + <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/> + <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/> + <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/> + <event event="0x19" title="Bus" name="Access" description="Bus access"/> + <event event="0x1A" title="Memory" name="Error" description="Local memory error"/> + <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/> + <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/> + <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/> + <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/> + <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/> + <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/> + <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/> + <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/> + <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/> + <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/> + <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/> + <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/> + <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/> + <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/> + <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/> + <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/> + <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/> + <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/> + <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/> + <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/> + <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/> + <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/> + <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/> + <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/> + <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/> + <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/> + <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/> + <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/> + <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/> + <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/> + <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/> + <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/> + <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/> + <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/> + <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/> + <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/> + <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/> + <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/> + <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/> + <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/> + <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/> + <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/> + <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/> + <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/> + <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/> + <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/> + <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/> + <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/> + <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/> + <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/> + <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/> + <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/> + <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/> + <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/> + <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/> + <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/> + <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/> + <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/> + <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/> + <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/> + <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/> + <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/> + <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/> + </category> diff --git a/driver/gator.h b/driver/gator.h index 5cc73a3..64173ec 100644 --- a/driver/gator.h +++ b/driver/gator.h @@ -38,6 +38,7 @@ #define KRAIT_S4_PRO 0x06f #define CORTEX_A53 0xd03 #define CORTEX_A57 0xd07 +#define CORTEX_A72 0xd08 #define AARCH64 0xd0f #define OTHER 0xfff diff --git a/driver/gator_main.c b/driver/gator_main.c index d3814c7..2bb3e87 100644 --- a/driver/gator_main.c +++ b/driver/gator_main.c @@ -383,6 +383,13 @@ static const struct gator_cpu gator_cpus[] = { .pmnc_counters = 6, }, { + .cpuid = CORTEX_A72, + .core_name = "Cortex-A72", + .pmnc_name = "ARM_Cortex-A72", + .dt_name = "arm,cortex-a72", + .pmnc_counters = 6, + }, + { .cpuid = AARCH64, .core_name = "AArch64", .pmnc_name = "ARM_AArch64", |