diff options
| author | Drew Richardson <drew.richardson@arm.com> | 2013-03-26 12:00:00 -0700 |
|---|---|---|
| committer | Drew Richardson <drew.richardson@arm.com> | 2014-12-19 15:41:32 -0800 |
| commit | 1b5637426bfc10a64571c81e24019032206d651b (patch) | |
| tree | 71e362be9385179b545c77205cdab612a133ca86 /daemon/events-Cortex-A8.xml | |
| parent | a01058e248133bb7c1ba0238ab380e4fac924e97 (diff) | |
gator: Version 5.145.14
Signed-off-by: Drew Richardson <drew.richardson@arm.com>
Diffstat (limited to 'daemon/events-Cortex-A8.xml')
| -rw-r--r-- | daemon/events-Cortex-A8.xml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/daemon/events-Cortex-A8.xml b/daemon/events-Cortex-A8.xml index fe4c69d..a301f1f 100644 --- a/daemon/events-Cortex-A8.xml +++ b/daemon/events-Cortex-A8.xml @@ -1,6 +1,6 @@ <counter_set name="ARM_Cortex-A8_cnt" count="4"/> <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cnt" per_cpu="yes" supports_event_based_sampling="yes"> - <event counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> + <event counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> @@ -27,7 +27,7 @@ <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/> <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/> <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/> - <event event="0x48" title="Memory" name="Unaligned access" description="Any unaligned memory access that results in a replay"/> + <event event="0x48" title="Memory" name="Unaligned access replay" description="Any unaligned memory access that results in a replay"/> <event event="0x49" title="Cache" name="L1 data hash miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/> <event event="0x4a" title="Cache" name="L1 inst hash miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/> <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/> |