path: root/daemon/events-Cortex-A7.xml
diff options
authorDrew Richardson <drew.richardson@arm.com>2013-03-26 12:00:00 -0700
committerDrew Richardson <drew.richardson@arm.com>2014-12-19 15:41:32 -0800
commit1b5637426bfc10a64571c81e24019032206d651b (patch)
tree71e362be9385179b545c77205cdab612a133ca86 /daemon/events-Cortex-A7.xml
parenta01058e248133bb7c1ba0238ab380e4fac924e97 (diff)
gator: Version 5.145.14
Signed-off-by: Drew Richardson <drew.richardson@arm.com>
Diffstat (limited to 'daemon/events-Cortex-A7.xml')
1 files changed, 5 insertions, 6 deletions
diff --git a/daemon/events-Cortex-A7.xml b/daemon/events-Cortex-A7.xml
index 50bba7f..bbd7a26 100644
--- a/daemon/events-Cortex-A7.xml
+++ b/daemon/events-Cortex-A7.xml
@@ -1,6 +1,6 @@
<counter_set name="ARM_Cortex-A7_cnt" count="4"/>
<category name="Cortex-A7" counter_set="ARM_Cortex-A7_cnt" per_cpu="yes" supports_event_based_sampling="yes">
- <event counter="ARM_Cortex-A7_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+ <event counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
<event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
<event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
<event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
@@ -17,7 +17,6 @@
<event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
<event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
<event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
- <event event="0x11" title="Cycle" name="Counter" description=""/>
<event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
<event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
<event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
@@ -25,8 +24,8 @@
<event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
<event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
<event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
- <event event="0x19" title="Bus" name="Access" description=""/>
- <event event="0x1d" title="Bus" name="Cycle" description=""/>
+ <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
+ <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
<event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
<event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
<event event="0x86" title="Exception" name="IRQ" description="IRQ exception taken"/>
@@ -37,8 +36,8 @@
<event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
<event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
<event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
- <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/>
- <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/>
+ <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description="ETM - ETM Ext Out[0]"/>
+ <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description="ETM - ETM Ext Out[1]"/>
<event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
<event event="0xCA" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local cluster, rather than accessing the L2 cache or issuing an external read."/>