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authorDrew Richardson <drew.richardson@arm.com>2015-07-22 12:00:00 -0700
committerDrew Richardson <drew.richardson@arm.com>2015-07-24 07:41:39 -0700
commit7ca6004c0b05138c49b9b21e0045487f55a60ab6 (patch)
tree74cdc2c608e28891189b58e68992b3a8acf140e0 /daemon/events-CCI-400.xml
parentc2fdcde9f26fff5eebbcc2ab34adb9d4202e0d55 (diff)
downloadgator-7ca6004c0b05138c49b9b21e0045487f55a60ab6.tar.gz
gator: Version 5.22HEAD5.22master
Signed-off-by: Drew Richardson <drew.richardson@arm.com>
Diffstat (limited to 'daemon/events-CCI-400.xml')
-rw-r--r--daemon/events-CCI-400.xml6
1 files changed, 3 insertions, 3 deletions
diff --git a/daemon/events-CCI-400.xml b/daemon/events-CCI-400.xml
index 40d91e5..0dd72c0 100644
--- a/daemon/events-CCI-400.xml
+++ b/daemon/events-CCI-400.xml
@@ -41,9 +41,9 @@
<event event="0x19" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/>
<event event="0x1a" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase MIx_W_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/>
</category>
- <counter_set name="CCI_400-r1_cnt" count="4"/>
- <category name="CCI-400" counter_set="CCI_400-r1_cnt" per_cpu="no">
- <event counter="CCI_400-r1_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+ <counter_set name="CCI_400_r1_cnt" count="4"/>
+ <category name="CCI-400" counter_set="CCI_400_r1_cnt" per_cpu="no">
+ <event counter="CCI_400_r1_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
<option_set name="Slave">
<option event_delta="0x00" name="S0" description="Slave interface 0"/>
<option event_delta="0x20" name="S1" description="Slave interface 1"/>