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/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#ifndef MISC_H
#define MISC_H
#include <stdio.h>
#include <string.h>
#define NUM_CPUS 8
#define inline __inline
#define A7 0xC07
#define A15 0xC0F
#define PART_NO(x) ((x >> 4) & 0xfff)
#define REVISION(x) (x & 0xf)
#define VARIANT(x) ((x >> 20) & 0xf)
#define MAX_CLUSTERS 2
#define MAX_CORES 8
#define MAX_CPUIFS 8
#define STACK_SIZE 96
#define TRUE 1
#define FALSE 0
#define CONTEXT_SAVE 0
#define CONTEXT_RESTORE 1
/* Switcher HVCs */
#define HVC_SWITCHER_CLUSTER_SWITCH 0x90000000
/* Virtualisor HVCs */
#define HVC_VIRT_MPIDR_READ 0x90000100
/* PMU HVCs */
#define HVC_PMU_PMCR_READ 0x90001000
#define HVC_PMU_PMCR_WRITE 0x90001001
#define HVC_PMU_PMSELR_READ 0x90001002
#define HVC_PMU_PMSELR_WRITE 0x90001003
#define HVC_PMU_PMXEVTYPER_READ 0x90001004
#define HVC_PMU_PMXEVTYPER_WRITE 0x90001005
#define HVC_PMU_PMCNTENSET_READ 0x90001006
#define HVC_PMU_PMCNTENSET_WRITE 0x90001007
#define HVC_PMU_PMCNTENCLR_READ 0x90001008
#define HVC_PMU_PMCNTENCLR_WRITE 0x90001009
#define HVC_PMU_PMCCNTR_READ 0x9000100A
#define HVC_PMU_PMCCNTR_WRITE 0x9000100B
#define HVC_PMU_PMOVSR_READ 0x9000100C
#define HVC_PMU_PMOVSR_WRITE 0x9000100D
#define HVC_PMU_PMXEVCNTR_READ 0x9000100E
#define HVC_PMU_PMXEVCNTR_WRITE 0x9000100F
#define HVC_PMU_PMINTENSET_READ 0x90001010
#define HVC_PMU_PMINTENSET_WRITE 0x90001011
#define HVC_PMU_PMINTENCLR_READ 0x90001012
#define HVC_PMU_PMINTENCLR_WRITE 0x90001013
#define HVC_PMU_SWITCH 0x90001100
#define HVC_PMU_GET_COUNTERS_SIZE 0x90001200
#define HVC_PMU_SYNC_PMU_COUNTERS 0x90001201
/* PMU States. */
#define PMU_STATE0 0
#define PMU_STATE1 1
#define PMU_STATE2 2
/*************************************************
* Virtual GIC defines
*************************************************/
/* Bit definitions in the secure GICC_CTLR */
#define EOI_MODE_NS (1 << 10)
#define EOI_MODE_S (1 << 9)
/* Bit definitions in the Active list registers */
#define HW_IRQ ((unsigned) 1 << 31)
#define NS_IRQ (1 << 30)
#define STATE(x) ((x & 0x3) << 28)
#define PENDING 0x1
/* Misc */
#define INTACK_CPUID_MASK 0x7
/*************************************************
* Bit definitions in the HYP configuration
* register.
*************************************************/
#define HCR_AMO (1 << 5)
#define HCR_IMO (1 << 4)
#define HCR_FMO (1 << 3)
#define HCR_VM (1 << 0)
#define HCR_TID2 (1 << 17)
#define HCR_TSW (1 << 22)
/*************************************************
* TEX remap defines for first level translations
*************************************************/
/* PRRR fields for memory attributes */
#define TR0(x) ((x) << 0) // SO
#define TR1(x) ((x) << 2) // DV
#define TR4(x) ((x) << 8) // NC
#define TR7(x) ((x) << 14) // C
/* PRRR fields for shareability attributes */
#define NOS0(x) ((x) << 24)
#define NOS1(x) ((x) << 25)
#define NOS4(x) ((x) << 28)
#define NOS7(x) ((x) << 31)
#define NS1(x) ((x) << 19)
#define DS1(x) ((x) << 17)
/* Memory attributes */
#define NORMAL_MEM 0x2
#define DEVICE_MEM 0x1
#define SO_MEM 0x0
#define INNER_SH 0x1
#define SHAREABLE 0x1
/* NMRR fields */
#define IR7(x) ((x) << 14) // Inner Cache attributes for TEX,C,B = 1,1,1
#define IR4(x) ((x) << 8) // Inner Cache attributes for TEX,C,B = 1,0,0
#define OR7(x) ((x) << 30) // Outer Cache attributes for TEX,C,B = 1,1,1
#define OR4(x) ((x) << 24) // Outer Cache attributes for TEX,C,B = 1,0,0
/* Normal memory attributes */
#define NMRR_NC 0x0
#define NMRR_WBWA 0x1
/************************************************
* Page table walk attributes in TTBR0/1
************************************************/
#define NOS(x) ((x) << 5)
#define RGN(x) ((x) << 3)
#define SH(x) ((x) << 1)
#define IRGN(x) ((((x) & 0x2) << 5) | ((x) & 0x1))
#define TTBR_SH 0x1
#define TTBR_WBWA 0x1
/*
* Bit definitions of Level 2 translation
* table entries.
*/
/* Mapping type[1:0] */
#define INVALID_MAPPING 0x0
#define BLOCK_MAPPING 0x1
#define TABLE_MAPPING 0x3
/*
* Bit definitions of Level 3 translation
* table entries.
*/
/* Mapping type[1:0] */
#define VALID_MAPPING 0x3
/* Lower block attributes[11:2] */
#define NON_GLOBAL (1 << 11)
#define ACCESS_FLAG (1 << 10)
#define SHAREABILITY(x) ((x & 0x3) << 8)
#define ACCESS_PERM(x) ((x & 0x3) << 6)
#define MEM_ATTR(x) ((x & 0xf) << 2)
/* Upper block attributes[63:52]. Defined as the upper word */
#define XN (1 << 22)
#define PXN (1 << 21)
/*
* Cache levels.
*/
#define L1 0x0
#define L2 0x1
/*
* Cache maintenance op types.
*/
#define INV 0x0
#define CLN 0x1
#define CLN_INV 0x2
/*
* Cache line length in bytes
*/
#define CACHE_LINE_SZ 64
/*
* CCI defines
*/
#define CCI_BASE 0x2c090000
#define CCI_PERF_CNT(x) CCI_BASE + ((0xa + x ) << 12)
#define CCI_CYCLE_CNT CCI_BASE + 0x9000
#define A15_SL_IFACE_BASE CCI_BASE + 0x4000
#define A7_SL_IFACE_BASE CCI_BASE + 0x5000
/* PMU Counter Registers */
#define EVNT_SEL_REG 0x0
#define CNT_REG 0x4
#define CNT_CTLR_REG 0x8
#define OVRFLW_STAT_REG 0xc
/* Control interface register offsets */
#define CTLR_OVERRIDE_REG 0x0
#define SPEC_CTLR_REG 0x4
#define SECURE_ACCESS_REG 0x8
#define STATUS_REG 0xc
#define IMPRECISE_ERR_REG 0x10
#define PERF_MON_CTRL_REG 0x100
/* Slave interface register */
#define SNOOP_CTLR_REG 0x0
/* PMCR bits */
#define PMCR_CEN (1 << 0)
#define PMCR_RST (1 << 1)
#define PMCR_CCR (1 << 2)
#define PMCR_CCD (1 << 3)
#define reset_cci_pmu() write32(CCI_BASE + PERF_MON_CTRL_REG, PMCR_RST | PMCR_CCR)
#define enable_cci_pmu() write32(CCI_BASE + PERF_MON_CTRL_REG, PMCR_CEN)
#define enable_cci_cntr(x) write32(CCI_PERF_CNT(x) + CNT_CTLR_REG, 0x1)
#define disable_cci_cntr(x) write32(CCI_PERF_CNT(x) + CNT_CTLR_REG, 0x0)
#define select_cci_event(x, y) write32(CCI_PERF_CNT(x) + EVNT_SEL_REG, y)
#define read_cci_cntr(x) read32(CCI_PERF_CNT(x) + CNT_REG)
/*
* TODO:
* Move platform specific definitions to the right places
*/
#define KFSCB_BASE 0x60000000
#define RST_HOLD0 0x0
#define RST_HOLD1 0x4
#define SYS_SWRESET 0x8
#define RST_STAT0 0xc
#define RST_STAT1 0x10
#define EAG_CFG_R 0x20
#define EAG_CFG_W 0x24
#define KFC_CFG_R 0x28
#define KFC_CFG_W 0x2c
#define KFS_CFG_R 0x30
#define RST_HANDLER0 0x40
#define RST_HANDLER1 0x48
#define RST_HANDLER2 0x50
#define RST_HANDLER3 0x58
#define RST_HANDLER4 0x60
#define RST_HANDLER5 0x68
#define RST_HANDLER6 0x70
#define RST_HANDLER7 0x78
#define KFS_ID 0xffc
/*
* KFSCB Tube offsets. Models only
*/
#define KFS_TUBE0 0x400
#define KFS_TUBE1 0x420
#define KFS_TUBE2 0x440
#define KFS_TUBE3 0x460
/*
* Map the 4 tubes to the Secure
* & non-secure worlds
*/
#define SEC_TUBE0 KFS_TUBE0
#define SEC_TUBE1 KFS_TUBE1
#define NS_TUBE0 KFS_TUBE2
#define NS_TUBE1 KFS_TUBE3
/* KFSCB Tube register offsets. */
#define TUBE_CHAR 0x00
#define TUBE_DATA0 0x08
#define TUBE_DATA1 0x10
#define TUBE_DATA2 0x18
#define CLUSTER_CPU_COUNT(x) (((read32(KFSCB_BASE + KFS_CFG_R) >> 16) >> (x << 2)) & 0xf)
#define DC_SYSTYPE ((read32(KFSCB_BASE + KFS_ID) >> 16) & 0xf)
#define asym_clusters() (((read32(KFSCB_BASE + KFS_CFG_R) >> 16) & 0xf) == \
((read32(KFSCB_BASE + KFS_CFG_R) >> 20) & 0xf))
/*
* "Always on" uses cpuids that span across clusters e.g.
* 0-7 for an MPx4+MPx4 system.
*/
#define abs_cpuid(cpu_id, cluster_id) (cluster_id ? cpu_id + CLUSTER_CPU_COUNT(!cluster_id) : cpu_id)
#define CLUSTER_LVL_RST (1 << 0)
#define RST_BIT(x) (1 << 4) << x
#define RST_LVL(x, y) ((x & 0x3) << 8) << (y << 1)
#define CORE_RESET 0x0
#define CORE_PORESET 0x1
#define CLUSTER_RESET 0x2
#define EAGLE_CORES(x) ((x & 0xf) << 16)
#define KFC_CORES(x) ((x & 0xf) << 20)
#define SW_RESET (1 << 2)
#define ENTER_RESET 0x1
#define EXIT_RESET 0x2
#define CASCADE_RESET 0x4
#define A15_A15 0x0
#define A7_A15 0x1
#define A15_A7 0x2
#define EAGLE 0x0
#define KFC 0x1
/* Platform defines */
#define VE_SYS_BASE 0X1C010000
#define FLAGS_SET 0x30
#define FLAGS_CLR 0x34
/* Control register bits */
#define CR_M (1<<0) /* MMU enabled */
#define CR_A (1<<1) /* Align fault enable */
#define CR_C (1<<2) /* Data cache */
#define CR_W (1<<3) /* Write buffer */
#define CR_Z (1<<11) /* Branch prediction */
#define CR_I (1<<12) /* Instruction cache */
#define CR_V (1<<13) /* Vectors */
#define CR_XP (1<<23) /* Extended page tables */
#define CR_TRE (1<<28) /* TEX Remap */
/*
* Processor modes
*/
#define MON_MODE 0x16
#define SVC_MODE 0x13
#define HYP_MODE 0x1A
#define USR_MODE 0x10
/* Timer Bits */
#define HYP_TIMER_MULT 0xa /* 12Mhz * 10 i.e. interrupt every 10ms. Linux uses 12MHz * 10 */
#define LCL_TIMER_FREQ 0x7f /* Every 128th timer acts as a trigger */
#define HYP_TIMER_IRQ 0x1a
#define LCL_TIMER_IRQ 0x1e
#define TIMER_ENABLE 0x1
#define TIMER_DISABLE 0x0
#define TIMER_MASK_IRQ 0x2
#define TIMER_IRQ_STAT 0x4
/* Trap ids provided in the HSR */
#define NUM_TRAPS 0x27
#define TRAP_UNKNOWN 0x0
#define TRAP_WFE_WFI 0x1
#define TRAP_CP15_32 0x3
#define TRAP_CP15_64 0x4
#define TRAP_CP14_32 0x5
#define TRAP_CP14_LDC_STC 0x6
#define TRAP_HCPTR_1 0x7
#define TRAP_HCPTR_2 0x8
#define TRAP_JAZELLE 0x9
#define TRAP_BXJ 0xA
#define TRAP_CP14_64 0xC
#define TRAP_HYP_SVC 0x11
#define TRAP_HVC 0x12
#define TRAP_HYP_SMC 0x13
#define TRAP_IABORT 0x20
#define TRAP_HYP_IABORT 0x21
#define TRAP_DABORT 0x24
#define TRAP_HYP_DABORT 0x25
/*
* Defines for making SMC calls
*/
#define SMC_SEC_INIT 0x0
#define SMC_SEC_SAVE 0x1
#define SMC_SEC_SHUTDOWN 0x2
#define MAX_CACHE_LEVELS 0x8
/* Data/unified and instruction cache */
#define MAX_CACHE_VARIANTS 0x2
#define CRN_C0 0x0
#define CRN_C7 0x7
#define CRN_C9 0x9
#define CRN_C15 0xf
/*
* Opcode2 definitions in the corresponding cp15 instruction
*/
#define MIDR 0x0
#define CTR 0x1
#define TCMTR 0x2
#define TLBTR 0x3
#define MPIDR 0x5
#define CCSIDR 0x0
#define CLIDR 0x1
#define AIDR 0x4
#define CSSELR 0x0
#define DCISW 0x2
#define DCCSW 0x2
#define DCCISW 0x2
#define ID_PFR0 0x0
#define ID_PFR1 0x1
#define ID_DFR0 0x2
#define ID_AFR0 0x3
#define ID_MMFR0 0x4
#define ID_MMFR1 0x5
#define ID_MMFR2 0x6
#define ID_MMFR3 0x7
#define ID_ISAR0 0x0
#define ID_ISAR1 0x1
#define ID_ISAR2 0x2
#define ID_ISAR3 0x3
#define ID_ISAR4 0x4
#define ID_ISAR5 0x5
#define IS_BOOT_CLUSTER (read_clusterid() == boot_cluster)
#define IS_HOST_CLUSTER (read_clusterid() == host_cluster)
#define IS_TGT_CLUSTER (!IS_HOST_CLUSTER)
extern void enable_cci_snoops(unsigned);
extern void disable_cci_snoops(unsigned);
extern void switch_cluster(unsigned);
extern unsigned long long *get_powerdown_stack(unsigned);
extern void spin_lock(unsigned int *);
extern void spin_unlock(unsigned int *);
extern void panic(void);
extern unsigned get_inbound(void);
extern unsigned reset_status(unsigned, unsigned, unsigned);
extern unsigned map_cpuif(unsigned, unsigned);
extern unsigned get_cpuif(unsigned, unsigned);
extern unsigned remap_cpuif(unsigned *);
extern unsigned get_cpuif_mask(unsigned);
extern unsigned get_cpu_mask(unsigned);
extern unsigned BL_DV_PAGE$$Base;
extern unsigned BL_SEC_DV_PAGE$$Base;
extern unsigned boot_cluster;
extern unsigned host_cluster;
extern unsigned switcher;
extern unsigned switchable_cpus_mask;
#define bitindex(x) (31-__builtin_clz(x))
#define find_first_cpu() 0
#define write32(addr, val) (*(volatile unsigned int *)(addr) = (val))
#define read32(addr) (*(volatile unsigned int *)(addr))
#endif
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