blob: 7112cbcc2aa64bfe632ccce3cd1fc588de64e03b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#ifndef ARM_H
#define ARM_H
/*
* File for ARM Architecture specific defines and constants
*/
#define CP15CTL_M 0x1
#define CP15CTL_A 0x2
#define CP15CTL_C 0x4
#define CP15CTL_W 0x8
/*
* 4:6 SBO
*/
#define CP15CTL_B 0x80
#define CP15CTL_S 0x100
#define CP15CTL_R 0x200
#define CP15CTL_F 0x400
#define CP15CTL_Z 0x800
#define CP15CTL_I 0x1000
#define CP15CTL_V 0x2000
#define CP15CTL_RR 0x4000
#define CP15CTL_L4 0x8000
#define FSR_XTABT_L1 0x0C
#define FSR_XTABT_L2 0x0E
#define FSR_SECTRANS 0x05
#define FSR_PAGETRANS 0x07
/*
* These macros extract the page/section numbers from an address
*/
#define pagenum(x) (((x) >> 12) & 0xFF)
#define secnum(x) ((x) >> 21) /* i$$NEW$$ */
//#define secnum(x) ((x) >> 20) /* orig */
#define MODE_USR 0x10
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_ABT 0x17
#define MODE_UND 0x1D
#define MODE_SYS 0x1F
#define MODE_MON 0x16
#define getmode(x) ((x) & 0x1F)
#endif
|