1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
|
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#include "context.h"
#include "misc.h"
#include "events.h"
#include "virt_helpers.h"
#include "virtualisor.h"
#include "bl.h"
#include "int_master.h"
extern unsigned vectors;
extern void SetupVirtExtPageTables(unsigned, unsigned);
extern void Enable2ndStagePageTables(void);
extern void monmode_setup(void);
extern void config_uart(void);
extern void SetupVGIC(unsigned);
extern void enable_trigger(unsigned);
extern void set_pmu_vcnt(unsigned);
extern void set_pmu_state(unsigned);
unsigned host_cluster = HOST_CLUSTER;
unsigned boot_cluster = BOOT_CLUSTER;
unsigned switcher = SWITCHER;
vm_state guestos_state[MAX_CPUIFS];
unsigned guestos_state_size = sizeof(vm_state);
/*
* To make events work across a non-coherent interconnect, events
* are allocated in an SO or DV page.
*/
unsigned event[NUM_CPUS][MAX_EVENTS] __attribute__ ((section("BL_DV_PAGE")));
/*
* C function to perform the remaining initialisation
* once the MMU has been enabled after a cold reset
*/
void bl_rest_init(void)
{
unsigned first_cpu = find_first_cpu();
unsigned cpu_id = read_cpuid();
unsigned cluster_id = read_clusterid();
unsigned warm_reset = 0;
/* HYP mode initialisation performed after every reset */
write_hvbar((unsigned)&vectors);
Enable2ndStagePageTables();
/* Initialise a per cpu UART */
config_uart();
if (switcher) {
/*
* Ask the secure world to initialise its context.
* Not required when "always on"
*/
smc(SMC_SEC_INIT, 0, 0);
/*
* Since we are using the shared vgic, we need to map
* the cpuids to the cpu interfaces as there is no
* longer a 1:1 mapping
*/
map_cpuif(cluster_id, cpu_id);
if (async_switchover && first_cpu == cpu_id)
enable_trigger(read_cntfrq());
} else {
/*
* Only one cpu should enable the CCI while the other
* cpus wait.
*/
if (first_cpu == cpu_id && cluster_id == host_cluster) {
write32(A7_SL_IFACE_BASE + SNOOP_CTLR_REG, 0x3);
write32(A15_SL_IFACE_BASE + SNOOP_CTLR_REG, 0x3);
dsb();
}
/* Wait for the dust to settle down */
while (read32(CCI_BASE + STATUS_REG) & 0x1) ;
}
/* Initialise the Virtual GIC and the Virtualizer */
SetupVGIC(warm_reset);
SetupVirtualisor(first_cpu);
/* Setup Performance Monitor Units. */
set_pmu_vcnt(4);
set_pmu_state(PMU_STATE0);
return;
}
|
