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/*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#include "context.h"
#include "misc.h"
#include "events.h"
#include "virt_helpers.h"
#include "virtualisor.h"
#include "bl.h"
extern unsigned vectors;
extern system_context switcher_context;
extern void SetupVirtExtPageTables(unsigned, unsigned);
extern void Enable2ndStagePageTables(void);
extern void monmode_setup(void);
extern void config_uart(void);
extern void SetupVGIC(unsigned);
extern void enable_trigger(unsigned);
extern void restore_context(unsigned);
extern unsigned async_switchover;
unsigned host_cluster = HOST_CLUSTER;
unsigned switcher = SWITCHER;
vm_state guestos_state[MAX_CPUIFS];
unsigned guestos_state_size = sizeof(vm_state);
/*
* To make events work across a non-coherent interconnect, events
* are allocated in an SO or DV page.
*/
unsigned event[NUM_CPUS][MAX_EVENTS] __attribute__ ((section("BL_DV_PAGE")));
/*
* C function to perform the remaining initialisation
* once the MMU has been enabled after a cold reset
*/
void bl_rest_init(void)
{
unsigned first_cpu = find_first_cpu();
unsigned cpu_id = read_cpuid();
unsigned cluster_id = read_clusterid();
unsigned warm_reset = 0;
/* HYP mode initialisation performed after every reset */
write_hvbar((unsigned)&vectors);
Enable2ndStagePageTables();
/* Initialise a per cpu UART */
config_uart();
if (switcher) {
/*
* Ask the secure world to initialise its context.
* Not required when "always on"
*/
smc(SMC_SEC_INIT, 0);
/*
* Since we are using the shared vgic, we need to map
* the cpuids to the cpu interfaces as there is no
* longer a 1:1 mapping
*/
map_cpuif(cluster_id, cpu_id);
if (async_switchover && first_cpu == cpu_id)
enable_trigger(read_cntfrq());
} else {
/*
* Only one cpu should enable the CCI while the other
* cpus wait.
*/
if (first_cpu == cpu_id && cluster_id == host_cluster) {
write32(A7_SL_IFACE_BASE + SNOOP_CTLR_REG, 0x3);
write32(A15_SL_IFACE_BASE + SNOOP_CTLR_REG, 0x3);
dsb();
}
/* Wait for the dust to settle down */
while (read32(CCI_BASE + STATUS_REG) & 0x1) ;
}
/* Initialise the Virtual GIC and the Virtualizer */
SetupVGIC(warm_reset);
SetupVirtualisor(first_cpu);
return;
}
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