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authorDietmar Eggemann <dietmar.eggemann@arm.com>2012-05-15 11:50:12 +0100
committerDietmar Eggemann <dietmar.eggemann@arm.com>2012-05-23 12:44:36 +0100
commitb01a51f1f4d2de9e350e1d4f82adf05f1233051e (patch)
tree4f823073bf82129cc320b792c71133b224244413
parentedc6843a3a4ac02422bda79f8cfb6894c5d384df (diff)
downloadswitcher-b01a51f1f4d2de9e350e1d4f82adf05f1233051e.tar.gz
Cleanup whitespace errors.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
-rw-r--r--acsr/c_helpers.c14
-rw-r--r--acsr/helpers.h14
-rw-r--r--acsr/helpers.s446
-rw-r--r--acsr/v7.s148
-rw-r--r--big-little/Makefile12
-rw-r--r--big-little/bl-sec.scf.template2
-rw-r--r--big-little/bl.scf.template2
-rw-r--r--big-little/common/cci.c14
-rw-r--r--big-little/common/hyp_setup.c22
-rw-r--r--big-little/common/hyp_vectors.s216
-rw-r--r--big-little/common/pagetable_setup.c56
-rw-r--r--big-little/common/vgic_handle.c24
-rw-r--r--big-little/common/vgic_setup.c28
-rw-r--r--big-little/common/vgiclib.c86
-rw-r--r--big-little/include/arm.h14
-rw-r--r--big-little/include/bakery.h16
-rw-r--r--big-little/include/bl.h14
-rw-r--r--big-little/include/context.h14
-rw-r--r--big-little/include/events.h18
-rw-r--r--big-little/include/gic_registers.h176
-rw-r--r--big-little/include/handler.h14
-rw-r--r--big-little/include/hvc.h14
-rw-r--r--big-little/include/hyp_types.h14
-rw-r--r--big-little/include/hyp_vmmap.h14
-rw-r--r--big-little/include/int_master.h16
-rw-r--r--big-little/include/misc.h30
-rw-r--r--big-little/include/traps.h14
-rw-r--r--big-little/include/vgiclib.h14
-rw-r--r--big-little/include/virt_helpers.h14
-rw-r--r--big-little/lib/bakery.c14
-rw-r--r--big-little/lib/tube.c14
-rw-r--r--big-little/lib/uart.c14
-rw-r--r--big-little/lib/virt_events.c14
-rw-r--r--big-little/lib/virt_helpers.s174
-rw-r--r--big-little/secure_world/events.c14
-rw-r--r--big-little/secure_world/flat_pagetable.s50
-rw-r--r--big-little/secure_world/monmode_vectors.s160
-rw-r--r--big-little/secure_world/secure_context.c22
-rw-r--r--big-little/secure_world/secure_resets.c20
-rw-r--r--big-little/secure_world/secure_world.h14
-rw-r--r--big-little/secure_world/ve_reset_handler.s32
-rw-r--r--big-little/switcher/context/gic.c20
-rw-r--r--big-little/switcher/context/ns_context.c18
-rw-r--r--big-little/switcher/context/sh_vgic.c30
-rw-r--r--big-little/switcher/trigger/async_switchover.c22
-rw-r--r--big-little/switcher/trigger/handle_switchover.s26
-rw-r--r--big-little/virtualisor/cache_geom.c46
-rw-r--r--big-little/virtualisor/cpus/a15/a15.c14
-rw-r--r--big-little/virtualisor/cpus/a15/include/a15.h14
-rw-r--r--big-little/virtualisor/cpus/a7/a7.c14
-rw-r--r--big-little/virtualisor/cpus/a7/include/a7.h14
-rw-r--r--big-little/virtualisor/include/cache_geom.h26
-rw-r--r--big-little/virtualisor/include/mem_trap.h14
-rw-r--r--big-little/virtualisor/include/virtualisor.h20
-rw-r--r--big-little/virtualisor/mem_trap.c18
-rw-r--r--big-little/virtualisor/vgic_trap_handler.c18
-rw-r--r--big-little/virtualisor/virt_context.c30
-rw-r--r--big-little/virtualisor/virt_handle.c18
-rw-r--r--big-little/virtualisor/virt_setup.c34
-rw-r--r--bootwrapper/Makefile8
-rw-r--r--bootwrapper/big-little-mp1.mxscript12
-rw-r--r--bootwrapper/big-little-mp4.mxscript12
-rw-r--r--bootwrapper/boot.S60
-rw-r--r--bootwrapper/bootargs.S20
-rw-r--r--bootwrapper/bootwrapper.h14
-rw-r--r--bootwrapper/c_start.c16
-rw-r--r--bootwrapper/emubuild.s20
-rw-r--r--bootwrapper/filesystem.S26
-rw-r--r--bootwrapper/helpers.S512
-rw-r--r--bootwrapper/helpers.h14
-rw-r--r--bootwrapper/kernel.S18
-rwxr-xr-xbootwrapper/makemap14
-rw-r--r--bootwrapper/uart.c14
-rw-r--r--bootwrapper/vectors.S16
-rw-r--r--bootwrapper/vgic.h14
75 files changed, 1604 insertions, 1604 deletions
diff --git a/acsr/c_helpers.c b/acsr/c_helpers.c
index a7df858..7ca6df7 100644
--- a/acsr/c_helpers.c
+++ b/acsr/c_helpers.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/**
diff --git a/acsr/helpers.h b/acsr/helpers.h
index 14c8472..ea1e0ca 100644
--- a/acsr/helpers.h
+++ b/acsr/helpers.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/*
diff --git a/acsr/helpers.s b/acsr/helpers.s
index 0c92511..1a7fba4 100644
--- a/acsr/helpers.s
+++ b/acsr/helpers.s
@@ -1,26 +1,26 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
+ ; permission.
+ ;
- EXPORT isb
+ EXPORT isb
EXPORT dsb
EXPORT dmb
EXPORT wfi
@@ -33,25 +33,25 @@
EXPORT get_cpu_type
EXPORT va_to_pa
- EXPORT read_cbar
+ EXPORT read_cbar
EXPORT read_sctlr
EXPORT read_actlr
EXPORT read_prrr
EXPORT read_nmrr
EXPORT read_l2ctlr
EXPORT read_dacr
- EXPORT read_ttbr0
- EXPORT read_cpacr
+ EXPORT read_ttbr0
+ EXPORT read_cpacr
EXPORT read_scr
EXPORT read_cpsr
EXPORT read_midr
- EXPORT read_mpidr
- EXPORT read_cntpct
- EXPORT read_cntfrq
+ EXPORT read_mpidr
+ EXPORT read_cntpct
+ EXPORT read_cntfrq
EXPORT read_vmpidr
- EXPORT read_vmidr
+ EXPORT read_vmidr
EXPORT read_vttbr
- EXPORT read_httbr
+ EXPORT read_httbr
EXPORT read_id_pfr0
EXPORT read_id_pfr1
EXPORT read_id_dfr0
@@ -59,20 +59,20 @@
EXPORT read_id_mmfr0
EXPORT read_id_mmfr1
EXPORT read_id_mmfr2
- EXPORT read_id_mmfr3
+ EXPORT read_id_mmfr3
EXPORT read_id_isar0
EXPORT read_id_isar1
EXPORT read_id_isar2
EXPORT read_id_isar3
EXPORT read_id_isar4
- EXPORT read_id_isar5
+ EXPORT read_id_isar5
EXPORT read_cpuid
- EXPORT read_aidr
+ EXPORT read_aidr
EXPORT read_ctr
EXPORT read_tcmtr
EXPORT read_tlbtr
EXPORT read_clusterid
- EXPORT read_l2ctlr
+ EXPORT read_l2ctlr
EXPORT read_hsctlr
EXPORT read_hdfar
EXPORT read_hpfar
@@ -80,22 +80,22 @@
EXPORT read_hcr
EXPORT read_hdcr
EXPORT read_hcptr
- EXPORT read_hstr
+ EXPORT read_hstr
EXPORT read_cnthctl
- EXPORT read_cntkctl
+ EXPORT read_cntkctl
EXPORT read_cntp_ctl
- EXPORT read_cntp_tval
+ EXPORT read_cntp_tval
EXPORT read_cnthp_ctl
EXPORT read_cnthp_tval
- EXPORT read_cnthp_cval
+ EXPORT read_cnthp_cval
EXPORT read_ttbcr
EXPORT read_nsacr
- EXPORT read_clidr
+ EXPORT read_clidr
EXPORT read_csselr
EXPORT read_ccsidr
EXPORT read_nmrr
EXPORT read_prrr
- EXPORT read_mvbar
+ EXPORT read_mvbar
EXPORT read_vbar
EXPORT read_hsr
EXPORT read_dfar
@@ -103,53 +103,53 @@
EXPORT read_dfsr
EXPORT read_ifsr
EXPORT read_adfsr
- EXPORT read_aifsr
- EXPORT read_l2ectlr
- EXPORT read_pmuserenr
- EXPORT read_pmintenset
- EXPORT read_pmintenclr
- EXPORT read_pmovsset
- EXPORT read_pmccntr
- EXPORT read_pmxevtyper
- EXPORT read_pmxevcntr
- EXPORT read_pmcr
- EXPORT read_pmcntenset
- EXPORT read_pmcntenclr
- EXPORT read_pmovsr
- EXPORT read_pmswinc
- EXPORT read_pmselr
- EXPORT read_pmceid0
- EXPORT read_pmceid1
-
- EXPORT write_l2ectlr
- EXPORT write_pmuserenr
- EXPORT write_pmintenset
- EXPORT write_pmintenclr
- EXPORT write_pmovsset
- EXPORT write_pmccntr
- EXPORT write_pmxevtyper
- EXPORT write_pmxevcntr
- EXPORT write_pmcr
- EXPORT write_pmcntenset
- EXPORT write_pmcntenclr
- EXPORT write_pmovsr
- EXPORT write_pmswinc
- EXPORT write_pmselr
- EXPORT write_pmceid0
- EXPORT write_pmceid1
+ EXPORT read_aifsr
+ EXPORT read_l2ectlr
+ EXPORT read_pmuserenr
+ EXPORT read_pmintenset
+ EXPORT read_pmintenclr
+ EXPORT read_pmovsset
+ EXPORT read_pmccntr
+ EXPORT read_pmxevtyper
+ EXPORT read_pmxevcntr
+ EXPORT read_pmcr
+ EXPORT read_pmcntenset
+ EXPORT read_pmcntenclr
+ EXPORT read_pmovsr
+ EXPORT read_pmswinc
+ EXPORT read_pmselr
+ EXPORT read_pmceid0
+ EXPORT read_pmceid1
+
+ EXPORT write_l2ectlr
+ EXPORT write_pmuserenr
+ EXPORT write_pmintenset
+ EXPORT write_pmintenclr
+ EXPORT write_pmovsset
+ EXPORT write_pmccntr
+ EXPORT write_pmxevtyper
+ EXPORT write_pmxevcntr
+ EXPORT write_pmcr
+ EXPORT write_pmcntenset
+ EXPORT write_pmcntenclr
+ EXPORT write_pmovsr
+ EXPORT write_pmswinc
+ EXPORT write_pmselr
+ EXPORT write_pmceid0
+ EXPORT write_pmceid1
EXPORT write_dacr
EXPORT write_prrr
- EXPORT write_nmrr
+ EXPORT write_nmrr
EXPORT write_ttbr0
EXPORT write_cpacr
EXPORT write_nsacr
EXPORT write_scr
EXPORT write_mvbar
EXPORT write_vbar
- EXPORT write_hvbar
+ EXPORT write_hvbar
EXPORT write_vmpidr
- EXPORT write_vmidr
- EXPORT write_csselr
+ EXPORT write_vmidr
+ EXPORT write_csselr
EXPORT write_hcr
EXPORT write_hdcr
EXPORT write_hcptr
@@ -157,29 +157,29 @@
EXPORT write_sctlr
EXPORT write_actlr
EXPORT write_ttbcr
- EXPORT write_cntfrq
+ EXPORT write_cntfrq
EXPORT write_cnthctl
- EXPORT write_cntkctl
+ EXPORT write_cntkctl
EXPORT write_cntp_ctl
- EXPORT write_cntp_tval
+ EXPORT write_cntp_tval
EXPORT write_cnthp_ctl
EXPORT write_cnthp_tval
- EXPORT write_cnthp_cval
+ EXPORT write_cnthp_cval
EXPORT write_hsctlr
EXPORT write_httbr
- EXPORT write_vttbr
+ EXPORT write_vttbr
EXPORT write_htcr
- EXPORT write_vtcr
- EXPORT write_hmair0
+ EXPORT write_vtcr
+ EXPORT write_hmair0
EXPORT write_hmair1
EXPORT write_dfar
EXPORT write_ifar
EXPORT write_dfsr
EXPORT write_ifsr
EXPORT write_adfsr
- EXPORT write_aifsr
-
-
+ EXPORT write_aifsr
+
+
MIDR_CPU_MASK EQU 0xff00fff0
AREA ACSR, CODE, ALIGN=5
@@ -194,7 +194,7 @@ wfi FUNCTION
wfi
bx lr
ENDFUNC
-
+
; WFI forever, and attempt to prevent speculative accesses starting
; FIQ and IRQ are assumed to be disabled
endless_wfi FUNCTION
@@ -234,8 +234,8 @@ copy_words FUNCTION
bne %b0
1 bx lr
ENDFUNC
-
-
+
+
appf_memcpy FUNCTION
cmp r2, #0
bxeq lr
@@ -264,26 +264,26 @@ write_cntfrq FUNCTION
mcr p15, 0, r0, c14, c0, 0
bx lr
ENDFUNC
-
+
read_cntpct FUNCTION
mrrc p15, 0, r0, r1, c14
bx lr
ENDFUNC
-
+
isb FUNCTION
isb
bx lr
- ENDFUNC
+ ENDFUNC
read_vmpidr FUNCTION
mrc p15, 4, r0, c0, c0, 5
bx lr
ENDFUNC
-
+
read_vmidr FUNCTION
mrc p15, 4, r0, c0, c0, 0
bx lr
- ENDFUNC
+ ENDFUNC
read_id_pfr0 FUNCTION
mrc p15, 0, r0, c0, c1, 0
@@ -299,12 +299,12 @@ read_id_dfr0 FUNCTION
mrc p15, 0, r0, c0, c1, 2
bx lr
ENDFUNC
-
+
read_id_afr0 FUNCTION
mrc p15, 0, r0, c0, c1, 3
bx lr
ENDFUNC
-
+
read_id_mmfr0 FUNCTION
mrc p15, 0, r0, c0, c1, 4
bx lr
@@ -314,17 +314,17 @@ read_id_mmfr1 FUNCTION
mrc p15, 0, r0, c0, c1, 5
bx lr
ENDFUNC
-
+
read_id_mmfr2 FUNCTION
mrc p15, 0, r0, c0, c1, 6
bx lr
- ENDFUNC
+ ENDFUNC
read_id_mmfr3 FUNCTION
mrc p15, 0, r0, c0, c1, 7
bx lr
ENDFUNC
-
+
read_id_isar0 FUNCTION
mrc p15, 0, r0, c0, c2, 0
bx lr
@@ -334,17 +334,17 @@ read_id_isar1 FUNCTION
mrc p15, 0, r0, c0, c2, 1
bx lr
ENDFUNC
-
+
read_id_isar2 FUNCTION
mrc p15, 0, r0, c0, c2, 2
bx lr
ENDFUNC
-
+
read_id_isar3 FUNCTION
mrc p15, 0, r0, c0, c2, 3
bx lr
ENDFUNC
-
+
read_id_isar4 FUNCTION
mrc p15, 0, r0, c0, c2, 4
bx lr
@@ -353,8 +353,8 @@ read_id_isar4 FUNCTION
read_id_isar5 FUNCTION
mrc p15, 0, r0, c0, c2, 5
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_ctr FUNCTION
mrc p15, 0, r0, c0, c0, 1
bx lr
@@ -368,12 +368,12 @@ read_tcmtr FUNCTION
read_tlbtr FUNCTION
mrc p15, 0, r0, c0, c0, 3
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_aidr FUNCTION
mrc p15, 1, r0, c0, c0, 7
bx lr
- ENDFUNC
+ ENDFUNC
read_dacr FUNCTION
mrc p15, 0, r0, c3, c0, 0
@@ -395,7 +395,7 @@ read_cpacr FUNCTION
mrc p15, 0, r0, c1, c0, 2
bx lr
ENDFUNC
-
+
write_cpacr FUNCTION
mcr p15, 0, r0, c1, c0, 2
bx lr
@@ -419,7 +419,7 @@ read_scr FUNCTION
write_scr FUNCTION
mcr p15, 0, r0, c1, c1, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
@@ -441,32 +441,32 @@ write_mvbar FUNCTION
ENDFUNC
write_vbar FUNCTION
- mcr p15, 0, r0, c12, c0, 0
+ mcr p15, 0, r0, c12, c0, 0
bx lr
ENDFUNC
write_hvbar FUNCTION
- mcr p15, 4, r0, c12, c0, 0
+ mcr p15, 4, r0, c12, c0, 0
bx lr
- ENDFUNC
+ ENDFUNC
read_mvbar FUNCTION
mrc p15, 0, r0, c12, c0, 1
bx lr
ENDFUNC
-
+
read_vbar FUNCTION
- mrc p15, 0, r0, c12, c0, 0
+ mrc p15, 0, r0, c12, c0, 0
bx lr
ENDFUNC
-
+
read_cpuid FUNCTION
mrc p15, 0, r0, c0, c0, 5
ands r0, r0, #0xf
bx lr
ENDFUNC
-read_clusterid FUNCTION
+read_clusterid FUNCTION
mrc p15, 0, r0, c0, c0, 5
lsr r0, r0, #0x8
ands r0, r0, #0xf
@@ -478,32 +478,32 @@ write_ttbr0 FUNCTION
mcr p15, 0, r0, c7, c5, 6
mcr p15, 0, r0, c8, c7, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
read_ttbcr FUNCTION
mrc p15, 0, r0, c2, c0, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_ttbcr FUNCTION
mcr p15, 0, r0, c2, c0, 2
bx lr
- ENDFUNC
+ ENDFUNC
write_vmpidr FUNCTION
mcr p15, 4, r0, c0, c0, 5
isb
bx lr
ENDFUNC
-
+
write_vmidr FUNCTION
mcr p15, 4, r0, c0, c0, 0
isb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_vtcr FUNCTION
mrc p15, 4, r0, c2, c1, 2
bx lr
@@ -518,16 +518,16 @@ read_hdcr FUNCTION
mrc p15, 4, r0, c1, c1, 1
bx lr
ENDFUNC
-
+
read_hcptr FUNCTION
mrc p15, 4, r0, c1, c1, 2
bx lr
ENDFUNC
-
+
read_hstr FUNCTION
mrc p15, 4, r0, c1, c1, 3
bx lr
- ENDFUNC
+ ENDFUNC
read_httbr FUNCTION
mrrc p15, 4, r0, r1, c2
@@ -537,25 +537,25 @@ read_httbr FUNCTION
read_vttbr FUNCTION
mrrc p15, 6, r0, r1, c2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_hcr FUNCTION
mcr p15, 4, r0, c1, c1, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
write_hdcr FUNCTION
mcr p15, 4, r0, c1, c1, 1
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_hcptr FUNCTION
mcr p15, 4, r0, c1, c1, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_hstr FUNCTION
mcr p15, 4, r0, c1, c1, 3
bx lr
@@ -566,7 +566,7 @@ write_httbr FUNCTION
mcr p15, 0, r0, c7, c5, 6
mcr p15, 0, r0, c8, c7, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
@@ -575,10 +575,10 @@ write_vttbr FUNCTION
mcr p15, 0, r0, c7, c5, 6
mcr p15, 0, r0, c8, c7, 0
dsb
- isb
+ isb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_htcr FUNCTION
mcr p15, 4, r0, c2, c0, 2
bx lr
@@ -587,7 +587,7 @@ write_htcr FUNCTION
write_vtcr FUNCTION
mcr p15, 4, r0, c2, c1, 2
bx lr
- ENDFUNC
+ ENDFUNC
write_hmair0 FUNCTION
mcr p15, 4, r0, c10, c2, 0
@@ -597,20 +597,20 @@ write_hmair0 FUNCTION
write_hmair1 FUNCTION
mcr p15, 4, r0, c10, c2, 1
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_nsacr FUNCTION
mrc p15, 0, r0, c1, c1, 2
bx lr
ENDFUNC
read_l2ctlr FUNCTION
- mrc p15, 1, r0, c9, c0, 2
+ mrc p15, 1, r0, c9, c0, 2
bx lr
ENDFUNC
read_l2ectlr FUNCTION
- mrc p15, 1, r0, c9, c0, 3
+ mrc p15, 1, r0, c9, c0, 3
bx lr
ENDFUNC
@@ -618,71 +618,71 @@ read_pmuserenr FUNCTION
mrc p15, 0, r0, c9, c14, 0
bx lr
ENDFUNC
-
+
read_pmintenset FUNCTION
mrc p15, 0, r0, c9, c14, 1
bx lr
- ENDFUNC
+ ENDFUNC
read_pmintenclr FUNCTION
mrc p15, 0, r0, c9, c14, 2
bx lr
ENDFUNC
-
+
read_pmovsset FUNCTION
mrc p15, 0, r0, c9, c14, 3
bx lr
ENDFUNC
-
+
read_pmccntr FUNCTION
mrc p15, 0, r0, c9, c13, 0
bx lr
ENDFUNC
-
+
read_pmxevtyper FUNCTION
mrc p15, 0, r0, c9, c13, 1
bx lr
ENDFUNC
-
+
read_pmxevcntr FUNCTION
mrc p15, 0, r0, c9, c13, 2
bx lr
ENDFUNC
-
+
read_pmcr FUNCTION
mrc p15, 0, r0, c9, c12, 0
bx lr
ENDFUNC
-
+
read_pmcntenset FUNCTION
mrc p15, 0, r0, c9, c12, 1
bx lr
ENDFUNC
-
+
read_pmcntenclr FUNCTION
mrc p15, 0, r0, c9, c12, 2
bx lr
ENDFUNC
-
+
read_pmovsr FUNCTION
mrc p15, 0, r0, c9, c12, 3
bx lr
ENDFUNC
-
+
read_pmswinc FUNCTION
mrc p15, 0, r0, c9, c12, 4
bx lr
ENDFUNC
-
+
read_pmselr FUNCTION
mrc p15, 0, r0, c9, c12, 5
bx lr
ENDFUNC
-
+
read_pmceid0 FUNCTION
mrc p15, 0, r0, c9, c12, 6
bx lr
- ENDFUNC
+ ENDFUNC
read_pmceid1 FUNCTION
mrc p15, 0, r0, c9, c12, 7
@@ -690,7 +690,7 @@ read_pmceid1 FUNCTION
ENDFUNC
write_l2ectlr FUNCTION
- mcr p15, 1, r0, c9, c0, 3
+ mcr p15, 1, r0, c9, c0, 3
bx lr
ENDFUNC
@@ -698,78 +698,78 @@ write_pmuserenr FUNCTION
mcr p15, 0, r0, c9, c14, 0
bx lr
ENDFUNC
-
+
write_pmintenset FUNCTION
mcr p15, 0, r0, c9, c14, 1
bx lr
- ENDFUNC
+ ENDFUNC
write_pmintenclr FUNCTION
mcr p15, 0, r0, c9, c14, 2
bx lr
ENDFUNC
-
+
write_pmovsset FUNCTION
mcr p15, 0, r0, c9, c14, 3
bx lr
ENDFUNC
-
+
write_pmccntr FUNCTION
mcr p15, 0, r0, c9, c13, 0
bx lr
ENDFUNC
-
+
write_pmxevtyper FUNCTION
mcr p15, 0, r0, c9, c13, 1
bx lr
ENDFUNC
-
+
write_pmxevcntr FUNCTION
mcr p15, 0, r0, c9, c13, 2
bx lr
ENDFUNC
-
+
write_pmcr FUNCTION
mcr p15, 0, r0, c9, c12, 0
bx lr
ENDFUNC
-
+
write_pmcntenset FUNCTION
mcr p15, 0, r0, c9, c12, 1
bx lr
ENDFUNC
-
+
write_pmcntenclr FUNCTION
mcr p15, 0, r0, c9, c12, 2
bx lr
ENDFUNC
-
+
write_pmovsr FUNCTION
mcr p15, 0, r0, c9, c12, 3
bx lr
ENDFUNC
-
+
write_pmswinc FUNCTION
mcr p15, 0, r0, c9, c12, 4
bx lr
ENDFUNC
-
+
write_pmselr FUNCTION
mcr p15, 0, r0, c9, c12, 5
bx lr
ENDFUNC
-
+
write_pmceid0 FUNCTION
mcr p15, 0, r0, c9, c12, 6
bx lr
- ENDFUNC
+ ENDFUNC
write_pmceid1 FUNCTION
mcr p15, 0, r0, c9, c12, 7
bx lr
- ENDFUNC
-
-read_sctlr FUNCTION
+ ENDFUNC
+
+read_sctlr FUNCTION
mrc p15, 0, r0, c1, c0, 0
bx lr
ENDFUNC
@@ -781,18 +781,18 @@ write_sctlr FUNCTION
bx lr
ENDFUNC
-read_hsctlr FUNCTION
+read_hsctlr FUNCTION
mrc p15, 4, r0, c1, c0, 0
bx lr
ENDFUNC
read_hdfar FUNCTION
- mrc p15, 4, r0, c6, c0, 0
+ mrc p15, 4, r0, c6, c0, 0
bx lr
ENDFUNC
-
+
read_hpfar FUNCTION
- mrc p15, 4, r0, c6, c0, 4
+ mrc p15, 4, r0, c6, c0, 4
bx lr
ENDFUNC
@@ -804,10 +804,10 @@ read_hsr FUNCTION
write_hsctlr FUNCTION
mcr p15, 4, r0, c1, c0, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
-
+
read_cnthctl FUNCTION
mrc p15, 4, r0, c14, c1, 0
bx lr
@@ -816,7 +816,7 @@ read_cnthctl FUNCTION
read_cntkctl FUNCTION
mrc p15, 0, r0, c14, c1, 0
bx lr
- ENDFUNC
+ ENDFUNC
read_cnthp_cval FUNCTION
mrrc p15, 6, r0, r1, c14
@@ -832,16 +832,16 @@ read_cntp_tval FUNCTION
mrc p15, 0, r0, c14, c2, 0
bx lr
ENDFUNC
-
+
read_cntp_ctl FUNCTION
mrc p15, 0, r0, c14, c2, 1
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_cnthp_ctl FUNCTION
mrc p15, 4, r0, c14, c2, 1
bx lr
- ENDFUNC
+ ENDFUNC
write_cnthctl FUNCTION
mcr p15, 4, r0, c14, c1, 0
@@ -851,65 +851,65 @@ write_cnthctl FUNCTION
write_cntkctl FUNCTION
mcr p15, 0, r0, c14, c1, 0
bx lr
- ENDFUNC
+ ENDFUNC
write_cntp_tval FUNCTION
mcr p15, 0, r0, c14, c2, 0
isb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_cntp_ctl FUNCTION
mcr p15, 0, r0, c14, c2, 1
dsb
- isb
+ isb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_cnthp_cval FUNCTION
mcrr p15, 6, r0, r1, c14
dsb
- isb
+ isb
bx lr
ENDFUNC
write_cnthp_tval FUNCTION
mcr p15, 4, r0, c14, c2, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
-
+
write_cnthp_ctl FUNCTION
mcr p15, 4, r0, c14, c2, 1
dsb
- isb
+ isb
bx lr
- ENDFUNC
-
-read_clidr FUNCTION
+ ENDFUNC
+
+read_clidr FUNCTION
mrc p15, 1, r0, c0, c0, 1 ; read clidr
bx lr
ENDFUNC
-read_ccsidr FUNCTION
+read_ccsidr FUNCTION
mrc p15, 1, r0, c0, c0, 0 ; read ccsidr
bx lr
ENDFUNC
-read_csselr FUNCTION
+read_csselr FUNCTION
mrc p15, 2, r0, c0, c0, 0 ; read csselr
bx lr
- ENDFUNC
-
-write_csselr FUNCTION
+ ENDFUNC
+
+write_csselr FUNCTION
mcr p15, 2, r0, c0, c0, 0 ; read csselr
dsb
- isb
+ isb
bx lr
- ENDFUNC
-
-read_actlr FUNCTION
+ ENDFUNC
+
+read_actlr FUNCTION
mrc p15, 0, r0, c1, c0, 1
bx lr
ENDFUNC
@@ -917,64 +917,64 @@ read_actlr FUNCTION
write_actlr FUNCTION
mcr p15, 0, r0, c1, c0, 1
dsb
- isb
+ isb
bx lr
ENDFUNC
-read_prrr FUNCTION
+read_prrr FUNCTION
mrc p15, 0, r0, c10, c2, 0
bx lr
ENDFUNC
-read_nmrr FUNCTION
+read_nmrr FUNCTION
mrc p15, 0, r0, c10, c2, 1
bx lr
ENDFUNC
-write_prrr FUNCTION
+write_prrr FUNCTION
mcr p15, 0, r0, c10, c2, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
-write_nmrr FUNCTION
+write_nmrr FUNCTION
mcr p15, 0, r0, c10, c2, 1
dsb
- isb
+ isb
bx lr
- ENDFUNC
+ ENDFUNC
read_dfar FUNCTION
mrc p15, 0, r0, c6, c0, 0
bx lr
ENDFUNC
-
+
read_ifar FUNCTION
- mrc p15, 0, r0, c6, c0, 2
+ mrc p15, 0, r0, c6, c0, 2
bx lr
ENDFUNC
-
+
read_dfsr FUNCTION
- mrc p15, 0, r0, c5, c0, 0
+ mrc p15, 0, r0, c5, c0, 0
bx lr
ENDFUNC
-
+
read_ifsr FUNCTION
- mrc p15, 0, r0, c5, c0, 1
+ mrc p15, 0, r0, c5, c0, 1
bx lr
ENDFUNC
-
+
read_adfsr FUNCTION
mrc p15, 0, r0, c5, c1, 0
bx lr
ENDFUNC
-
+
read_aifsr FUNCTION
- mrc p15, 0, r0, c5, c1, 1
+ mrc p15, 0, r0, c5, c1, 1
bx lr
ENDFUNC
-
+
write_dfar FUNCTION
mcr p15, 0, r0, c6, c0, 0
dsb
@@ -985,38 +985,38 @@ write_dfar FUNCTION
write_ifar FUNCTION
mcr p15, 0, r0, c6, c0, 2
dsb
- isb
+ isb
bx lr
ENDFUNC
write_dfsr FUNCTION
mcr p15, 0, r0, c5, c0, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
write_ifsr FUNCTION
mcr p15, 0, r0, c5, c0, 1
dsb
- isb
+ isb
bx lr
ENDFUNC
-
+
write_adfsr FUNCTION
mcr p15, 0, r0, c5, c1, 0
dsb
- isb
+ isb
bx lr
ENDFUNC
-
+
write_aifsr FUNCTION
mcr p15, 0, r0, c5, c1, 1
dsb
- isb
+ isb
bx lr
ENDFUNC
-
+
read_cbar FUNCTION
mrc p15, 4, r0, c15, c0, 0 ; Read Configuration Base Address Register
bx lr
@@ -1033,7 +1033,7 @@ dsb FUNCTION
dsb
bx lr
ENDFUNC
-
+
va_to_pa FUNCTION ; Note: assumes conversion will be successful!
mov r1, r0
mcr p15, 0, r0, c7, c8, 1 ; Priv Write Current World VA-PA
diff --git a/acsr/v7.s b/acsr/v7.s
index f7fe4c5..afec824 100644
--- a/acsr/v7.s
+++ b/acsr/v7.s
@@ -1,24 +1,24 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
- ; Redistribution and use in source and binary forms, with
- ; or without modification, are permitted provided that the
- ; following conditions are met:
- ;
- ; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
- ; following disclaimer.
- ;
- ; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
- ; and/or other materials provided with the distribution.
- ;
- ; Neither the name of ARM nor the names of its
- ; contributors may be used to endorse or promote products
- ; derived from this software without specific prior written
- ; permission.
- ;
+ ;
+ ; Redistribution and use in source and binary forms, with
+ ; or without modification, are permitted provided that the
+ ; following conditions are met:
+ ;
+ ; Redistributions of source code must retain the above
+ ; copyright notice, this list of conditions and the
+ ; following disclaimer.
+ ;
+ ; Redistributions in binary form must reproduce the
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
+ ; and/or other materials provided with the distribution.
+ ;
+ ; Neither the name of ARM nor the names of its
+ ; contributors may be used to endorse or promote products
+ ; derived from this software without specific prior written
+ ; permission.
+ ;
EXPORT save_performance_monitors
EXPORT restore_performance_monitors
@@ -45,7 +45,7 @@
EXPORT restore_generic_timer
EXPORT save_fault_status
- EXPORT restore_fault_status
+ EXPORT restore_fault_status
AREA APPF, CODE
@@ -62,7 +62,7 @@ MODE_HYP EQU 0x1A
TTBCR_EAE EQU (1<<31) ; Are we using LPAE?
-PFR0_THUMB_EE_SUPPORT EQU (1<<12)
+PFR0_THUMB_EE_SUPPORT EQU (1<<12)
save_performance_monitors FUNCTION
@@ -73,14 +73,14 @@ save_performance_monitors FUNCTION
bic r1,r8,#1
mcr p15,0,r1,c9,c12,0 ; disable counter updates from here
isb ; 0b0 => PMCR<0>
- mrc p15,0,r9,c9,c12,5 ; PMon: Event Counter Selection Register
+ mrc p15,0,r9,c9,c12,5 ; PMon: Event Counter Selection Register
mrc p15,0,r10,c9,c12,1 ; PMon: Count Enable Set Reg
stm r0!, {r8-r10}
- mrc p15,0,r8,c9,c12,2 ; PMon: Count Enable Clear Register
+ mrc p15,0,r8,c9,c12,2 ; PMon: Count Enable Clear Register
mrc p15,0,r9,c9,c13,0 ; PMon: Cycle Counter Register
mrc p15,0,r10,c9,c12,3 ; PMon: Overflow flag Status Register
stm r0!, {r8-r10}
- mrc p15,0,r8,c9,c14,1 ; PMon: Interrupt Enable Set Registern
+ mrc p15,0,r8,c9,c14,1 ; PMon: Interrupt Enable Set Registern
mrc p15,0,r9,c9,c14,2 ; PMon: Interrupt Enable Clear Register
stm r0!, {r8-r9}
mrc p15,0,r8,c9,c12,0 ; Read PMon Control Register
@@ -120,15 +120,15 @@ restore_performance_monitors FUNCTION
tst r12, r12
beq %f20
- add r1,r0,#32 ; r1 now points to the 1st saved event counter
+ add r1,r0,#32 ; r1 now points to the 1st saved event counter
;; Restore counters
mov r6,#0
10 mcr p15,0,r6,c9,c12,5 ; PMon: select CounterN
isb
- ldm r1!, {r3,r4} ; Read saved data
+ ldm r1!, {r3,r4} ; Read saved data
mcr p15,0,r3,c9,c13,1 ; PMon: restore Event Type Register
mcr p15,0,r4,c9,c13,2 ; PMon: restore Event Counter Register
- add r6,r6,#1 ; increment index
+ add r6,r6,#1 ; increment index
cmps r6,r12
bne %b10
@@ -154,13 +154,13 @@ restore_performance_monitors FUNCTION
;; Restore left regs but PMCR
add r1,r0,#4 ; r1 now points to the PMSELR
ldm r1!,{r3,r4}
- mcr p15,0,r3,c9,c12,5 ; PMon: Event Counter Selection Reg
+ mcr p15,0,r3,c9,c12,5 ; PMon: Event Counter Selection Reg
mcr p15,0,r4,c9,c12,1 ; PMon: Count Enable Set Reg
ldm r1!, {r3,r4}
mcr p15,0,r4,c9,c13,0 ; PMon: Cycle Counter Register
ldm r1!,{r3,r4}
mcr p15,0,r3,c9,c14,2 ; PMon: Interrupt Enable Clear Reg
- mcr p15,0,r4,c9,c14,1 ; PMon: Interrupt Enable Set Reg
+ mcr p15,0,r4,c9,c14,1 ; PMon: Interrupt Enable Set Reg
ldr r3,[r1]
isb
ldr r0,[r0]
@@ -180,20 +180,20 @@ save_banked_registers FUNCTION
str sp,[r0], #4 ; save the User SP
str lr,[r0], #4 ; save the User LR
cps #MODE_ABT ; switch to Abort mode
- str sp,[r0], #4 ; save the current SP
- mrs r3,SPSR
+ str sp,[r0], #4 ; save the current SP
+ mrs r3,SPSR
stm r0!,{r3,lr} ; save the current SPSR, LR
cps #MODE_UND ; switch to Undefined mode
str sp,[r0], #4 ; save the current SP
- mrs r3,SPSR
+ mrs r3,SPSR
stm r0!,{r3,lr} ; save the current SPSR, LR
cps #MODE_IRQ ; switch to IRQ mode
str sp,[r0], #4 ; save the current SP
- mrs r3,SPSR
+ mrs r3,SPSR
stm r0!,{r3,lr} ; save the current SPSR, LR
cps #MODE_FIQ ; switch to FIQ mode
str SP,[r0], #4 ; save the current SP
- mrs r3,SPSR
+ mrs r3,SPSR
stm r0!,{r8-r12,lr} ; save the current SPSR,r8-r12,LR
msr CPSR_cxsf, r2 ; switch back to original mode
bx lr
@@ -243,23 +243,23 @@ restore_banked_registers FUNCTION
cmp r3, #MODE_HYP ; instructions to restore the banked registers
beq rest_in_hyp ; without changing the mode
- cps #MODE_SYS ; switch to System mode
- ldr sp,[r0],#4 ; restore the User SP
+ cps #MODE_SYS ; switch to System mode
+ ldr sp,[r0],#4 ; restore the User SP
ldr lr,[r0],#4 ; restore the User LR
- cps #MODE_ABT ; switch to Abort mode
- ldr sp,[r0],#4 ; restore the current SP
- ldm r0!,{r3,lr} ; restore the current LR
+ cps #MODE_ABT ; switch to Abort mode
+ ldr sp,[r0],#4 ; restore the current SP
+ ldm r0!,{r3,lr} ; restore the current LR
msr SPSR_fsxc,r3 ; restore the current SPSR
- cps #MODE_UND ; switch to Undefined mode
- ldr sp,[r0],#4 ; restore the current SP
- ldm r0!,{r3,lr} ; restore the current LR
+ cps #MODE_UND ; switch to Undefined mode
+ ldr sp,[r0],#4 ; restore the current SP
+ ldm r0!,{r3,lr} ; restore the current LR
msr SPSR_fsxc,r3 ; restore the current SPSR
- cps #MODE_IRQ ; switch to IRQ mode
- ldr sp,[r0],#4 ; restore the current SP
- ldm r0!,{r3,lr} ; restore the current LR
+ cps #MODE_IRQ ; switch to IRQ mode
+ ldr sp,[r0],#4 ; restore the current SP
+ ldm r0!,{r3,lr} ; restore the current LR
msr SPSR_fsxc,r3 ; restore the current SPSR
- cps #MODE_FIQ ; switch to FIQ mode
- ldr sp,[r0],#4 ; restore the current SP
+ cps #MODE_FIQ ; switch to FIQ mode
+ ldr sp,[r0],#4 ; restore the current SP
ldm r0!,{r8-r12,lr} ; restore the current r8-r12,LR
msr SPSR_fsxc,r4 ; restore the current SPSR
msr CPSR_cxsf, r2 ; switch back to original mode
@@ -274,53 +274,53 @@ rest_in_hyp
msr SPSR_und, r2
msr LR_und, r3
- ldm r0!, {r1-r3}
+ ldm r0!, {r1-r3}
msr SP_abt, r1
msr SPSR_abt, r2
msr LR_abt, r3
- ldm r0!, {r1-r3}
+ ldm r0!, {r1-r3}
msr SP_svc, r1
msr SPSR_svc, r2
msr LR_svc, r3
- ldm r0!, {r1-r3}
+ ldm r0!, {r1-r3}
msr SP_irq, r1
msr SPSR_irq, r2
msr LR_irq, r3
-
+
ldm r0!, {r1-r3}
msr SP_fiq, r1
msr SPSR_fiq, r2
- msr LR_fiq, r3
+ msr LR_fiq, r3
ldm r0!, {r1-r3}
msr r8_fiq, r1
msr r9_fiq, r2
- msr r10_fiq, r3
+ msr r10_fiq, r3
ldm r0!, {r1-r2}
msr r11_fiq, r1
msr r12_fiq, r2
-
- bx lr
+
+ bx lr
ENDFUNC
-
+
save_cp15 FUNCTION
; CSSELR Cache Size Selection Register
mrc p15,2,r3,c0,c0,0
str r3,[r0], #4
- ; IMPLEMENTATION DEFINED - proprietary features:
+ ; IMPLEMENTATION DEFINED - proprietary features:
; (CP15 register 15, TCM support, lockdown support, etc.)
; NOTE: IMP DEF registers might have save and restore order that relate
- ; to other CP15 registers or logical grouping requirements and can
+ ; to other CP15 registers or logical grouping requirements and can
; therefore occur at any point in this sequence.
bx lr
ENDFUNC
-
+
restore_cp15 FUNCTION
; CSSELR Cache Size Selection Register
ldr r3,[r0], #4
@@ -328,7 +328,7 @@ restore_cp15 FUNCTION
bx lr
ENDFUNC
-
+
; Function called with two arguments:
; r0 contains address to store control registers
; r1 is non-zero if we are Secure
@@ -354,16 +354,16 @@ save_control_registers FUNCTION
; The next two registers are only present if ThumbEE is implemented
mrc p15, 0, r1, c0, c1, 0 ; Read ID_PFR0
tst r1, #PFR0_THUMB_EE_SUPPORT
- mrcne p14,6,r1,c0,c0,0 ; TEECR
+ mrcne p14,6,r1,c0,c0,0 ; TEECR
mrcne p14,6,r2,c1,c0,0 ; TEEHBR
stmne r0!, {r1, r2}
-
+
mrc p14,7,r1,c1,c0,0 ; JOSCR
mrc p14,7,r2,c2,c0,0 ; JMCR
stm r0!, {r1, r2}
bx lr
ENDFUNC
-
+
; Function called with two arguments:
; r0 contains address to read control registers
@@ -455,7 +455,7 @@ restore_mmu FUNCTION
bx lr
ENDFUNC
-
+
save_mpu FUNCTION
mrc p15, 0, r1, c0, c0, 4 ; Read MPUIR
and r1, r1, #0xff00
@@ -475,7 +475,7 @@ save_mpu FUNCTION
20 bx lr
ENDFUNC
-
+
restore_mpu FUNCTION
mrc p15, 0, r1, c0, c0, 4 ; Read MPUIR
and r1, r1, #0xff00
@@ -500,7 +500,7 @@ save_vfp FUNCTION
; FPU state save/restore.
; FPSID,MVFR0 and MVFR1 don't get serialized/saved (Read Only).
mrc p15,0,r3,c1,c0,2 ; CPACR allows CP10 and CP11 access
- ORR r2,r3,#0xF00000
+ ORR r2,r3,#0xF00000
mcr p15,0,r2,c1,c0,2
isb
mrc p15,0,r2,c1,c0,2
@@ -509,7 +509,7 @@ save_vfp FUNCTION
beq %f0
movs r2, #0
b %f2
-
+
0 ; Save configuration registers and enable.
vmrs r12,FPEXC
str r12,[r0],#4 ; Save the FPEXC
@@ -518,7 +518,7 @@ save_vfp FUNCTION
vmsr FPEXC,r2
vmrs r2,FPSCR
str r2,[r0],#4 ; Save the FPSCR
- ; Store the VFP-D16 registers.
+ ; Store the VFP-D16 registers.
vstm r0!, {D0-D15}
; Check for Advanced SIMD/VFP-D32 support
vmrs r2,MVFR0
@@ -528,7 +528,7 @@ save_vfp FUNCTION
; Store the Advanced SIMD/VFP-D32 additional registers.
vstm r0!, {D16-D31}
- ; IMPLEMENTATION DEFINED: save any subarchitecture defined state
+ ; IMPLEMENTATION DEFINED: save any subarchitecture defined state
; NOTE: Don't change the order of the FPEXC and CPACR restores
1
vmsr FPEXC,r12 ; Restore the original En bit of FPU.
@@ -543,12 +543,12 @@ restore_vfp FUNCTION
; serialized (RO).
; Modify CPACR to allow CP10 and CP11 access
mrc p15,0,r1,c1,c0,2
- ORR r2,r1,#0x00F00000
+ ORR r2,r1,#0x00F00000
mcr p15,0,r2,c1,c0,2
; Enable FPU access to save/restore the rest of registers.
ldr r2,=0x40000000
vmsr FPEXC, r2
- ; Recover FPEXC and FPSCR. These will be restored later.
+ ; Recover FPEXC and FPSCR. These will be restored later.
ldm r0!,{r3,r12}
; Restore the VFP-D16 registers.
vldm r0!, {D0-D15}
@@ -561,12 +561,12 @@ restore_vfp FUNCTION
; Store the Advanced SIMD/VFP-D32 additional registers.
vldm r0!, {D16-D31}
- ; IMPLEMENTATION DEFINED: restore any subarchitecture defined state
+ ; IMPLEMENTATION DEFINED: restore any subarchitecture defined state
0 ; Restore configuration registers and enable.
; Restore FPSCR _before_ FPEXC since FPEXC could disable FPU
; and make setting FPSCR unpredictable.
- vmsr FPSCR,r12
+ vmsr FPSCR,r12
vmsr FPEXC,r3 ; Restore FPEXC after FPSCR
; Restore CPACR
mcr p15,0,r1,c1,c0,2
@@ -577,7 +577,7 @@ restore_vfp FUNCTION
; If r1 is 0, we assume that the OS is not using the Virtualization extensions,
; and that the warm boot code will set up CNTHCTL correctly. If r1 is non-zero
; then CNTHCTL is saved and restored
- ; CNTP_CVAL will be preserved as it is in the always-on domain.
+ ; CNTP_CVAL will be preserved as it is in the always-on domain.
save_generic_timer FUNCTION
mrc p15,0,r2,c14,c2,1 ; read CNTP_CTL
diff --git a/big-little/Makefile b/big-little/Makefile
index e866ba0..066f48f 100644
--- a/big-little/Makefile
+++ b/big-little/Makefile
@@ -114,11 +114,11 @@ OBJS += cci.o
ASFLAGS = --apcs /inter --cpu=Eagle --keep --fpu=none \
$(SWITCHER_ASFLAGS) \
- $(VIRTUALISOR_ASFLAGS)
+ $(VIRTUALISOR_ASFLAGS)
CFLAGS = -Iinclude -I. -Ivirtualisor/include -Ivirtualisor/cpus/a7/include \
-Ivirtualisor/cpus/a15/include -I../acsr \
- --cpu=Eagle --fpu=none -O2 $(SWITCHER_CFLAGS) $(VIRTUALISOR_CFLAGS)
+ --cpu=Eagle --fpu=none -O2 $(SWITCHER_CFLAGS) $(VIRTUALISOR_CFLAGS)
ifdef DEBUG
CFLAGS += -g -O0
@@ -165,12 +165,12 @@ clean:
$(Q)rm -f $(LISTFILE)
$(Q)rm -f $(SECURE_LISTFILE)
-dump:
+dump:
@echo " OBJDUMP"
fromelf --text -c bl.axf > bl.dump
fromelf --text -c bl_sec.axf > bl_sec.dump
-%.o: %.s
+%.o: %.s
@echo " AS $<"
$(Q)$(AS) $(ASFLAGS) $< -o $@
@@ -212,11 +212,11 @@ secure_resets.o: secure_resets.c
@echo " CC $<"
$(Q)$(CC) $(SECURE_CFLAGS) -c $< -o $@
-monmode_vectors.o: monmode_vectors.s
+monmode_vectors.o: monmode_vectors.s
@echo " AS $<"
$(Q)$(AS) $(SECURE_ASFLAGS) $< -o $@
-flat_pagetable.o: flat_pagetable.s
+flat_pagetable.o: flat_pagetable.s
@echo " AS $<"
$(Q)$(AS) $(SECURE_ASFLAGS) $< -o $@
diff --git a/big-little/bl-sec.scf.template b/big-little/bl-sec.scf.template
index 490e9b3..935f4b0 100644
--- a/big-little/bl-sec.scf.template
+++ b/big-little/bl-sec.scf.template
@@ -49,5 +49,5 @@ LOAD_REGION1 HIBASE00000 NOCOMPRESS ALIGN 4096 65536
SEC_DATA +0x0
{
*(+ZI,+RW)
- }
+ }
}
diff --git a/big-little/bl.scf.template b/big-little/bl.scf.template
index b58fbf7..b76bc79 100644
--- a/big-little/bl.scf.template
+++ b/big-little/bl.scf.template
@@ -33,5 +33,5 @@ LOAD_REGION1 HIBASE0D000 NOCOMPRESS ALIGN 4096 65536
BL_DATA +0x0
{
*(+ZI,+RW)
- }
+ }
}
diff --git a/big-little/common/cci.c b/big-little/common/cci.c
index 3c47e19..b71ebe0 100644
--- a/big-little/common/cci.c
+++ b/big-little/common/cci.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "misc.h"
diff --git a/big-little/common/hyp_setup.c b/big-little/common/hyp_setup.c
index d15654a..2287017 100644
--- a/big-little/common/hyp_setup.c
+++ b/big-little/common/hyp_setup.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "context.h"
@@ -69,15 +69,15 @@ void bl_rest_init(void)
config_uart();
if (switcher) {
- /*
+ /*
* Ask the secure world to initialise its context.
* Not required when "always on"
*/
smc(SMC_SEC_INIT, 0, 0);
- /*
+ /*
* Since we are using the shared vgic, we need to map
- * the cpuids to the cpu interfaces as there is no
+ * the cpuids to the cpu interfaces as there is no
* longer a 1:1 mapping
*/
map_cpuif(cluster_id, cpu_id);
@@ -88,7 +88,7 @@ void bl_rest_init(void)
/*
* Only one cpu should enable the CCI while the other
- * cpus wait.
+ * cpus wait.
*/
if (first_cpu == cpu_id && cluster_id == host_cluster) {
write32(A7_SL_IFACE_BASE + SNOOP_CTLR_REG, 0x3);
diff --git a/big-little/common/hyp_vectors.s b/big-little/common/hyp_vectors.s
index e727b5f..b2e5426 100644
--- a/big-little/common/hyp_vectors.s
+++ b/big-little/common/hyp_vectors.s
@@ -1,25 +1,25 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA HypVectors, CODE, READONLY, ALIGN=5
PRESERVE8
@@ -29,7 +29,7 @@
IMPORT guestos_state
IMPORT guestos_state_size
IMPORT get_sp
- IMPORT output_string
+ IMPORT output_string
IMPORT virt_dead
IMPORT SetupVirtExtPageTables
IMPORT Enable2ndStagePageTables
@@ -42,7 +42,7 @@
IMPORT bl_rest_init
IMPORT hyp_l1_pagetable
IMPORT find_restore_op_type
-
+
EXPORT vectors
EXPORT iabt_entry
EXPORT dabt_entry
@@ -50,46 +50,46 @@
EXPORT svc_hyp_entry
EXPORT fiq_entry
EXPORT bl_setup
- EXPORT hyp_warm_reset_handler
+ EXPORT hyp_warm_reset_handler
-
- MACRO
+
+ MACRO
hyp_entry $reg
SUB $reg, $reg, #72
; ---------------------------------------------------
- ; Save all GP registers
+ ; Save all GP registers
; Save User mode LR which the HYP mode will use now.
; Save HYP mode ELR & SPSR in case we are re-entrant
- ; Pass saved context as argument to next bit of code
- ; ---------------------------------------------------
+ ; Pass saved context as argument to next bit of code
+ ; ---------------------------------------------------
STMIA $reg, {r0-r12}
MRS r0, ELR_hyp
MRS r1, SPSR
- MRS r2, LR_usr
+ MRS r2, LR_usr
ADD r3, $reg, #60
STMIA r3, {r0-r2}
MEND
- MACRO
+ MACRO
hyp_exit $reg
ADD r3, $reg, #60
- LDMIA r3, {r0-r2}
+ LDMIA r3, {r0-r2}
MSR ELR_hyp, r0
MSR SPSR_cxsf, r1
MSR LR_usr, r2
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; We do need to clear the BTAC though since it is
; virtually-addressed with no regard for the NS bit
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
MCR p15, 0, r0, c7, c5, 6 ; invalidate BTAC
-
+
LDMIA $reg, {r0-r12}
ADD $reg, $reg, #72
- ERET
+ ERET
MEND
-
+
IF {FALSE}
dabort_string
DCB " Virtualisor-DAB!\n", 0
@@ -106,19 +106,19 @@ fiq_string
unused_string
DCB " Virtualisor-UNU!\n", 0
- ALIGN
+ ALIGN
ENDIF
; ----------------------------------------------------
- ; Defines for enabling HYP mode MMU
+ ; Defines for enabling HYP mode MMU
; ----------------------------------------------------
ENABLE EQU 0x1
DISABLE EQU 0x0
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; HMAIR attributes relevant to us
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
HMAIR_INNER_WB_RWA_MEM EQU 0x0f
HMAIR_OUTER_WB_RWA_MEM EQU 0xf0
HMAIR_DEVICE_MEM EQU 0x04
@@ -128,17 +128,17 @@ IDX0 EQU (HMAIR_DEVICE_MEM << 0)
IDX1 EQU ((HMAIR_INNER_WB_RWA_MEM :OR: HMAIR_OUTER_WB_RWA_MEM) << 8)
IDX2 EQU (HMAIR_SO_MEM << 16)
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; HSCTLR defines
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
ICACHE EQU (ENABLE << 12)
ALIGN EQU (ENABLE << 1)
DCACHE EQU (ENABLE << 2)
MMU EQU (ENABLE << 0)
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; HTCR defines
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
CR_C_WBWA EQU 0x1
CR_OUTER_SH EQU 0x2
CR_INNER_SH EQU 0x3
@@ -149,7 +149,7 @@ T0SZ EQU (CR_ADDR_SPC_4GB << 0)
IRGN0 EQU (CR_C_WBWA << 8)
ORGN0 EQU (CR_C_WBWA << 10)
SH0 EQU (CR_INNER_SH << 12)
-
+
vectors
B bl_setup ; reset
B undef_entry ; undef
@@ -161,75 +161,75 @@ vectors
B fiq_entry ; fiq
bl_setup FUNCTION
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; This function is called after a reset. 'r0-r3' can
; be corrupted after a cold reset.
; Its also assumed that we are taking part in coherency
- ; already (entered in secure world)
- ; ----------------------------------------------------
+ ; already (entered in secure world)
+ ; ----------------------------------------------------
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Enable Caches
; ----------------------------------------------------
- mrc p15, 4, r0, c1, c0, 0
+ mrc p15, 4, r0, c1, c0, 0
orr r0, #ICACHE
orr r0, #ALIGN
orr r0, #DCACHE
- mcr p15, 4, r0, c1, c0, 0
+ mcr p15, 4, r0, c1, c0, 0
isb
-
+
msr elr_hyp, lr
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Give yourself a stack without enabling the MMU so
; that the pagetables can be created in C code.
- ; ----------------------------------------------------
-
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
+
+ ; ----------------------------------------------------
; Allocate the HYP stack first up to do greater things
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
ldr r0, =guestos_state
ldr r1, =guestos_state_size
ldr r1, [r1]
- bl get_sp
+ bl get_sp
mov sp, r0
-
- ; ----------------------------------------------------
+
+ ; ----------------------------------------------------
; Create the 2nd stage and HYP mode page tables
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
bl SetupVirtExtPageTables
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Enable the HYP mode MMU before doing anything further
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
ldr r0, =hyp_l1_pagetable
MOV r1, #0
- mcrr p15, 4, r0, r1, c2
+ mcrr p15, 4, r0, r1, c2
ldr r0, =(IDX2 :OR: IDX1 :OR: IDX0)
mcr p15, 4, r0, c10, c2, 0
- ldr r0, =(EAE :OR: SH0 :OR: ORGN0 :OR: IRGN0 :OR: T0SZ)
+ ldr r0, =(EAE :OR: SH0 :OR: ORGN0 :OR: IRGN0 :OR: T0SZ)
mcr p15, 4, r0, c2, c0, 2
- mrc p15, 4, r0, c1, c0, 0
+ mrc p15, 4, r0, c1, c0, 0
orr r0, #MMU
- mcr p15, 4, r0, c1, c0, 0
+ mcr p15, 4, r0, c1, c0, 0
dsb
- isb
-
- ; ----------------------------------------------------
+ isb
+
+ ; ----------------------------------------------------
; Initialise the remaining bits now that the MMU is on
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
hyp_entry sp
bl bl_rest_init
hyp_exit sp
ENDFUNC
-
+
IF {FALSE}
common_abt
PUSH {lr}
BL hexword ; print r0
-
+
MRC p15, 0, r0, c5, c0, 0 ; DFSR
BL hexword
@@ -244,39 +244,39 @@ common_abt
MRC p15, 4, r0, c6, c0, 2 ; HIFAR
BL hexword
-
+
MRC p15, 4, r0, c6, c0, 4 ; HPFAR
BL hexword
-
- POP {lr}
+
+ POP {lr}
BX lr
dabt_entry
- MOV r0, lr ; save lr, just in case it's interesting
+ MOV r0, lr ; save lr, just in case it's interesting
IF {FALSE}
- BL common_abt
+ BL common_abt
ENDIF
LDR r0, =dabort_string
BL output_string
B dead
-
+
iabt_entry
- MOV r0, lr ; save lr, just in case it's interesting
+ MOV r0, lr ; save lr, just in case it's interesting
IF {FALSE}
- BL common_abt
+ BL common_abt
ENDIF
LDR r0, =pabort_string
BL output_string
- B dead
+ B dead
undef_entry
- MOV r0, lr ; save lr, just in case it's interesting
+ MOV r0, lr ; save lr, just in case it's interesting
IF {FALSE}
- BL common_abt
+ BL common_abt
ENDIF
LDR r0, =undef_string
- BL output_string
- B dead
+ BL output_string
+ B dead
dead
B dead
@@ -286,20 +286,20 @@ dabt_entry
B dabt_entry
iabt_entry
- B iabt_entry
-
+ B iabt_entry
+
undef_entry
- B undef_entry
-
-irq_entry
+ B undef_entry
+
+irq_entry
hyp_entry sp
; ----------------------------------------------------
; Pass SP as arg if we intend to initiate a switchover
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
MOV r0, sp
- BL handle_interrupt
- hyp_exit sp
-
+ BL handle_interrupt
+ hyp_exit sp
+
svc_hyp_entry
B svc_hyp_entry
@@ -311,64 +311,64 @@ hvc_entry
; ----------------------------------------------------
; Check if we have an HVC call. The Switcher handles
- ; it first. If its unable to, its passed to the
+ ; it first. If its unable to, its passed to the
; Virtualisor. It should be possible to cascade an HVC
- ; across the two, but not for the time being.
- ; ----------------------------------------------------
- MOV r0, sp
+ ; across the two, but not for the time being.
+ ; ----------------------------------------------------
+ MOV r0, sp
BL HandleVirtualisor
-out
+out
hyp_exit sp
hyp_warm_reset_handler FUNCTION
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Enable Caches
; ----------------------------------------------------
- mrc p15, 4, r0, c1, c0, 0
+ mrc p15, 4, r0, c1, c0, 0
orr r0, #ICACHE
orr r0, #ALIGN
orr r0, #DCACHE
- mcr p15, 4, r0, c1, c0, 0
+ mcr p15, 4, r0, c1, c0, 0
isb
-
- ; ----------------------------------------------------
+
+ ; ----------------------------------------------------
; Enable the HYP mode MMU before doing anything further
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
ldr r0, =hyp_l1_pagetable
MOV r1, #0
- mcrr p15, 4, r0, r1, c2
+ mcrr p15, 4, r0, r1, c2
ldr r0, =(IDX2 :OR: IDX1 :OR: IDX0)
mcr p15, 4, r0, c10, c2, 0
- ldr r0, =(EAE :OR: SH0 :OR: ORGN0 :OR: IRGN0 :OR: T0SZ)
+ ldr r0, =(EAE :OR: SH0 :OR: ORGN0 :OR: IRGN0 :OR: T0SZ)
mcr p15, 4, r0, c2, c0, 2
- mrc p15, 4, r0, c1, c0, 0
+ mrc p15, 4, r0, c1, c0, 0
orr r0, #MMU
- mcr p15, 4, r0, c1, c0, 0
+ mcr p15, 4, r0, c1, c0, 0
dsb
- isb
+ isb
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Initialise the remaining bits now that the MMU is on
- ; ----------------------------------------------------
-
+ ; ----------------------------------------------------
+
; ----------------------------------------------------
; Allocate the HYP stack first up to do greater things
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
ldr r0, =guestos_state
ldr r1, =guestos_state_size
ldr r1, [r1]
- bl get_sp
+ bl get_sp
mov sp, r0
; ----------------------------------------------------
; Initialise the HVBAR
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
adr r0, vectors
mcr p15, 4, r0, c12, c0, 0
; ----------------------------------------------------
; Initialise the 2nd stage translations for NS PL0/1
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
bl Enable2ndStagePageTables
; ----------------------------------------------------
@@ -382,6 +382,6 @@ hyp_warm_reset_handler FUNCTION
hyp_exit sp
ENDFUNC
-
+
END
diff --git a/big-little/common/pagetable_setup.c b/big-little/common/pagetable_setup.c
index e394b15..eeaf7f1 100644
--- a/big-little/common/pagetable_setup.c
+++ b/big-little/common/pagetable_setup.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/* ----------------------------------------------------------------------------
@@ -47,14 +47,14 @@ typedef struct {
#define HYP_VA_START HYP_PA_START
#define HYP_VA_END HYP_PA_END
-/*
- * First level pagetables to cover 512GB.
+/*
+ * First level pagetables to cover 512GB.
* Only first 4GB used
*/
unsigned long long hyp_l1_pagetable[512] __attribute__ ((aligned(4096)));
-/*
- * Second level pagetables to cover each GB.
+/*
+ * Second level pagetables to cover each GB.
* Arranged contiguously for ease
*/
unsigned long long hyp_l2_pagetable[4][512] __attribute__ ((aligned(16384)));
@@ -75,7 +75,7 @@ unsigned long long stage2_l2_pagetable[4][512] __attribute__ ((aligned(16384)));
/*
* Allocate one Level 3 page table which will
* route guestOS physical cpu interface accesses
- * to the virtual cpu interface. Align it to the
+ * to the virtual cpu interface. Align it to the
* 4K boundary.
*/
unsigned long long stage2_l3_cpuif_pt[512] __attribute__ ((aligned(4096)));
@@ -144,12 +144,12 @@ unsigned long long stage2_l3_kfscb_pt[512] __attribute__ ((aligned(4096)));
* Dcache clean by MVA ops added to ensure that main memory is updated prior to
* the first page table walk upon entry into NS world. This is potentially an AEM
* bug as the descriptors should be picked from the cache itself since the VTCR
- * marks PTWs as cacheable.
+ * marks PTWs as cacheable.
* It would be better to collect the writes and then perform the clean rather then
* picking them up individually.
*/
/*
- * Map the physical cpu interface to the virtual
+ * Map the physical cpu interface to the virtual
* cpu interface for OS use.
*/
static void CreateL3PageTable(four_kb_pt_desc * l3_mapping, unsigned level,
@@ -166,7 +166,7 @@ static void CreateL3PageTable(four_kb_pt_desc * l3_mapping, unsigned level,
unsigned long long *l2_pt_addr = 0;
unsigned long long *l3_pt_addr = l3_mapping->pt_addr;
- /*
+ /*
* Indices calculated above are relative to the GB or MB they
* belong to rather than an offset of 0x0. e.g. for the 2mb index
* index = (address >> 21) - (<number of 2MBs in 1GB> x <this GB index>)
@@ -273,8 +273,8 @@ void CreateHypModePageTables(void)
}
}
- /*
- * Create a mapping for a device page to be used
+ /*
+ * Create a mapping for a device page to be used
* for Locks, Events & anything that is shared when both
* the clusters are executing at the same time.
*/
@@ -294,7 +294,7 @@ void EnableHypModePageTables(void)
/* Update the HTTBR */
write_httbr((unsigned long long)hyp_l1_pagetable);
- /*
+ /*
* Setup the HMAIR0 register.
* [7:0] = Device memory
* [15:8] = Normal memory, Inner and outer cacheable, WBWA
@@ -303,7 +303,7 @@ void EnableHypModePageTables(void)
IDX1(HMAIR_INNER_WB_RWA_MEM | HMAIR_OUTER_WB_RWA_MEM) |
IDX0(HMAIR_DEVICE_MEM));
- /*
+ /*
* Set the HTCR.
* Pagetables are Normal memory, Inner/Outer shareable, Inner/Outer WBWA
*/
@@ -327,7 +327,7 @@ void Create2ndStagePageTables(void)
/*
* Create the flat mapped 2nd stage page tables.
* This should be done only once. The remaining
- * cpus can share the mappings and wait while
+ * cpus can share the mappings and wait while
* this is being done.
*/
for (one_gb_index = 0; one_gb_index < 4; one_gb_index++)
@@ -385,8 +385,8 @@ void Create2ndStagePageTables(void)
l3_desc.pt_addr = stage2_l3_cpuif_pt;
Add4KMapping(&l3_desc);
- /*
- * Create a mapping for a device page to be used
+ /*
+ * Create a mapping for a device page to be used
* for Locks, Events & anything that is shared when both
* the clusters are executing at the same time.
*/
@@ -412,7 +412,7 @@ void Create2ndStagePageTables(void)
void Enable2ndStagePageTables(void)
{
- /*
+ /*
* Set the VTCR to:
* Normal memory outer shareable, Device memory shareable
* Outer and Inner WBWA
@@ -426,9 +426,9 @@ void Enable2ndStagePageTables(void)
write_hcr(read_hcr() | HCR_VM);
- /*
+ /*
* TODO: We do not need a synchronization barrier here as we
- * are not yet executing out of NS PL0 & PL1 and there will be
+ * are not yet executing out of NS PL0 & PL1 and there will be
* a barrier at some point before that.
*/
return;
@@ -446,7 +446,7 @@ void SetupVirtExtPageTables(void)
if (!switcher)
abs_cpuid = abs_cpuid(cpu_id, cluster_id);
- /*
+ /*
* First cpu creates the pagetables after
* a cold reset. Reused by all cpus across
* warm resets.
@@ -456,7 +456,7 @@ void SetupVirtExtPageTables(void)
/*
* While switching its possible that the host cluster
* is brought out of reset first. Hence, the first
- * cpu of whichever cluster reaches here does the
+ * cpu of whichever cluster reaches here does the
* pagetable setup
*/
if (cpu_id == first_cpu) {
@@ -474,7 +474,7 @@ void SetupVirtExtPageTables(void)
} else {
/*
- * Any cluster can do the initialisation as long as
+ * Any cluster can do the initialisation as long as
* only one of them does it.
*/
if (cpu_id == first_cpu && cluster_id == host_cluster) {
diff --git a/big-little/common/vgic_handle.c b/big-little/common/vgic_handle.c
index 960f97d..627653b 100644
--- a/big-little/common/vgic_handle.c
+++ b/big-little/common/vgic_handle.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "int_master.h"
@@ -37,7 +37,7 @@ extern unsigned check_trigger(unsigned, unsigned);
/*
* Flag to make the interrupt handling code aware that
* each interrupt needs to be checked for it being a
- * signal to switch to the other cluster
+ * signal to switch to the other cluster
*/
unsigned async_switchover = ASYNC_SWITCH;
@@ -120,14 +120,14 @@ vm_context *handle_interrupt(vm_context * context)
keep_trigger_alive();
/*
- * Special case IPIs, since we need the source CPU ID
+ * Special case IPIs, since we need the source CPU ID
*/
if (i < 16) {
unsigned type = get_hyp_ipi(cpu_if, i);
src_cpu = (status >> 10) & INTACK_CPUID_MASK;
- /*
+ /*
* SGI Ack actually returns the source cpu interface
* which needs to be mapped to the apt cpuid.
*/
@@ -150,7 +150,7 @@ vm_context *handle_interrupt(vm_context * context)
/* Check whether we have been requested to switchover */
case IPI_CLUSTER_SWITCH:
- /*
+ /*
* switch_cluster() takes the first_cpu as its arg. Since
* all the cores are expected to power down, its reasonable
* to assume cpu0 is the first cpu and will take care of
@@ -195,7 +195,7 @@ vm_context *handle_interrupt(vm_context * context)
write32(GIC_IC_PHY_BASE + GICC_PRIODROP, i);
/*
- * Priority reg = (interrupt no. / 4) x 4 bytes.
+ * Priority reg = (interrupt no. / 4) x 4 bytes.
* Priority index = interrupt no. % 4 x 8 bits (8 bits for each priority value)
* Prioriity value = Priority reg >> Priority index
*/
diff --git a/big-little/common/vgic_setup.c b/big-little/common/vgic_setup.c
index 15625cf..e4c960a 100644
--- a/big-little/common/vgic_setup.c
+++ b/big-little/common/vgic_setup.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "int_master.h"
@@ -29,9 +29,9 @@
/*
* The Big-little spftware needs to bother itself with
- * bareminimal vGIC configuration.
+ * bareminimal vGIC configuration.
*
- * 1. Distributor. Security bits should be taken care of
+ * 1. Distributor. Security bits should be taken care of
* by the boot firmaware after a cold reset. Big-little
* code should initialise private interrupts as secure
* after a warm reset.
@@ -39,11 +39,11 @@
* 2. Physical Cpu interface. Initialised by us after
* both warm and cold reset.
*
- * 3. Virtual CPU interface (HYP view). Initialised by us
+ * 3. Virtual CPU interface (HYP view). Initialised by us
* after cold reset & restored after warm reset.
*
- * 4. Virtual CPU interface (CPU view). Initialised by
- * the payload software after cold reset and restored by
+ * 4. Virtual CPU interface (CPU view). Initialised by
+ * the payload software after cold reset and restored by
* us after a warm reset.
*/
static void gic_cpuinit()
@@ -58,7 +58,7 @@ static void gic_cpuinit()
void SetupVGIC(unsigned warm_reset)
{
- /*
+ /*
* Initialise the HYP view Virtual CPU interface after
* a cold reset
*/
@@ -75,7 +75,7 @@ void SetupVGIC(unsigned warm_reset)
/*
* TODO: Barriers not needed here as there will surely
- * be others further down the line before virtual
+ * be others further down the line before virtual
* exceptions are used.
*/
return;
diff --git a/big-little/common/vgiclib.c b/big-little/common/vgiclib.c
index 9acee57..d05f81a 100644
--- a/big-little/common/vgiclib.c
+++ b/big-little/common/vgiclib.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "vgiclib.h"
@@ -30,7 +30,7 @@
extern unsigned get_cpuinfo(unsigned);
/*
- * Manage overflowints somehow.. static pool with recycling allocators.
+ * Manage overflowints somehow.. static pool with recycling allocators.
*/
#define MAXOVERFLOWINTS 200
@@ -284,8 +284,8 @@ void vgic_init(void)
free_overflowint(&(theoverflowints[cpuid][i]), cpuid);
}
- /*
- * Find the number of List registers
+ /*
+ * Find the number of List registers
* TODO: Will not work if individual cpus can have different number
* of list registers across clusters. Needs to be detected for each
* access then.
@@ -299,7 +299,7 @@ void vgic_init(void)
}
/*
- * Abstracted entry accessor functions. Work for live or saved state
+ * Abstracted entry accessor functions. Work for live or saved state
*/
static void set_vgic_entry(unsigned int descr, unsigned int slot)
{
@@ -312,7 +312,7 @@ static unsigned int get_vgic_entry(unsigned int slot)
}
/*
- * Abstracted status accessor functions, as above
+ * Abstracted status accessor functions, as above
*/
static void set_vgic_status(unsigned int status)
{
@@ -337,13 +337,13 @@ static void set_vgic_queue_entry(struct gic_cpuif *cpuif, unsigned int descr)
unsigned cpuid = read_cpuid();
/*
- * If we are queuing something and there is currently no queue, set the interrupt bit
+ * If we are queuing something and there is currently no queue, set the interrupt bit
*/
if (!(cpuif->overflow))
set_vgic_status(get_vgic_status() | 0x2);
/*
- * Determine insertion point, might be the end of the list
+ * Determine insertion point, might be the end of the list
*/
for (oflowh = &(cpuif->overflow); *oflowh; oflowh = &((*oflowh)->next))
if ((*oflowh)->priority > pri)
@@ -377,7 +377,7 @@ void vgic_savestate(unsigned int cpu)
/* Clear the saved bit index */
cur_elrsr &= ~(1 << i);
- /*
+ /*
* Invalidate the pending/active virtual interrupt. Since its a shared vGIC
* this irq will persist till the next switch and hence create a duplicate.
*/
@@ -451,12 +451,12 @@ void vgic_loadstate(unsigned int cpu)
* vgic_refresh: Generic "maintenance" routine for the VGIC
* *
* * This is called:
- * * - On maintenance interrupt. We get maintenance interrupts for
- * * two reasons:
+ * * - On maintenance interrupt. We get maintenance interrupts for
+ * * two reasons:
* * o Non-zero EOI skid. This routine deals with the skid and sets
* * the field to 0, quenching the interrupt source.
- * * o "Nearly empty" interrupt bit set, and nearly empty condition
- * * exists. This interrupt source is quenched by filling the
+ * * o "Nearly empty" interrupt bit set, and nearly empty condition
+ * * exists. This interrupt source is quenched by filling the
* * slots (and clearing the interrupt bit if the queue is now empty)
* * - When a new interrupt arrives and the cached "free slot" value
* * indicates that there are no free slots. We expect to scavenge some
@@ -476,31 +476,31 @@ void vgic_refresh(unsigned int cpu)
struct overflowint **oflowh, *oflowp;
/*
- * Grab a copy of the status.
+ * Grab a copy of the status.
*/
status = get_vgic_status();
/*
* "newstatus" is the value to be written back if needed. Whatever
- * * happens, we will clear the slipped EOI count by the time we are done
+ * * happens, we will clear the slipped EOI count by the time we are done
*/
newstatus = status & 0x07FFFFFF;
/*
- * See if there are any "slipped" EOIs
+ * See if there are any "slipped" EOIs
*/
i = (status >> 27) & 0x1F;
if (i) {
/*
- * If there are, let's deal with them.
+ * If there are, let's deal with them.
* *
* * We will walk through the list of queued interrupts, deactivating the
* * ACTIVE ones as needed until we either have no more slipped EOI's to
* * do or run out of queued interrupts. If we run out of queued
* * interrupts first, that's UNPREDICTABLE behaviour (and the fault of
* * the VM). In this case we will just ignore the surplus EOIs.
- * *
+ * *
* * After EOI'ing, we delete the entry if it was just ACTIVE or set it
* * to PENDING if it was PENDING+ACTIVE.
* *
@@ -513,14 +513,14 @@ void vgic_refresh(unsigned int cpu)
value = (*oflowh)->value;
if (value & VGIC_ENTRY_ACTIVE) {
/*
- * It's ACTIVE (or PENDING+ACTIVE)
+ * It's ACTIVE (or PENDING+ACTIVE)
*/
i--;
if (value & VGIC_ENTRY_HW) {
/*
* HW bit set, so we need to pass on an EOI. This doesn't ever happen
- * * for IPIs, so just pass on the 10-bit "Hardware ID"
+ * * for IPIs, so just pass on the 10-bit "Hardware ID"
*/
gic_deactivate_int((value >> 10) &
0x3FF);
@@ -528,12 +528,12 @@ void vgic_refresh(unsigned int cpu)
if (value & VGIC_ENTRY_PENDING) {
/*
- * It was PENDING+ACTIVE, clear the ACTIVE bit and move on
+ * It was PENDING+ACTIVE, clear the ACTIVE bit and move on
*/
(*oflowh)->value &= ~VGIC_ENTRY_ACTIVE;
} else {
/*
- * It was only ACTIVE, so we need to delete it..
+ * It was only ACTIVE, so we need to delete it..
*/
oflowp = *oflowh;
oflowh = &(oflowp->next);
@@ -541,7 +541,7 @@ void vgic_refresh(unsigned int cpu)
}
} else {
/*
- * It wasn't ACTIVE :( Try the next one.
+ * It wasn't ACTIVE :( Try the next one.
*/
oflowh = &((*oflowh)->next);
}
@@ -549,26 +549,26 @@ void vgic_refresh(unsigned int cpu)
}
/*
- * Now populate any spare slots with entries from the list (if any). Also fix up the free slot bitmap
+ * Now populate any spare slots with entries from the list (if any). Also fix up the free slot bitmap
*/
for (i = 0; i < hv_lr_count[cpu]; i++) {
value = get_vgic_entry(i);
if (value & 0x30000000) {
/*
- * This entry already contains a valid interrupt, skip
+ * This entry already contains a valid interrupt, skip
*/
continue;
}
/*
- * Not a valid interrupt
+ * Not a valid interrupt
*/
oflowp = cpuif->overflow;
if (oflowp) {
/*
* If there's a queue, move the top entry out of the queue and into
- * * this slot..
+ * * this slot..
*/
cpuif->overflow = oflowp->next;
@@ -576,21 +576,21 @@ void vgic_refresh(unsigned int cpu)
free_overflowint(oflowp, cpu);
} else {
/*
- * .. otherwise mark it as available.
+ * .. otherwise mark it as available.
*/
cpuif->freelist |= (1 << i);
}
}
/*
- * If we now don't have any overflow, clear the status bit
+ * If we now don't have any overflow, clear the status bit
*/
if (!(cpuif->overflow)) {
newstatus &= ~0x2;
}
/*
- * Refresh status if needed
+ * Refresh status if needed
*/
if (newstatus != status) {
set_vgic_status(newstatus);
@@ -613,7 +613,7 @@ void enqueue_interrupt(unsigned int descr, unsigned int cpu)
cpuif = &(cpuifs[cpu]);
/*
- * If there are no free slots, trigger a maintenance
+ * If there are no free slots, trigger a maintenance
*/
if (!(cpuif->freelist)) {
vgic_refresh(cpu);
@@ -621,7 +621,7 @@ void enqueue_interrupt(unsigned int descr, unsigned int cpu)
if (cpuif->freelist) {
/*
- * There is a free slot, use it.
+ * There is a free slot, use it.
*/
slot = cpuif->freelist; /* Take the free list.. */
slot &= (-slot); /* .. extract one set bit .. */
@@ -631,7 +631,7 @@ void enqueue_interrupt(unsigned int descr, unsigned int cpu)
set_vgic_entry(descr, slot);
} else {
/*
- * There are no free slots, we are either queuing this one or swapping another out
+ * There are no free slots, we are either queuing this one or swapping another out
*/
unsigned int pri = (descr >> 20) & 0xFF;
unsigned int minpri = 0;
@@ -640,14 +640,14 @@ void enqueue_interrupt(unsigned int descr, unsigned int cpu)
if (cpuif->overflow && cpuif->overflow->priority <= pri) {
/*
- * There are already queued interrupts with the same or higher priority, just queue this one
+ * There are already queued interrupts with the same or higher priority, just queue this one
*/
set_vgic_queue_entry(cpuif, descr);
return;
}
/*
- * Otherwise find the lowest priority entry..
+ * Otherwise find the lowest priority entry..
*/
for (i = 0; i < hv_lr_count[cpu]; i++) {
j = (get_vgic_entry(i) >> 20) & 0xFF; /* Get the priority for the current thing in this slot */
@@ -659,13 +659,13 @@ void enqueue_interrupt(unsigned int descr, unsigned int cpu)
if (minpri > pri) {
/*
- * If it's lower priority than this new one we kick it out
+ * If it's lower priority than this new one we kick it out
*/
set_vgic_queue_entry(cpuif, get_vgic_entry(minslot));
set_vgic_entry(descr, minslot);
} else {
/*
- * Otherwise just queue the new one
+ * Otherwise just queue the new one
*/
set_vgic_queue_entry(cpuif, descr);
}
diff --git a/big-little/include/arm.h b/big-little/include/arm.h
index 4f33cb5..7112cbc 100644
--- a/big-little/include/arm.h
+++ b/big-little/include/arm.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef ARM_H
diff --git a/big-little/include/bakery.h b/big-little/include/bakery.h
index 261acf3..cb37d38 100644
--- a/big-little/include/bakery.h
+++ b/big-little/include/bakery.h
@@ -1,30 +1,30 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef _BAKERY_H_
#define _BAKERY_H_
#define MAX_CPUS 4
-/*
+/*
* Bakery structure - declare/allocate one of these for each lock.
* A pointer to this struct is passed to the lock/unlock functions.
*/
diff --git a/big-little/include/bl.h b/big-little/include/bl.h
index 94e2fb0..eb5b11a 100644
--- a/big-little/include/bl.h
+++ b/big-little/include/bl.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __BL_H__
diff --git a/big-little/include/context.h b/big-little/include/context.h
index 4620393..38e591a 100644
--- a/big-little/include/context.h
+++ b/big-little/include/context.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __CONTEXT_H__
diff --git a/big-little/include/events.h b/big-little/include/events.h
index 4adc856..aa96098 100644
--- a/big-little/include/events.h
+++ b/big-little/include/events.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __EVENTS_H__
@@ -44,12 +44,12 @@
/* Cores have finished performing inbound headstart specific initialisation */
#define HS_DONE 6
/*
- * Holding pen to ensure that all other context is restored only after all
+ * Holding pen to ensure that all other context is restored only after all
* cpus have finished initialised local and global HYP mode context.
*/
#define HYP_CONTEXT_DONE 7
/*
- * Holding pen to ensure that all cores have setup the local and global
+ * Holding pen to ensure that all cores have setup the local and global
* virtualisor context before any one of them uses it
*/
#define VIRT_SETUP_DONE 8
diff --git a/big-little/include/gic_registers.h b/big-little/include/gic_registers.h
index 8a9ce9c..4d213e5 100644
--- a/big-little/include/gic_registers.h
+++ b/big-little/include/gic_registers.h
@@ -1,102 +1,102 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
+ */
+
+#ifndef __GIC_REGISTERS_H__
+#define __GIC_REGISTERS_H__
+
+#include "hyp_vmmap.h"
+
+#define MAX_INTS 256
+
+/* Distributor interface registers */
+#define GICD_CTL 0x0
+#define GICD_CTR 0x4
+#define GICD_SEC 0x80
+#define GICD_ENABLESET 0x100
+#define GICD_ENABLECLEAR 0x180
+#define GICD_PENDINGSET 0x200
+#define GICD_PENDINGCLEAR 0x280
+#define GICD_ACTIVESET 0x300
+#define GICD_ACTIVECLEAR 0x380
+#define GICD_PRI 0x400
+#define GICD_CPUS 0x800
+#define GICD_CONFIG 0xC00
+#define GICD_SW 0xF00
+#define GICD_CPENDSGIR 0xF10
+#define GICD_SPENDSGIR 0xF20
+
+/* Physical CPU Interface registers */
+#define GICC_CTL 0x0
+#define GICC_PRIMASK 0x4
+#define GICC_BP 0x8
+#define GICC_INTACK 0xC
+#define GICC_EOI 0x10
+#define GICC_RUNNINGPRI 0x14
+#define GICC_HIGHESTPEND 0x18
+#define GICC_DEACTIVATE 0x1000
+#define GICC_PRIODROP GICC_EOI
+
+/* HYP view virtual CPU Interface registers */
+#define GICH_CTL 0x0
+#define GICH_VTR 0x4
+#define GICH_ELRSR0 0x30
+#define GICH_ELRSR1 0x34
+#define GICH_APR0 0xF0
+#define GICH_LR_BASE 0x100
+
+/* GuestOS view virtual CPU Interface registers */
+#define GICV_CTL 0x0
+#define GICV_PRIMASK 0x4
+#define GICV_BP 0x8
+#define GICV_INTACK 0xC
+#define GICV_EOI 0x10
+#define GICV_RUNNINGPRI 0x14
+#define GICV_HIGHESTPEND 0x18
+#define GICV_DEACTIVATE 0x1000
+
+#define VGICH_HCR_EN 0x1
+#define VGICV_NS_EN 0x2
+
+#define GS_ENABLED 0x01
+#define GS_EDGE 0x02
+#define GIC_INTS 128
+#define GIC_PRIMASK 0xF8 /* 32 levels only */
+#define GIC_DISTENABLE 0x1
+#define GIC_CPUIFENABLE 0x2
+
+#define VGIC_PRI 0x200
+#define VGIC_LIST 0x100
+#define VGIC_CONTROL 0x0
+/*
+ * TODO:
+ * Current mechanism to find free slots uses unsigned ints
+ * and is thus restricted to storing just 32 free slots.
*/
-
-#ifndef __GIC_REGISTERS_H__
-#define __GIC_REGISTERS_H__
-
-#include "hyp_vmmap.h"
-
-#define MAX_INTS 256
-
-/* Distributor interface registers */
-#define GICD_CTL 0x0
-#define GICD_CTR 0x4
-#define GICD_SEC 0x80
-#define GICD_ENABLESET 0x100
-#define GICD_ENABLECLEAR 0x180
-#define GICD_PENDINGSET 0x200
-#define GICD_PENDINGCLEAR 0x280
-#define GICD_ACTIVESET 0x300
-#define GICD_ACTIVECLEAR 0x380
-#define GICD_PRI 0x400
-#define GICD_CPUS 0x800
-#define GICD_CONFIG 0xC00
-#define GICD_SW 0xF00
-#define GICD_CPENDSGIR 0xF10
-#define GICD_SPENDSGIR 0xF20
-
-/* Physical CPU Interface registers */
-#define GICC_CTL 0x0
-#define GICC_PRIMASK 0x4
-#define GICC_BP 0x8
-#define GICC_INTACK 0xC
-#define GICC_EOI 0x10
-#define GICC_RUNNINGPRI 0x14
-#define GICC_HIGHESTPEND 0x18
-#define GICC_DEACTIVATE 0x1000
-#define GICC_PRIODROP GICC_EOI
-
-/* HYP view virtual CPU Interface registers */
-#define GICH_CTL 0x0
-#define GICH_VTR 0x4
-#define GICH_ELRSR0 0x30
-#define GICH_ELRSR1 0x34
-#define GICH_APR0 0xF0
-#define GICH_LR_BASE 0x100
-
-/* GuestOS view virtual CPU Interface registers */
-#define GICV_CTL 0x0
-#define GICV_PRIMASK 0x4
-#define GICV_BP 0x8
-#define GICV_INTACK 0xC
-#define GICV_EOI 0x10
-#define GICV_RUNNINGPRI 0x14
-#define GICV_HIGHESTPEND 0x18
-#define GICV_DEACTIVATE 0x1000
-
-#define VGICH_HCR_EN 0x1
-#define VGICV_NS_EN 0x2
-
-#define GS_ENABLED 0x01
-#define GS_EDGE 0x02
-#define GIC_INTS 128
-#define GIC_PRIMASK 0xF8 /* 32 levels only */
-#define GIC_DISTENABLE 0x1
-#define GIC_CPUIFENABLE 0x2
-
-#define VGIC_PRI 0x200
-#define VGIC_LIST 0x100
-#define VGIC_CONTROL 0x0
-/*
- * TODO:
- * Current mechanism to find free slots uses unsigned ints
- * and is thus restricted to storing just 32 free slots.
- */
-#define VGIC_LISTENTRIES 64
-
-#define VGIC_ENTRY_HW 0x80000000
-#define VGIC_ENTRY_ACTIVE 0x20000000
-#define VGIC_ENTRY_ACTIVE_PENDING 0x30000000
-#define VGIC_ENTRY_PENDING 0x10000000
-
-#endif /* __GIC_REGISTERS_H__ */
-
+#define VGIC_LISTENTRIES 64
+
+#define VGIC_ENTRY_HW 0x80000000
+#define VGIC_ENTRY_ACTIVE 0x20000000
+#define VGIC_ENTRY_ACTIVE_PENDING 0x30000000
+#define VGIC_ENTRY_PENDING 0x10000000
+
+#endif /* __GIC_REGISTERS_H__ */
+
diff --git a/big-little/include/handler.h b/big-little/include/handler.h
index 7246b9e..b2466ae 100644
--- a/big-little/include/handler.h
+++ b/big-little/include/handler.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __HANDLER_H__
diff --git a/big-little/include/hvc.h b/big-little/include/hvc.h
index d0df974..ec9aa64 100644
--- a/big-little/include/hvc.h
+++ b/big-little/include/hvc.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __HVC_H__
diff --git a/big-little/include/hyp_types.h b/big-little/include/hyp_types.h
index 441320b..d40ca9c 100644
--- a/big-little/include/hyp_types.h
+++ b/big-little/include/hyp_types.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __HYP_TYPES_H__
diff --git a/big-little/include/hyp_vmmap.h b/big-little/include/hyp_vmmap.h
index aeeceae..c1b7b55 100644
--- a/big-little/include/hyp_vmmap.h
+++ b/big-little/include/hyp_vmmap.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __HYP_VMMAP_H__
diff --git a/big-little/include/int_master.h b/big-little/include/int_master.h
index f6fe603..cf55e8b 100644
--- a/big-little/include/int_master.h
+++ b/big-little/include/int_master.h
@@ -1,28 +1,28 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/*
* Master interrupt controller driver - talks to real IC and dispatches
- * * interrupts to slave ICs or monitor drivers as appropriate
+ * * interrupts to slave ICs or monitor drivers as appropriate
*/
#ifndef _INT_MASTER_H_
diff --git a/big-little/include/misc.h b/big-little/include/misc.h
index 4656d00..f5ada31 100644
--- a/big-little/include/misc.h
+++ b/big-little/include/misc.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef MISC_H
@@ -150,8 +150,8 @@
#define TTBR_SH 0x1
#define TTBR_WBWA 0x1
-/*
- * Bit definitions of Level 2 translation
+/*
+ * Bit definitions of Level 2 translation
* table entries.
*/
@@ -160,8 +160,8 @@
#define BLOCK_MAPPING 0x1
#define TABLE_MAPPING 0x3
-/*
- * Bit definitions of Level 3 translation
+/*
+ * Bit definitions of Level 3 translation
* table entries.
*/
@@ -236,7 +236,7 @@
#define read_cci_cntr(x) read32(CCI_PERF_CNT(x) + CNT_REG)
/*
* TODO:
- * Move platform specific definitions to the right places
+ * Move platform specific definitions to the right places
*/
#define KFSCB_BASE 0x60000000
@@ -270,7 +270,7 @@
/*
* Map the 4 tubes to the Secure
- * & non-secure worlds
+ * & non-secure worlds
*/
#define SEC_TUBE0 KFS_TUBE0
#define SEC_TUBE1 KFS_TUBE1
@@ -384,8 +384,8 @@
#define CRN_C9 0x9
#define CRN_C15 0xf
-/*
- * Opcode2 definitions in the corresponding cp15 instruction
+/*
+ * Opcode2 definitions in the corresponding cp15 instruction
*/
#define MIDR 0x0
#define CTR 0x1
diff --git a/big-little/include/traps.h b/big-little/include/traps.h
index 2d36210..2782b61 100644
--- a/big-little/include/traps.h
+++ b/big-little/include/traps.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __TRAPS_H__
diff --git a/big-little/include/vgiclib.h b/big-little/include/vgiclib.h
index 5cbca56..a520a3f 100644
--- a/big-little/include/vgiclib.h
+++ b/big-little/include/vgiclib.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef VGICLIB_H
diff --git a/big-little/include/virt_helpers.h b/big-little/include/virt_helpers.h
index 1388e35..c399430 100644
--- a/big-little/include/virt_helpers.h
+++ b/big-little/include/virt_helpers.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef _VIRT_HELPERS_H_
diff --git a/big-little/lib/bakery.c b/big-little/lib/bakery.c
index 068ac0d..7984168 100644
--- a/big-little/lib/bakery.c
+++ b/big-little/lib/bakery.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/*
diff --git a/big-little/lib/tube.c b/big-little/lib/tube.c
index 8ab693e..1db7d4e 100644
--- a/big-little/lib/tube.c
+++ b/big-little/lib/tube.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "misc.h"
diff --git a/big-little/lib/uart.c b/big-little/lib/uart.c
index 26d00e5..a08694e 100644
--- a/big-little/lib/uart.c
+++ b/big-little/lib/uart.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/*
diff --git a/big-little/lib/virt_events.c b/big-little/lib/virt_events.c
index ec5c468..d6d7c68 100644
--- a/big-little/lib/virt_events.c
+++ b/big-little/lib/virt_events.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "events.h"
diff --git a/big-little/lib/virt_helpers.s b/big-little/lib/virt_helpers.s
index eb3c909..ebf4721 100644
--- a/big-little/lib/virt_helpers.s
+++ b/big-little/lib/virt_helpers.s
@@ -1,57 +1,57 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
+ ; permission.
+ ;
IMPORT read_actlr
IMPORT write_actlr
-
+
EXPORT smc
EXPORT dcisw
- EXPORT dccsw
- EXPORT dccisw
- EXPORT read_lr
+ EXPORT dccsw
+ EXPORT dccisw
+ EXPORT read_lr
EXPORT read_sp
EXPORT write_sp
- EXPORT write_lr
+ EXPORT write_lr
EXPORT panic
EXPORT spin_lock
- EXPORT spin_trylock
- EXPORT spin_unlock
+ EXPORT spin_trylock
+ EXPORT spin_unlock
EXPORT virt_memset
EXPORT hyp_save
EXPORT num_secondaries
EXPORT virt_dead
- EXPORT get_sp
+ EXPORT get_sp
EXPORT disable_coherency
EXPORT enable_coherency
EXPORT inv_tlb_all
- EXPORT inv_tlb_mva
- EXPORT inv_icache_all
+ EXPORT inv_tlb_mva
+ EXPORT inv_icache_all
EXPORT inv_bpred_is
EXPORT inv_bpred_all
EXPORT inv_icache_mva_pou
EXPORT inv_dcache_mva_poc
EXPORT cln_dcache_mva_pou
- EXPORT cln_dcache_mva_poc
+ EXPORT cln_dcache_mva_poc
EXPORT cache_maint_op
; Cache maintenance op types
@@ -60,9 +60,9 @@ CLN EQU 0x1
CLN_INV EQU 0x2
AREA |.text|, CODE
-
+
read_lr FUNCTION
- ; Save r1
+ ; Save r1
push {r1}
and r0, r0, #0x1f
; Read the current cpsr
@@ -71,18 +71,18 @@ read_lr FUNCTION
; Check if the desired lr is of the current mode
cmp r0, r1
moveq r0, LR
- beq read_lr_out
+ beq read_lr_out
; Check if desired lr is of user mode
cmp r0, #0x10
mrseq r0, LR_usr
beq read_lr_out
- ; Check if desired lr is of supervisor mode
+ ; Check if desired lr is of supervisor mode
cmp r0, #0x13
mrseq r0, LR_svc
read_lr_out
pop {r1}
bx lr
- ENDFUNC
+ ENDFUNC
write_lr FUNCTION
; Save r2
@@ -94,12 +94,12 @@ write_lr FUNCTION
; Check if the lr is of the current mode
cmp r0, r2
moveq LR, r1
- beq write_lr_out
+ beq write_lr_out
; Check if the lr is of user mode
cmp r0, #0x10
msreq LR_usr, r1
beq write_lr_out
- ; Check if the lr is of supervisor mode
+ ; Check if the lr is of supervisor mode
cmp r0, #0x13
msreq LR_svc, r1
write_lr_out
@@ -108,7 +108,7 @@ write_lr_out
ENDFUNC
read_sp FUNCTION
- ; Save r1
+ ; Save r1
push {r1}
and r0, r0, #0x1f
; Read the current cpsr
@@ -117,30 +117,30 @@ read_sp FUNCTION
; Check if the desired sp is of the current mode
cmp r0, r1
moveq r0, SP
- beq read_sp_out
+ beq read_sp_out
; Check if desired sp is of user mode
cmp r0, #0x10
mrseq r0, SP_usr
beq read_sp_out
- ; Check if desired sp is of supervisor mode
+ ; Check if desired sp is of supervisor mode
cmp r0, #0x13
mrseq r0, SP_svc
beq read_sp_out
- ; Check if desired sp is of irq mode
+ ; Check if desired sp is of irq mode
cmp r0, #0x12
mrseq r0, SP_irq
- beq read_sp_out
- ; Check if desired sp is of supervisor mode
+ beq read_sp_out
+ ; Check if desired sp is of supervisor mode
cmp r0, #0x1a
mrseq r0, SP_hyp
beq read_sp_out
- ; Check if desired sp is of monitor mode
+ ; Check if desired sp is of monitor mode
cmp r0, #0x16
- mrseq r0, SP_mon
+ mrseq r0, SP_mon
read_sp_out
pop {r1}
bx lr
- ENDFUNC
+ ENDFUNC
write_sp FUNCTION
; Save r2
@@ -152,32 +152,32 @@ write_sp FUNCTION
; Check if the sp is of the current mode
cmp r0, r2
moveq SP, r1
- beq write_sp_out
+ beq write_sp_out
; Check if the sp is of user mode
cmp r0, #0x10
msreq SP_usr, r1
beq write_sp_out
- ; Check if the sp is of supervisor mode
+ ; Check if the sp is of supervisor mode
cmp r0, #0x13
msreq SP_svc, r1
beq write_sp_out
- ; Check if the sp is of irq mode
+ ; Check if the sp is of irq mode
cmp r0, #0x12
msreq SP_irq, r1
- beq write_sp_out
- ; Check if the sp is of hyp mode
+ beq write_sp_out
+ ; Check if the sp is of hyp mode
cmp r0, #0x1a
msreq SP_hyp, r1
beq write_sp_out
- ; Check if the sp is of monitor mode
+ ; Check if the sp is of monitor mode
cmp r0, #0x16
- msreq SP_mon, r1
+ msreq SP_mon, r1
write_sp_out
pop {r2}
bx lr
- ENDFUNC
+ ENDFUNC
- ALIGN 4
+ ALIGN 4
;--------------------------------------------------------
; spin_lock
@@ -193,7 +193,7 @@ sl_tryloop
MCR p15, 0, r0, c7, c10, 4
bx lr
ENDFUNC
-
+
;--------------------------------------------------------
; spin_lock
;--------------------------------------------------------
@@ -204,10 +204,10 @@ spin_trylock FUNCTION
STREXEQ r1, r2, [r0]
MOV r0, r1
MCR p15, 0, r0, c7, c10, 4
- bx lr
+ bx lr
ENDFUNC
-
- ALIGN 4
+
+ ALIGN 4
;--------------------------------------------------------
; spin_unlock
@@ -216,36 +216,36 @@ spin_unlock FUNCTION
MOV r1, #0
STR r1, [r0]
MCR p15, 0, r0, c7, c10, 4
- bx lr
+ bx lr
ENDFUNC
-
- ALIGN 4
+
+ ALIGN 4
;--------------------------------------------------------
; panic
;--------------------------------------------------------
panic FUNCTION
isb
- dsb
+ dsb
CPSID aif
- B panic
+ B panic
ENDFUNC
;--------------------------------------------------------------
; Utility function that takes a pointer (r0), stack size (r1).
-; It returns the pointer to the stack offset for the asked cpu
-;--------------------------------------------------------------
+; It returns the pointer to the stack offset for the asked cpu
+;--------------------------------------------------------------
get_sp FUNCTION
- ldr r2, =0x2c001800
+ ldr r2, =0x2c001800
ldr r2, [r2]
- and r2, r2, #0xff
+ and r2, r2, #0xff
clz r2, r2
mov r3, #32
sub r2, r3, r2
mul r2, r2, r1
add r0, r0, r2
bx lr
- ENDFUNC
+ ENDFUNC
disable_coherency FUNCTION
push {lr}
@@ -257,7 +257,7 @@ disable_coherency FUNCTION
pop {lr}
bx lr
ENDFUNC
-
+
enable_coherency FUNCTION
push {lr}
bl read_actlr
@@ -266,19 +266,19 @@ enable_coherency FUNCTION
dsb
isb
pop {lr}
- bx lr
+ bx lr
ENDFUNC
inv_bpred_is FUNCTION
mcr p15, 0, r0, c7, c1, 6
bx lr
ENDFUNC
-
+
inv_bpred_all FUNCTION
mcr p15, 0, r0, c7, c5, 6
bx lr
ENDFUNC
-
+
inv_tlb_all FUNCTION
mcr p15, 0, r0, c8, c7, 0
dsb
@@ -288,53 +288,53 @@ inv_tlb_all FUNCTION
inv_tlb_mva FUNCTION
mcr p15, 0, r0, c8, c7, 1
- dsb
+ dsb
isb
bx lr
ENDFUNC
-
+
inv_icache_all FUNCTION
mcr p15, 0, r10, c7, c5, 0 ; invalidate I cache
dsb
isb
bx lr
ENDFUNC
-
+
inv_icache_mva_pou FUNCTION
mcr p15, 0, r0, c7, c5, 1
dsb
isb
bx lr
ENDFUNC
-
+
cln_dcache_mva_pou FUNCTION
mcr p15, 0, r0, c7, c11, 1
dsb
isb
bx lr
ENDFUNC
-
+
cln_dcache_mva_poc FUNCTION
mcr p15, 0, r0, c7, c10, 1
dsb
isb
- bx lr
+ bx lr
ENDFUNC
inv_dcache_mva_poc FUNCTION
mcr p15, 0, r0, c7, c6, 1
dsb
isb
- bx lr
- ENDFUNC
-
+ bx lr
+ ENDFUNC
+
; Clean/Invalidate/Clean and invalidate a specified cache level.
; Ignore if the level does not exist.
cache_maint_op FUNCTION
push {r4-r11}
dsb
lsl r10, r0, #1 ; start clean at specified cache level
- mrc p15, 1, r0, c0, c0, 1 ; read clidr
+ mrc p15, 1, r0, c0, c0, 1 ; read clidr
10
add r2, r10, r10, lsr #1 ; work out 3x current cache level
mov r3, r0, lsr r2 ; extract cache type bits from clidr
@@ -353,12 +353,12 @@ cache_maint_op FUNCTION
ands r7, r7, r3, lsr #13 ; extract max number of the index size
20
mov r9, r4 ; create working copy of max way size
-30
+30
orr r11, r10, r9, lsl r5 ; factor way and cache number into r11
- lsl r6, r9, r5
+ lsl r6, r9, r5
orr r11, r10, r6 ; factor way and cache number into r11
orr r11, r11, r7, lsl r2 ; factor index number into r11
- lsl r6, r7, r2
+ lsl r6, r7, r2
orr r11, r11, r6 ; factor index number into r11
cmp r1, #INV
mcreq p15, 0, r11, c7, c6, 2 ; invalidate by set/way
@@ -368,7 +368,7 @@ cache_maint_op FUNCTION
beq %f40
mcr p15, 0, r11, c7, c14, 2 ; clean & invalidate by set/way
; nop ; nop
-40
+40
subs r9, r9, #1 ; decrement the way
bge %b30
subs r7, r7, #1 ; decrement the index
@@ -378,20 +378,20 @@ cache_maint_op FUNCTION
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
dsb
isb
- pop {r4-r11}
+ pop {r4-r11}
bx lr
- ENDFUNC
+ ENDFUNC
smc FUNCTION
push {r4-r12, lr}
smc #0
pop {r4-r12, pc}
ENDFUNC
-
+
hyp_save FUNCTION
hvc #2
bx lr
- ENDFUNC
+ ENDFUNC
virt_memcpy FUNCTION
cmp r2, #0
@@ -415,7 +415,7 @@ virt_memset FUNCTION
virt_dead FUNCTION
b virt_dead
ENDFUNC
-
+
num_secondaries FUNCTION
mrc p15, 1, r0, c9, c0, 2
lsr r0, r0, #24
@@ -426,17 +426,17 @@ num_secondaries FUNCTION
dcisw FUNCTION
mcr p15, 0, r0, c7, c6, 2
bx lr
- ENDFUNC
+ ENDFUNC
dccsw FUNCTION
mcr p15, 0, r0, c7, c10, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
dccisw FUNCTION
mcr p15, 0, r0, c7, c14, 2
bx lr
- ENDFUNC
-
-
+ ENDFUNC
+
+
END
diff --git a/big-little/secure_world/events.c b/big-little/secure_world/events.c
index 4533039..6aee95a 100644
--- a/big-little/secure_world/events.c
+++ b/big-little/secure_world/events.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "events.h"
diff --git a/big-little/secure_world/flat_pagetable.s b/big-little/secure_world/flat_pagetable.s
index 5038f85..2db7f95 100644
--- a/big-little/secure_world/flat_pagetable.s
+++ b/big-little/secure_world/flat_pagetable.s
@@ -1,31 +1,31 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
+ ; permission.
+ ;
PRESERVE8
AREA PageTable, DATA, READONLY, ALIGN=14
EXPORT flat_pagetables
GBLL CONFIG_SMP_CPU3_AMP
CONFIG_SMP_CPU3_AMP SETL {FALSE}
-
+
; Definitions for section descriptors
NGLOBAL EQU (1<<17)
SHARED EQU (1<<16)
@@ -45,7 +45,7 @@ SECURITY EQU 0
; Select WBWA for both Inner and Outer cache
MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1 :OR: SECURITY)
S_RO_MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1 :OR: APX)
-S_RW_MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1)
+S_RW_MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1)
; Select WBWA Inner cache, WBnWA Outer cache
;MEMORY EQU (TEX3 | TEX2 | TEX1 | BUFFER | SECTION | AP0 | AP1 | SECURITY)
@@ -58,61 +58,61 @@ DEVICE EQU (BUFFER :OR: SHARED :OR: SECTION :OR: AP0 :OR: AP1 :OR: XN
NO_MEMORY EQU (SECTION)
SHARED_MEMORY EQU (MEMORY :OR: SHARED)
SHARED_S_RO_MEMORY EQU (S_RO_MEMORY :OR: SHARED)
-SHARED_S_RW_MEMORY EQU (S_RW_MEMORY :OR: SHARED)
+SHARED_S_RW_MEMORY EQU (S_RW_MEMORY :OR: SHARED)
SHARED_NC_MEMORY EQU (NC_MEMORY :OR: SHARED)
SHARED_SO_MEMORY EQU (SO_MEMORY :OR: SHARED)
SHARED_DEVICE EQU (DEVICE :OR: SHARED)
-
+
; first-level descriptors - all of them are 1MB sections
flat_pagetables
GBLA count16
GBLA ramstart
-count16 SETA 0
+count16 SETA 0
ramstart SETA 0
-
+
; NOT FOR RELEASE
- WHILE count16 < ramstart+0x40
+ WHILE count16 < ramstart+0x40
; 0-64MB Secure ROM/NOR Flash
DCD (count16<<20) :OR: SHARED_DEVICE
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
WHILE count16 < ramstart+0x80
; 64-128MB Secure RAM
DCD (count16<<20) :OR: SHARED_S_RW_MEMORY
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
WHILE count16 < ramstart+0x800
; 128-2048MB Peripheral space
DCD (count16<<20) :OR: SHARED_DEVICE
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
- WHILE count16 < ramstart+0x810
+ WHILE count16 < ramstart+0x810
; 0-16MB Shared Memory
DCD (count16<<20) :OR: SHARED_MEMORY
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
-
+
WHILE count16 < ramstart+0x81f
; 16-31MB Strongly Ordered
DCD (count16<<20) :OR: SHARED_SO_MEMORY
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
WHILE count16 < ramstart+0x820
; 31-32MB Shared Noncached Normal Memory
DCD (count16<<20) :OR: SHARED_NC_MEMORY
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
-
+
WHILE count16 < ramstart+0x1000
; rest of memory is RAM
DCD (count16<<20) :OR: SHARED_MEMORY
-count16 SETA count16 + 1
+count16 SETA count16 + 1
WEND
END
diff --git a/big-little/secure_world/monmode_vectors.s b/big-little/secure_world/monmode_vectors.s
index 641de50..e6d8ace 100644
--- a/big-little/secure_world/monmode_vectors.s
+++ b/big-little/secure_world/monmode_vectors.s
@@ -1,25 +1,25 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA |monmode_vectors|, CODE, ALIGN=5
PRESERVE8
@@ -31,13 +31,13 @@ L1 EQU 0x0
L2 EQU 0x1
INV EQU 0x0
CLN EQU 0x1
-CLN_INV EQU 0x2
-CR_M EQU (1<<0)
+CLN_INV EQU 0x2
+CR_M EQU (1<<0)
CR_C EQU (1<<2)
CR_I EQU (1<<12)
-CR_Z EQU (1<<11)
+CR_Z EQU (1<<11)
CR_U EQU (1<<22)
-CR_TRE EQU (1<<28)
+CR_TRE EQU (1<<28)
SCR_NS EQU 0x01
PT_IRGN EQU (1<<0)
PT_RGN EQU (1<<3)
@@ -48,7 +48,7 @@ SO_MEM EQU 0x0
DV_MEM EQU 0x1
NM_MEM EQU 0x2
I_SH EQU 0x1
-SH EQU 0x1
+SH EQU 0x1
PRRR_TR0 EQU (SO_MEM<<0)
PRRR_TR1 EQU (DV_MEM<<2)
PRRR_TR4 EQU (NM_MEM<<8)
@@ -57,7 +57,7 @@ PRRR_DS1 EQU (SH<<17)
PRRR_NS1 EQU (SH<<19)
PRRR_NOS1 EQU (I_SH<<25)
PRRR_NOS4 EQU (I_SH<<28)
-PRRR_NOS7 EQU (I_SH<<31)
+PRRR_NOS7 EQU (I_SH<<31)
NC EQU 0x0
WBWA EQU 0x1
NMRR_OR4 EQU (NC<<24)
@@ -67,51 +67,51 @@ NMRR_IR7 EQU (WBWA<<14)
; ==============================================================================
; These should be the same the defines in misc.h
-; ==============================================================================
+; ==============================================================================
MAX_CLUSTERS EQU 2
MAX_CPUS EQU 8
STACK_SIZE EQU (96 << 2)
-
+
; ==============================================================================
; Simple vector table
; ==============================================================================
IMPORT ns_entry_ptr
IMPORT secure_context_save
IMPORT enable_caches
- IMPORT inv_icache_all
+ IMPORT inv_icache_all
IMPORT flat_pagetables
IMPORT read_sctlr
IMPORT write_sctlr
IMPORT read_ttbr0
IMPORT write_ttbr0
IMPORT inv_tlb_all
- IMPORT inv_bpred_all
+ IMPORT inv_bpred_all
IMPORT write_dacr
IMPORT write_prrr
IMPORT write_nmrr
IMPORT get_sp
IMPORT secure_context_restore
IMPORT do_power_op
- IMPORT get_powerdown_stack
+ IMPORT get_powerdown_stack
IMPORT wfi
IMPORT read_cpuid
- IMPORT add_dv_page
+ IMPORT add_dv_page
EXPORT monmode_vector_table
- EXPORT warm_reset
+ EXPORT warm_reset
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Macro to initialise MMU. Corrupts 'r0'
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
MACRO
setup_mmu $r1, $r2
MOV $r1, #0x5555
- MOVT $r1, #0x5555
+ MOVT $r1, #0x5555
; Enable our page tables if not
- LDR r0, =flat_pagetables
+ LDR r0, =flat_pagetables
ORR r0, #TTBR0_PROP
; Write TTBR0
MCR p15, 0, r0, c2, c0, 0
- ; Write DACR
+ ; Write DACR
MCR p15, 0, $r1, c3, c0, 0
; Enable the remap registers to treat OSH memory as ISH memory
@@ -143,17 +143,17 @@ STACK_SIZE EQU (96 << 2)
ISB
MEND
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Macro to setup secure stacks, Corrupts 'r0-r3'
- ; ----------------------------------------------------
- MACRO
+ ; ----------------------------------------------------
+ MACRO
setup_stack
LDR r0, =secure_stacks
MOV r1, #STACK_SIZE
BL get_sp
MOV sp, r0
MEND
-
+
ALIGN 32
monmode_vector_table
monmode_reset_vec
@@ -161,32 +161,32 @@ monmode_reset_vec
monmode_undef_vec
B monmode_undef_vec
monmode_smc_vec
- B do_smc
-monmode_pabort_vec
+ B do_smc
+monmode_pabort_vec
B monmode_pabort_vec
-monmode_dabort_vec
+monmode_dabort_vec
B monmode_dabort_vec
-monmode_unused_vec
+monmode_unused_vec
B monmode_unused_vec
monmode_irq_vec
B monmode_irq_vec
-monmode_fiq_vec
+monmode_fiq_vec
B monmode_fiq_vec
- ; SMC handler. Currently accepts three types of calls:
+ ; SMC handler. Currently accepts three types of calls:
; 1. Init: Sets up stack, mmu, caches & coherency
; 2. Context Save: Saves the secure world context
; 3. Powerdown: Cleans the caches and power downs the cluster
- ; Also assumes the availability of r4-r7
+ ; Also assumes the availability of r4-r7
do_smc FUNCTION
; Switch to non-secure banked registers
MRC p15, 0, r3, c1, c1, 0
BIC r3, #SCR_NS
MCR p15, 0, r3, c1, c1, 0
ISB
-
- ; Check if we are being called to setup the world
+
+ ; Check if we are being called to setup the world
CMP r0, #SMC_SEC_INIT
BEQ setup_secure
@@ -196,15 +196,15 @@ do_smc FUNCTION
CMP r0, #SMC_SEC_SHUTDOWN
BEQ shutdown
-smc_done
+smc_done
; Return to non-secure banked registers
MRC p15, 0, r0, c1, c1, 0
ORR r0, #SCR_NS
MCR p15, 0, r0, c1, c1, 0
ISB
- ERET
+ ERET
ENDFUNC
-
+
shutdown
MOV r4, r1
MOV r5, r2
@@ -224,7 +224,7 @@ shutdown
enter_wfi
BL wfi
B enter_wfi
-
+
save_secure
PUSH {lr}
MOV r0, r1
@@ -234,71 +234,71 @@ save_secure
B smc_done
setup_secure
- ; Save the LR
+ ; Save the LR
MOV r4, lr
-
+
; Turn on the I cache, branch predictor and alingment
BL read_sctlr
ORR r0, #CR_I
ORR r0, #CR_U
- ORR r0, #CR_Z
- BL write_sctlr
+ ORR r0, #CR_Z
+ BL write_sctlr
dsb
isb
-
+
setup_stack
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Safely turn on caches
; TODO: Expensive usage of stacks as we are executing
; out of SO memory. Done only once so can live with it
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
BL enable_caches
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Add a page backed by device memory for locks & stacks
; ----------------------------------------------------
LDR r0, =flat_pagetables
- BL add_dv_page
+ BL add_dv_page
setup_mmu r1, r2
- ; Restore LR
- MOV lr, r4
+ ; Restore LR
+ MOV lr, r4
B smc_done
-
+
warm_reset FUNCTION
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Start the SO load of the pagetables asap
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
LDR r4, =flat_pagetables
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Enable I, C, Z, U bits in the SCTLR and SMP bit in
; the ACTLR right after reset
; ----------------------------------------------------
- MRC p15, 0, r0, c1, c0, 0
+ MRC p15, 0, r0, c1, c0, 0
ORR r0, r0, #CR_I
ORR r0, r0, #CR_U
ORR r0, r0, #CR_Z
ORR r0, r0, #CR_C
MCR p15, 0, r0, c1, c0, 0
- MRC p15, 0, r1, c1, c0, 1
+ MRC p15, 0, r1, c1, c0, 1
ORR r1, r1, #0x40
- MCR p15, 0, r1, c1, c0, 1
+ MCR p15, 0, r1, c1, c0, 1
ISB
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Enable the MMU even though CCI snoops have not been
; enabled. Should not be a problem as we will not
; access any inter-cluster data till we do so
; ----------------------------------------------------
MOV r2, #0x5555
- MOVT r2, #0x5555
+ MOVT r2, #0x5555
; Enable our page tables if not
ORR r4, #TTBR0_PROP
; Write TTBR0
MCR p15, 0, r4, c2, c0, 0
- ; Write DACR
+ ; Write DACR
MCR p15, 0, r2, c3, c0, 0
; Enable the remap registers to treat OSH memory as ISH memory
@@ -324,26 +324,26 @@ warm_reset FUNCTION
ORR r0, #CR_C
ORR r0, #CR_TRE
MCR p15, 0, r0, c1, c0, 0
- ISB
+ ISB
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Try Preloading the literal pools before they are
; accessed.
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
ADR r4, warm_reset_ltrls
- PLD [r4]
+ PLD [r4]
PLD warm_reset_ltrls
LDR r6, =secure_stacks
-
- ; ----------------------------------------------------
+
+ ; ----------------------------------------------------
; Safely turn on CCI snoops
; ----------------------------------------------------
MOV r4, #0x0
MOVT r4, #0x2c09
MRC p15, 0, r0, c0, c0, 5
UBFX r1, r0, #0, #8
- UBFX r2, r0, #8, #8
- MOV r3, #3
+ UBFX r2, r0, #8, #8
+ MOV r3, #3
CMP r2, #0
BEQ a15_snoops
MOV r5, #0x5000
@@ -364,27 +364,27 @@ cci_snoop_status
TST r0, #1
BNE cci_snoop_status
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Switch to Monitor mode straight away as we do not want to worry
; about setting up Secure SVC stacks. All Secure world save/restore
; takes place in the monitor mode.
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
MRS r5, cpsr ; Get current mode (SVC) in r0
BIC r1, r5, #0x1f ; Clear all mode bits
ORR r1, r1, #0x16 ; Set bits for Monitor mode
MSR cpsr_cxsf, r1 ; We are now in Monitor Mode
BIC r1, r5, #0x1f ; Clear all mode bits
- ORR r1, r1, #0x1a ; Set bits for a return to the HYP mode
+ ORR r1, r1, #0x1a ; Set bits for a return to the HYP mode
MSR spsr_cxsf, r1
MOV r0, r6
MOV r1, #STACK_SIZE
BL get_sp
- MOV sp, r0
+ MOV sp, r0
; Restore secure world context & enable MMU
BL secure_context_restore
-
+
; Switch to non-secure registers for HYP &
; later non-secure world restore.
MRC p15, 0, r1, c1, c1, 0
@@ -399,8 +399,8 @@ cci_snoop_status
ADD r1, r1, r0, lsl #2
LDR lr, [r1]
; Switch to Non-secure world
- ERET
-warm_reset_ltrls
+ ERET
+warm_reset_ltrls
ENDFUNC
AREA stacks, DATA, ALIGN=6
diff --git a/big-little/secure_world/secure_context.c b/big-little/secure_world/secure_context.c
index 321f4ab..9619823 100644
--- a/big-little/secure_world/secure_context.c
+++ b/big-little/secure_world/secure_context.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "secure_world.h"
@@ -51,7 +51,7 @@ void enable_caches(void)
/*
* Only one cpu should enable the CCI while the other
- * cpus wait.
+ * cpus wait.
*/
if (first_cpu == cpu_id) {
if (cluster_id)
@@ -158,7 +158,7 @@ static void create_l1_sp_desc(unsigned virt_addr, unsigned l1_ttb_va,
ttb1_index = (virt_addr & MB_MASK) >> MB_SHIFT;
- /*
+ /*
* Create a mapping if one is not already present.
* Assuming that page tables are initialized to 0.
*/
@@ -190,8 +190,8 @@ static void create_l2_sp_desc(unsigned virt_addr, unsigned phys_addr,
/* Left shift by 12 followed by a right shift by 24 gives 2nd level index */
ttb2_index = (virt_addr << PAGE_SHIFT) >> (PAGE_SHIFT * 2);
- /*
- * Create a mapping if one is not already present
+ /*
+ * Create a mapping if one is not already present
* Assuming that page tables are initialized to 0.
*/
if (!(read32(l2_ttb_va + 4 * ttb2_index))) {
diff --git a/big-little/secure_world/secure_resets.c b/big-little/secure_world/secure_resets.c
index a734838..457f91c 100644
--- a/big-little/secure_world/secure_resets.c
+++ b/big-little/secure_world/secure_resets.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "secure_world.h"
@@ -62,13 +62,13 @@ unsigned event[MAX_CORES][MAX_EVENTS]
/*
* Normal spinlock to guard inbound cluster registers
- * in the KFSCB. It will always be used when the MMU
+ * in the KFSCB. It will always be used when the MMU
* is on. Each cluster will anyways use it sequentially.
*/
static unsigned lock_ib_kfscb;
/*
- * Bakery lock to guard outbound cluster registers in
+ * Bakery lock to guard outbound cluster registers in
* KFSCB. It will always be used when the MMU is off.
* Each cluster will anyways use it sequentially
*/
@@ -278,7 +278,7 @@ void do_power_op(unsigned cpu_mask, unsigned op_type)
}
/********************* RESET HANDLING **************************************
- * Secondaries place themselves in reset while the 'first_cpu' waits for
+ * Secondaries place themselves in reset while the 'first_cpu' waits for
* them to do so.
***************************************************************************/
diff --git a/big-little/secure_world/secure_world.h b/big-little/secure_world/secure_world.h
index 658016b..c3e7827 100644
--- a/big-little/secure_world/secure_world.h
+++ b/big-little/secure_world/secure_world.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __SECURE_WORLD_H__
diff --git a/big-little/secure_world/ve_reset_handler.s b/big-little/secure_world/ve_reset_handler.s
index e887108..5647eb0 100644
--- a/big-little/secure_world/ve_reset_handler.s
+++ b/big-little/secure_world/ve_reset_handler.s
@@ -1,28 +1,28 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA test, CODE
- ENTRY
+ ENTRY
[ FM_BETA
IMPORT warm_reset
@@ -38,21 +38,21 @@
STREQ r1, [r2]
LDREQ PC, =0x80000000
LDRNE PC, =warm_reset
-
+
|
-
+
MRC p15, 0, r0, c0, c0, 5
UBFX r1, r0, #0, #8
UBFX r2, r0, #8, #8
ADD r3, r1, r2, lsl #2
- LSL r3, #3
+ LSL r3, #3
LDR r4, =0x60000040
LDR r4, [r4, r3]
- CMP r4, #0
+ CMP r4, #0
BXNE r4
- LDR pc, =0x80000000
+ LDR pc, =0x80000000
]
END
-
+
diff --git a/big-little/switcher/context/gic.c b/big-little/switcher/context/gic.c
index d4bb1b1..a080ce1 100644
--- a/big-little/switcher/context/gic.c
+++ b/big-little/switcher/context/gic.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virt_helpers.h"
@@ -115,11 +115,11 @@ int save_gic_distributor_private(unsigned int *pointer,
++pointer;
/*
- * Private peripheral interrupts need to be replayed on
+ * Private peripheral interrupts need to be replayed on
* the destination cpu interface for consistency. This
* is the responsibility of the peripheral driver. When
* it sees a pending interrupt while saving its context
- * it should record enough information to recreate the
+ * it should record enough information to recreate the
* interrupt while restoring.
* We don't save the Pending/Active status and clear it
* so that it does not interfere when we are back.
@@ -209,7 +209,7 @@ void restore_gic_distributor_private(unsigned int *pointer,
++pointer;
/*
- * Clear active and pending PPIs as they will be recreated by the
+ * Clear active and pending PPIs as they will be recreated by the
* peripiherals
*/
id->active.clear[0] = 0xffffffff;
diff --git a/big-little/switcher/context/ns_context.c b/big-little/switcher/context/ns_context.c
index 65bee37..265c672 100644
--- a/big-little/switcher/context/ns_context.c
+++ b/big-little/switcher/context/ns_context.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virt_helpers.h"
@@ -82,7 +82,7 @@ void stop_generic_timer(generic_timer_context * ctr_ctx)
*/
write_cntp_ctl(TIMER_MASK_IRQ);
- /*
+ /*
* If the local timer interrupt was being used as
* the asynchronous trigger, then it was disabled
* in handle_interrupt() to prevent this level-
@@ -192,7 +192,7 @@ void save_context(unsigned first_cpu, unsigned op_type)
/*
* Save the HYP view registers. These registers contain a snapshot
- * of all the physical interrupts acknowledged till we
+ * of all the physical interrupts acknowledged till we
* entered this HYP mode.
*/
vgic_savestate(cpu_id);
diff --git a/big-little/switcher/context/sh_vgic.c b/big-little/switcher/context/sh_vgic.c
index c2ba190..36c89c3 100644
--- a/big-little/switcher/context/sh_vgic.c
+++ b/big-little/switcher/context/sh_vgic.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virt_helpers.h"
@@ -39,8 +39,8 @@ static unsigned int cpuif_map[MAX_CLUSTERS][MAX_CORES];
* 4 store the cpuid.
*
* TODO:
- * No real need for this data structure. Should be
- * possible to get this info from the previous data
+ * No real need for this data structure. Should be
+ * possible to get this info from the previous data
* structure and the knowledge of number of clusters
* and cpus from the KFSCB
*/
@@ -61,7 +61,7 @@ static unsigned int cpuinfo_map[MAX_CPUIFS];
* cluster.
* Ideally a platform defined register should have done the
* trick. However, we rely on a software mechanism to obtain
- * this information.
+ * this information.
*
* Assumptions:
* a) Expected to be used only in the "Switching" case when
@@ -78,7 +78,7 @@ static unsigned int cpuinfo_map[MAX_CPUIFS];
* be targetted to the outbound cluster cpus & there will be no
* local peripheral interrupts expected. There is paranoia about
* getting IPIs from the outbound but this can be dealt with by
- * manipulating the IPI priorities so that we only see what we
+ * manipulating the IPI priorities so that we only see what we
* want to see.
*
* TODO:
@@ -163,14 +163,14 @@ unsigned get_cpuif_mask(unsigned cpu_mask)
}
/*
- * Given a cpu interface mask, find its corresponding mask on the other cluster
+ * Given a cpu interface mask, find its corresponding mask on the other cluster
* NOTE: Creates the new mask in-place.
*/
#if 1
/*
* This is the fast version of remapping cpu interface ids to cpuids. Instead of
* remapping each bit (target interface) in the arg passed, it simply shifts all
- * the bits by the number of cpus available.
+ * the bits by the number of cpus available.
*/
unsigned remap_cpuif(unsigned *cpuif_mask)
{
@@ -203,13 +203,13 @@ unsigned remap_cpuif(unsigned *cpuif_mask)
ob_cpuid = get_cpuinfo(ob_cpuif) & 0xf;
ob_clusterid = (get_cpuinfo(ob_cpuif) >> 4) & 0xf;
- /*
+ /*
* TODO: Can we assume that the inbound and outbound clusters will
* always be logical complements of each other
*/
ib_clusterid = !ob_clusterid;
- /*
+ /*
* TODO: Assuming that the cpuids have a 1:1 mapping i.e. cpuX on
* one cluster will always map to cpuX on the other cluster.
*/
diff --git a/big-little/switcher/trigger/async_switchover.c b/big-little/switcher/trigger/async_switchover.c
index b8585e7..cbe8f56 100644
--- a/big-little/switcher/trigger/async_switchover.c
+++ b/big-little/switcher/trigger/async_switchover.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "ipi.h"
@@ -71,7 +71,7 @@ unsigned cluster_reset_status(unsigned cluster_id)
}
/*
- * Broadcast first available IPI so that all cpus can start switching to
+ * Broadcast first available IPI so that all cpus can start switching to
* the other cluster.
*/
void signal_switchover(void)
@@ -172,10 +172,10 @@ unsigned check_trigger(unsigned int_id, unsigned int_ack)
if (hyp_timer_trigger)
ack_trigger();
else
- /*
+ /*
* Complete handling of the local timer interrupt at the physical gic
- * level. Its disabled as its level triggerred and will reassert as
- * soon as we leave this function since its not been cleared at the
+ * level. Its disabled as its level triggerred and will reassert as
+ * soon as we leave this function since its not been cleared at the
* peripheral just yet. The local timer context is saved and this irq
* cleared while saving the context. The interrupt is enabled then.
*/
diff --git a/big-little/switcher/trigger/handle_switchover.s b/big-little/switcher/trigger/handle_switchover.s
index 4f26183..99c8380 100644
--- a/big-little/switcher/trigger/handle_switchover.s
+++ b/big-little/switcher/trigger/handle_switchover.s
@@ -1,25 +1,25 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA SwitchoverCode, CODE, READONLY, ALIGN=5
PRESERVE8
@@ -31,9 +31,9 @@
SMC_SEC_SHUTDOWN EQU 0x2
OP_TYPE_SWITCH EQU 0x1
-
+
switch_cluster FUNCTION
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; Save the NS state and ask the secure world to save
; its context and bring the corresponding inbound core
; out of reset
@@ -41,7 +41,7 @@ switch_cluster FUNCTION
MOV r1, #OP_TYPE_SWITCH
BL save_context
- ; ----------------------------------------------------
+ ; ----------------------------------------------------
; All context has been saved and restored. The inbound
; core has resumed payload execution. Ask the secure
; world to clean the caches and power down the cluster
@@ -51,7 +51,7 @@ switch_cluster FUNCTION
LDR r1, [r1]
MOV r2, #OP_TYPE_SWITCH
BL smc
- ENDFUNC
+ ENDFUNC
END
diff --git a/big-little/virtualisor/cache_geom.c b/big-little/virtualisor/cache_geom.c
index 1f24882..4677226 100644
--- a/big-little/virtualisor/cache_geom.c
+++ b/big-little/virtualisor/cache_geom.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virtualisor.h"
@@ -82,7 +82,7 @@ void find_cache_geometry(cache_geometry * cg_ptr)
}
/*
- * Given two cache geometries, find out how they differ
+ * Given two cache geometries, find out how they differ
*/
void find_cache_diff(cache_geometry * hcg_ptr, cache_geometry * tcg_ptr,
cache_diff * cd_ptr)
@@ -113,11 +113,11 @@ void find_cache_diff(cache_geometry * hcg_ptr, cache_geometry * tcg_ptr,
tc_size = tc_assoc * tc_numsets * tc_linelen;
hc_size = hc_assoc * hc_numsets * hc_linelen;
- /*
- * Find the factor by which the cache line sizes differ.
+ /*
+ * Find the factor by which the cache line sizes differ.
* If so, then the target cacheline will have to be
* multiplied or divided by the factor to get the absolute
- * cache line number. Then, find the number of absolute
+ * cache line number. Then, find the number of absolute
* cache lines in each cache
*/
if (tc_linelen >= hc_linelen) {
@@ -133,7 +133,7 @@ void find_cache_diff(cache_geometry * hcg_ptr, cache_geometry * tcg_ptr,
}
/*
- * Find if the cache sizes differ. If so, then set a flag
+ * Find if the cache sizes differ. If so, then set a flag
* to indicate whether some set/way operations need to be
* extended on the host cpu or ignored on the target cpu
*/
@@ -183,8 +183,8 @@ unsigned map_cache_geometries(cache_geometry * hcg_ptr,
* Assuming that only no. of sets, ways and cache line
* size will be different across the target and host
* cpu caches. Hence the CLIDRs should look the same
- * Support for absence of cache levels and memory
- * Also this check ensures that the target cpu is
+ * Support for absence of cache levels and memory
+ * Also this check ensures that the target cpu is
* always run before the host else the cache geometry
* will have to be hardcoded.
* mapped caches will be added later.
@@ -198,8 +198,8 @@ unsigned map_cache_geometries(cache_geometry * hcg_ptr,
find_cache_diff(hcg_ptr, tcg_ptr, cd_ptr);
- /*
- * Enable bit for trapping set/way operations &
+ /*
+ * Enable bit for trapping set/way operations &
* cache identification registers
*/
hcr = read_hcr();
@@ -224,7 +224,7 @@ unsigned map_cache_geometries(cache_geometry * hcg_ptr,
return rc;
}
-/*
+/*
* Given two cache geometries and the difference between them
* handle a cache maintenance operation by set/way
*/
@@ -245,10 +245,10 @@ void handle_cm_op(unsigned reg,
*/
unsigned ctr = cd_ptr[clvl].tcline_factor;
- /*
+ /*
* Find out the cache level for which the set/way operation has invoked.
- * Use this to find the cache geometry in target cache to ascertain the
- * set & way number from the argument. Use this info to calculate the
+ * Use this to find the cache geometry in target cache to ascertain the
+ * set & way number from the argument. Use this info to calculate the
* target cache line number.
*/
clvl = get_cache_level(reg);
@@ -262,7 +262,7 @@ void handle_cm_op(unsigned reg,
if (cmop_debug) {
/*
- * tc_prev_line is initialised to -1 (unsigned). We can never have so many
+ * tc_prev_line is initialised to -1 (unsigned). We can never have so many
* cache lines. Helps determining when to record the start of a cm op.
* If count != lineno then either we are not counting or have been counting
* and now are out of sync. In either case, a new cm op is started
@@ -292,7 +292,7 @@ void handle_cm_op(unsigned reg,
lineno = abs_lineno / cd_ptr[clvl].hcline_factor;
/*
- * Find out the set & way no. on the host cache corresponding to the
+ * Find out the set & way no. on the host cache corresponding to the
* cache line no. calculated on the target cache.
*/
hc_linesz = get_cache_linesz(hcg_ptr, clvl);
@@ -365,7 +365,7 @@ void handle_cm_op(unsigned reg,
/*
* If the target cache is smaller than the host cache then we
* need to extend the maintenance operation to rest of the host
- * cache.
+ * cache.
*/
if ((abs_lineno +
(1 * cd_ptr[clvl].tcline_factor)) ==
diff --git a/big-little/virtualisor/cpus/a15/a15.c b/big-little/virtualisor/cpus/a15/a15.c
index 1b244c4..5b6c091 100644
--- a/big-little/virtualisor/cpus/a15/a15.c
+++ b/big-little/virtualisor/cpus/a15/a15.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "bl.h"
diff --git a/big-little/virtualisor/cpus/a15/include/a15.h b/big-little/virtualisor/cpus/a15/include/a15.h
index 3a9515d..5873b51 100644
--- a/big-little/virtualisor/cpus/a15/include/a15.h
+++ b/big-little/virtualisor/cpus/a15/include/a15.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __A15_H__
diff --git a/big-little/virtualisor/cpus/a7/a7.c b/big-little/virtualisor/cpus/a7/a7.c
index 4aff69d..59e3618 100644
--- a/big-little/virtualisor/cpus/a7/a7.c
+++ b/big-little/virtualisor/cpus/a7/a7.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "bl.h"
diff --git a/big-little/virtualisor/cpus/a7/include/a7.h b/big-little/virtualisor/cpus/a7/include/a7.h
index ff3000e..817f841 100644
--- a/big-little/virtualisor/cpus/a7/include/a7.h
+++ b/big-little/virtualisor/cpus/a7/include/a7.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __A7_H__
diff --git a/big-little/virtualisor/include/cache_geom.h b/big-little/virtualisor/include/cache_geom.h
index 23db57b..e2935ea 100644
--- a/big-little/virtualisor/include/cache_geom.h
+++ b/big-little/virtualisor/include/cache_geom.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __CACHE_GEOM_H__
@@ -51,20 +51,20 @@
* between the host and target caches at each implemented
* cache level.
* Absolute cache line numbers are calculated relative to
- * the cache line size of the smaller cache to get the
+ * the cache line size of the smaller cache to get the
* maximum granularity.
*/
typedef struct cache_diff {
/* Stores whether target cache is =,<,> host cache */
unsigned csize_diff;
- /*
- * Stores factor by which target cache line
+ /*
+ * Stores factor by which target cache line
* has to be multiplied to get absolute line
* no.
*/
unsigned tcline_factor;
- /*
- * Stores factor by which absolute cache line
+ /*
+ * Stores factor by which absolute cache line
* no. has to be divided to get host cache line
* no.
*/
@@ -80,7 +80,7 @@ typedef struct cache_diff {
*/
typedef struct cache_geom {
unsigned clidr;
- /*
+ /*
* One for each cpu to store the cache level
* the OS thinks its operating on.
*/
diff --git a/big-little/virtualisor/include/mem_trap.h b/big-little/virtualisor/include/mem_trap.h
index ab68259..1eaa117 100644
--- a/big-little/virtualisor/include/mem_trap.h
+++ b/big-little/virtualisor/include/mem_trap.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __MEM_TRAP_H__
diff --git a/big-little/virtualisor/include/virtualisor.h b/big-little/virtualisor/include/virtualisor.h
index 1bcd5e2..6b84eb8 100644
--- a/big-little/virtualisor/include/virtualisor.h
+++ b/big-little/virtualisor/include/virtualisor.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __VIRTUALISOR_H__
@@ -35,7 +35,7 @@ typedef struct virt_regs {
unsigned midr;
} virt_reg_data;
-/*
+/*
* Data structure that holds all the trap registers exported
* by the Virtualisation Extensions.
*/
@@ -52,14 +52,14 @@ typedef struct gp_regs {
/*
* Descriptor exported by each processor describing
- * which traps it wants to implement along with
+ * which traps it wants to implement along with
* handlers for saving and restoring for each conf-
* -igured trap.
*/
typedef struct virt_desc {
/* cpu midr contents */
unsigned cpu_no;
- /*
+ /*
* Bitmask to inidicate that Virtualisor setup has been
* done on both host & target cpus.
*/
diff --git a/big-little/virtualisor/mem_trap.c b/big-little/virtualisor/mem_trap.c
index c40433a..6850c37 100644
--- a/big-little/virtualisor/mem_trap.c
+++ b/big-little/virtualisor/mem_trap.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virtualisor.h"
@@ -27,7 +27,7 @@
/*
* Generic call to make accesses to a peripheral trap into the
- * HYP mode by invalidating its descriptor in the 2nd stage
+ * HYP mode by invalidating its descriptor in the 2nd stage
* translation tables
*/
unsigned mem_trap_setup(unsigned periph_addr, mem_trap_data * periph_trap_data)
@@ -115,7 +115,7 @@ unsigned mem_trap_setup(unsigned periph_addr, mem_trap_data * periph_trap_data)
l3_desc =
((unsigned long long *)((unsigned)(&l3_table)[0]))[four_kb_index];
- /*
+ /*
* Validate the 3rd level descriptor. This means that the mapping is
* already invalid and we have not touched it
*/
diff --git a/big-little/virtualisor/vgic_trap_handler.c b/big-little/virtualisor/vgic_trap_handler.c
index 75e1030..063ab40 100644
--- a/big-little/virtualisor/vgic_trap_handler.c
+++ b/big-little/virtualisor/vgic_trap_handler.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virtualisor.h"
@@ -76,9 +76,9 @@ void handle_vgic_distif_abort(unsigned pa, unsigned *data, unsigned write)
/* Get the updated cpu interface mask */
value = get_cpuif_mask((*data >> 16) & 0xff) << 16;
value |= *data & ~(0xff << 16);
- /*
+ /*
* Clear the old cpu interface mask & update
- * value with new cpu interface mask
+ * value with new cpu interface mask
*/
write32(pa, value);
} else {
diff --git a/big-little/virtualisor/virt_context.c b/big-little/virtualisor/virt_context.c
index 65dacb6..85d572e 100644
--- a/big-little/virtualisor/virt_context.c
+++ b/big-little/virtualisor/virt_context.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virtualisor.h"
@@ -33,7 +33,7 @@ extern cache_stats cm_op_stats[NUM_CPUS][MAX_CACHE_LEVELS];
/*
* Save/Restore of Virtualisor should be done only on the host cpu
* & host cluster unlike setup which is done on both. The cluster
- * is need for cases where both clusters have same cpu type and one
+ * is need for cases where both clusters have same cpu type and one
* cluster does not use the Virtualisor.
*/
void SaveVirtualisor(unsigned first_cpu)
@@ -52,7 +52,7 @@ void SaveVirtualisor(unsigned first_cpu)
if (cluster_id == host_cluster) {
/*
- * Since there is only one second stage translation table, its
+ * Since there is only one second stage translation table, its
* safe to assume that only one cpu (first_cpu) should save &
* restore the context.
*/
@@ -64,7 +64,7 @@ void SaveVirtualisor(unsigned first_cpu)
if (s2_td[ctr].valid
&& s2_td[ctr].cluster_id == cluster_id) {
- /*
+ /*
* Save the current descriptor and restore the
* previous. Need not worry about synchronisation
* issues, as the existing entry was causing
@@ -105,7 +105,7 @@ void SaveVirtualisor(unsigned first_cpu)
}
- /*
+ /*
* Call any cpu specific save routines (if any)
*/
vd_len = (unsigned)&virt_desc_section$$Length;
@@ -155,7 +155,7 @@ void RestoreVirtualisor(unsigned first_cpu)
if (cluster_id == host_cluster) {
/*
- * Since there is only one second stage translation table, its
+ * Since there is only one second stage translation table, its
* safe to assume that only one cpu (first_cpu) should save &
* restore the context.
*/
@@ -166,8 +166,8 @@ void RestoreVirtualisor(unsigned first_cpu)
ctr++) {
if (s2_td[ctr].valid
&& s2_td[ctr].cluster_id == cluster_id) {
- /*
- * Restore the current descriptor and save the previous
+ /*
+ * Restore the current descriptor and save the previous
*/
cd_ptr =
&((unsigned long long
@@ -204,7 +204,7 @@ void RestoreVirtualisor(unsigned first_cpu)
}
}
- /*
+ /*
* Call any cpu specific restore routines (if any)
*/
vd_len = (unsigned)&virt_desc_section$$Length;
diff --git a/big-little/virtualisor/virt_handle.c b/big-little/virtualisor/virt_handle.c
index ca3cb8e..fcb1610 100644
--- a/big-little/virtualisor/virt_handle.c
+++ b/big-little/virtualisor/virt_handle.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virtualisor.h"
@@ -344,7 +344,7 @@ void trap_cp15_mrc_mcr_handle(unsigned hsr, gp_regs * regs)
goto error;
}
- /*
+ /*
* A read of the L2CTLR should return the total number
* of cpus across both the clusters in the "always on"
* configuration. Since there are only 2 bits for the
@@ -398,7 +398,7 @@ void trap_cp15_mrc_mcr_handle(unsigned hsr, gp_regs * regs)
break;
/*
- * Support for accesses to the PMON space. Its not been
+ * Support for accesses to the PMON space. Its not been
* verified whether all the registers are readable &
* writable. But then, execution will never reach here
* if a reg is inaccessible. It will be a undef abort
diff --git a/big-little/virtualisor/virt_setup.c b/big-little/virtualisor/virt_setup.c
index 4403ae2..33949f0 100644
--- a/big-little/virtualisor/virt_setup.c
+++ b/big-little/virtualisor/virt_setup.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include "virt_helpers.h"
@@ -46,7 +46,7 @@ static mem_trap_data svgic_distif_trap
*/
static unsigned virt_init[NUM_CPUS];
-/*
+/*
* Detect the type of dual cluster system we are, read
* our cpu type and then use the KFS_ID register to
* return the type of cpu on the other cluster.
@@ -110,7 +110,7 @@ void SetupVirtualisor(unsigned first_cpu)
write_hstr(read_hstr() | (1 << 9));
}
- /*
+ /*
* Cache geometry of each cpu on the host cluster needs
* to be virtualised if the cpu type is different from
* that on the target cluster. This can be done generic-
@@ -130,12 +130,12 @@ void SetupVirtualisor(unsigned first_cpu)
}
- /*
+ /*
* If the two clusters have different cpu types, then the
* target saves its midr and the host uses the value to
* virtualise its midr.
- * mpidr is virtualised on the host cluster whether we are
- * running "always on" or "switching". The latter cares
+ * mpidr is virtualised on the host cluster whether we are
+ * running "always on" or "switching". The latter cares
* about the cluster id while the former cares about the
* cpu ids as well.
*/
@@ -144,7 +144,7 @@ void SetupVirtualisor(unsigned first_cpu)
if (cpu_no != sibling)
host_virt_regs[cpu_id].midr = read_midr();
if (!switcher) {
- /*
+ /*
* Send a signal to the host to indicate
* that the regs is ready to be read. The
* cpu id is the absolute cpu number across
@@ -155,15 +155,15 @@ void SetupVirtualisor(unsigned first_cpu)
} else {
if (!switcher) {
/*
- * Wait for the target to read its regs
+ * Wait for the target to read its regs
* before using them.
*/
wait_for_event(VID_REGS_DONE, abs_cpuid);
reset_event(VID_REGS_DONE, abs_cpuid);
/*
- * Add number of cpus in the target cluster to
- * the cpuid of this cpu.
+ * Add number of cpus in the target cluster to
+ * the cpuid of this cpu.
*/
host_virt_regs[cpu_id].mpidr +=
CLUSTER_CPU_COUNT(!host_cluster);
@@ -191,7 +191,7 @@ void SetupVirtualisor(unsigned first_cpu)
RestoreVirtualisor(first_cpu);
}
- /*
+ /*
* Do the cpu specific initialisation (if any)
*/
vd_len = (unsigned)&virt_desc_section$$Length;
diff --git a/bootwrapper/Makefile b/bootwrapper/Makefile
index bb59aec..90cc975 100644
--- a/bootwrapper/Makefile
+++ b/bootwrapper/Makefile
@@ -61,7 +61,7 @@ V7_ASFLAGS=--apcs /inter --cpu=Eagle --keep \
--pd "BOOTARGS SETS \"$(BOOTARGS)\"" \
--pd "L2_POLICY SETS \"$(L2_POLICY)\"" \
--pd "VE SETL {$(VE)}" \
- --pd "HIBASE SETS \"$(HIBASE)\""
+ --pd "HIBASE SETS \"$(HIBASE)\""
CFLAGS:=--cpu=Eagle -O2 \
-DT2=$(T2) \
@@ -110,7 +110,7 @@ helpers.o : emubuild.s
@echo " CC $<"
$(Q)armcc $(CFLAGS) -o $@ -c $<
-bl.S:
+bl.S:
make -C big-little bl.axf
@echo " MAP"
$(Q)./makemap big-little/bl.axf bl
@@ -119,7 +119,7 @@ bl.o: bl.S
@echo " AS $<"
$(Q)armasm $(V7_ASFLAGS) -o $@ $<
-bl_sec.S:
+bl_sec.S:
make -C big-little bl_sec.axf wboot.bin
@echo " MAP"
$(Q)./makemap big-little/bl_sec.axf bl_sec
@@ -140,5 +140,5 @@ img.axf: $(OBJS)
-e "s/VECTBASE/${VECTBASE}/g" \
boot.map
@echo " LD $@"
- $(Q)armlink --entry $(VECTBASE)00000 -o $@ --scatter boot.map $(OBJS)
+ $(Q)armlink --entry $(VECTBASE)00000 -o $@ --scatter boot.map $(OBJS)
diff --git a/bootwrapper/big-little-mp1.mxscript b/bootwrapper/big-little-mp1.mxscript
index 0dbcfb0..54106cf 100644
--- a/bootwrapper/big-little-mp1.mxscript
+++ b/bootwrapper/big-little-mp1.mxscript
@@ -6,7 +6,7 @@ string model = "<path to the model>";
// e.g. string app = "/home/working_dir/bootwrapper/img.axf"
string app = "<path to the software image>";
-// Replace the string with the absolute path of the wboot.bin image created in the
+// Replace the string with the absolute path of the wboot.bin image created in the
// bootwrapper/big-little directory. This image is load in flash at 0x0 and distinguishes
// between a warm and a cold reset
string wboot = "<path to warm reset handler image>";
@@ -16,7 +16,7 @@ int ctr = 0;
// NOTE
//
// Uncomment the next 4 'string' variables and update them _only_ if the run is required
-// to generate trace output as described in docs/04-Cache-hit-rate-howto.txt. Also,
+// to generate trace output as described in docs/04-Cache-hit-rate-howto.txt. Also,
// comment out the system() invocation on line 47 and uncomment the system() command on line 34.
// Each 'trace' parameter is described below.
@@ -44,10 +44,10 @@ string console = " -C motherboard.pl011_uart0.untimed_fifos=1 -C motherboard.pl0
string dualcluster = " -C coretile.dualclustersystemconfigurationblock.CFG_ACTIVECLUSTER=0x1";
// NOTE
-//
+//
// _Only_ if a run is needed using an optional rootfs MMC image built using the instructions in
-// docs/06-Optional-rootfs-build.txt, then comment out the system() invocation
-// below (on line 47) and uncomment the following lines taking care to update
+// docs/06-Optional-rootfs-build.txt, then comment out the system() invocation
+// below (on line 47) and uncomment the following lines taking care to update
// the paths accordingly.
// string mmcimage = "<path to mmc.img>";
// system(model + " -C motherboard.mmc.p_mmc_file=" + mmcimage + trace_plugin + trace_sources + trace_file + trace_misc + " -C coretile.cache_state_modelled=1" + " -a coretile.cluster0.\*=" + app + " -a coretile.cluster1.\*=" + app + " --verbose -S &");
@@ -59,7 +59,7 @@ system(model + " -C motherboard.flashloader0.fname=" + wboot + " -C coretile.cac
// Wait for the model to load before connecting to it. There will be times when we
// try connecting before the model has loded resulting in a "Connection refused"
// error. Increasing 'ctr' or retrying should solve the problem.
-while(ctr < 400000000)
+while(ctr < 400000000)
{
ctr++;
}
diff --git a/bootwrapper/big-little-mp4.mxscript b/bootwrapper/big-little-mp4.mxscript
index b30509c..67ebec3 100644
--- a/bootwrapper/big-little-mp4.mxscript
+++ b/bootwrapper/big-little-mp4.mxscript
@@ -6,7 +6,7 @@ string model = "<path to the model>";
// e.g. string app = "/home/working_dir/bootwrapper/img.axf";
string app = "<path to the software image>";
-// Replace the string with the absolute path of the wboot.bin image created in the
+// Replace the string with the absolute path of the wboot.bin image created in the
// bootwrapper/big-little directory. This image is load in flash at 0x0 and distinguishes
// between a warm and a cold reset
string wboot = "<path to warm reset handler image>";
@@ -16,7 +16,7 @@ int ctr = 0;
// NOTE
//
// Uncomment the next 4 'string' variables and update them _only_ if the run is required
-// to generate trace output as described in docs/04-Cache-hit-rate-howto.txt. Also,
+// to generate trace output as described in docs/04-Cache-hit-rate-howto.txt. Also,
// comment out the system() invocation on line 47 and uncomment the system() command on line 34.
// Each 'trace' parameter is described below.
@@ -44,10 +44,10 @@ string console = " -C motherboard.pl011_uart0.untimed_fifos=1 -C motherboard.pl0
string dualcluster = " -C coretile.dualclustersystemconfigurationblock.CFG_ACTIVECLUSTER=0x1";
// NOTE
-//
+//
// _Only_ if a run is needed using an optional rootfs MMC image built using the instructions in
-// docs/06-Optional-rootfs-build.txt, then comment out the system() invocation
-// below (on line 47) and uncomment the following lines taking care to update
+// docs/06-Optional-rootfs-build.txt, then comment out the system() invocation
+// below (on line 47) and uncomment the following lines taking care to update
// the paths accordingly.
// string mmcimage = "<path to mmc.img>";
// system(model + " -C motherboard.mmc.p_mmc_file=" + mmcimage + trace_plugin + trace_sources + trace_file + trace_misc + " -C coretile.cache_state_modelled=1" + " -a coretile.cluster0.\*=" + app + " -a coretile.cluster1.\*=" + app + " --verbose -S &");
@@ -59,7 +59,7 @@ system(model + " -C motherboard.flashloader0.fname=" + wboot + " -C coretile.cac
// Wait for the model to load before connecting to it. There will be times when we
// try connecting before the model has loded resulting in a "Connection refused"
// error. Increasing 'ctr' or retrying should solve the problem.
-while(ctr < 400000000)
+while(ctr < 400000000)
{
ctr++;
}
diff --git a/bootwrapper/boot.S b/bootwrapper/boot.S
index 88cb036..fa4e363 100644
--- a/bootwrapper/boot.S
+++ b/bootwrapper/boot.S
@@ -1,25 +1,25 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA |boot|, CODE, ALIGN=2
PRESERVE8
@@ -29,14 +29,14 @@
IMPORT __use_no_heap_region
IMPORT output_string
IMPORT c_start
- IMPORT enable_coherency
+ IMPORT enable_coherency
IMPORT stack
- IMPORT stack_size
+ IMPORT stack_size
IMPORT hexword
IMPORT read_sctlr
IMPORT write_sctlr
- IMPORT get_sp
- IMPORT inv_icache_all
+ IMPORT get_sp
+ IMPORT inv_icache_all
EXPORT start
EXPORT dabort
@@ -48,27 +48,27 @@
EXPORT unused
EXPORT dead
-;------------------------------------------------------------------------------
+;------------------------------------------------------------------------------
; Boot code starts here - identify the CPU type, set up stacks and call c_start
-;------------------------------------------------------------------------------
+;------------------------------------------------------------------------------
start
bl inv_icache_all
;------------------------------------------------------------------
; Enable ICache, branch predictor and alignment
- ;------------------------------------------------------------------
+ ;------------------------------------------------------------------
bl read_sctlr
- bic r0, r0, #CR_C
+ bic r0, r0, #CR_C
orr r0, r0, #CR_Z
orr r0, r0, #CR_I
- ;------------------------------------------------------------------
+ ;------------------------------------------------------------------
; Set U bit - the C compiler produces non-64-bit-aligned LDRD/STRDs
- ;------------------------------------------------------------------
+ ;------------------------------------------------------------------
orr r0, #CR_U
bl write_sctlr
;------------------------------------------------------------------
- ; Give yourself a stack to make things easier
- ;------------------------------------------------------------------
+ ; Give yourself a stack to make things easier
+ ;------------------------------------------------------------------
ldr r0, =stack
ldr r1, =stack_size
ldr r1, [r1]
@@ -77,8 +77,8 @@ start
;------------------------------------------------------------------
; Caches are inavlidated at reset & MMU is off. So its safe to
- ; enable coherency
- ;------------------------------------------------------------------
+ ; enable coherency
+ ;------------------------------------------------------------------
;; bl enable_coherency
;------------------------------------------------------------------
@@ -87,15 +87,15 @@ start
;------------------------------------------------------------------
; Jump to the C handler
- ;------------------------------------------------------------------
+ ;------------------------------------------------------------------
bl c_start
;------------------------------------------------------------------
; Should never come here
- ;------------------------------------------------------------------
+ ;------------------------------------------------------------------
kernel_returned
b kernel_returned
-
+
; ==============================================================================
; End of main code
; ==============================================================================
@@ -122,10 +122,10 @@ fiq_string
unused_string
DCB " Emubuild-UNU!", 0
- ALIGN
-
+ ALIGN
+
; ==============================================================================
-; Exception handlers - for most exceptions we spin
+; Exception handlers - for most exceptions we spin
; ==============================================================================
dabort
@@ -139,7 +139,7 @@ dabort
mrc p15,0,r0,c6,c0,0 ; DFAR
bl hexword
-
+
ldr r0, =dabort_string
bl output_string
b dead
diff --git a/bootwrapper/bootargs.S b/bootwrapper/bootargs.S
index 373ff7d..6721354 100644
--- a/bootwrapper/bootargs.S
+++ b/bootwrapper/bootargs.S
@@ -1,25 +1,25 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA | bootargs|, CODE, ALIGN=8
PRESERVE8
@@ -36,7 +36,7 @@ args SETS BOOTARGS :CC: " l2=alreadyon"
args SETS BOOTARGS :CC: " nol2x0"
ENDIF
-
+
; ==============================================================================
; Linux "Tagged List" is declared here (see linux/Documentation/arm/Booting)
; ==============================================================================
diff --git a/bootwrapper/bootwrapper.h b/bootwrapper/bootwrapper.h
index bc2671b..ef12670 100644
--- a/bootwrapper/bootwrapper.h
+++ b/bootwrapper/bootwrapper.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __BOOTWRAPPER_H__
diff --git a/bootwrapper/c_start.c b/bootwrapper/c_start.c
index a4f1729..f0ebd88 100644
--- a/bootwrapper/c_start.c
+++ b/bootwrapper/c_start.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#include <stdio.h>
@@ -84,7 +84,7 @@ void kick(unsigned cpu_id, unsigned cluster_id, int secondary_cpus)
}
/*
- * This function doesn't retun - it waits for an address to be
+ * This function doesn't retun - it waits for an address to be
* written into the FLAGs register, then jumps to that address.
*/
void secondary_main(unsigned cluster_id, unsigned cpu_id)
diff --git a/bootwrapper/emubuild.s b/bootwrapper/emubuild.s
index 87b01fb..dd7bb82 100644
--- a/bootwrapper/emubuild.s
+++ b/bootwrapper/emubuild.s
@@ -1,24 +1,24 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
+ ; permission.
+ ;
;; CPSR Mode bits definitions
USR_MODE EQU 16
@@ -43,9 +43,9 @@ CR_M EQU (1<<0)
CR_W EQU (1<<3)
CR_Z EQU (1<<11)
CR_XP EQU (1<<23)
-
+
PAGE_MASK EQU ~0xfff
-
+
CLIENT_ACCESS EQU 0x55555555
MANAGER_ACCESS EQU 0xffffffff
diff --git a/bootwrapper/filesystem.S b/bootwrapper/filesystem.S
index 05e2f35..ba0c5da 100644
--- a/bootwrapper/filesystem.S
+++ b/bootwrapper/filesystem.S
@@ -1,29 +1,29 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
- AREA |filesystem|, CODE, ALIGN=2
-
+ ; permission.
+ ;
+ AREA |filesystem|, CODE, ALIGN=2
+
EXPORT fs_start
- EXPORT fs_end
-fs_start
+ EXPORT fs_end
+fs_start
INCBIN payload/fsimg
-fs_end
+fs_end
END
diff --git a/bootwrapper/helpers.S b/bootwrapper/helpers.S
index bf08be0..261d0c6 100644
--- a/bootwrapper/helpers.S
+++ b/bootwrapper/helpers.S
@@ -1,47 +1,47 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
EXPORT wfi
EXPORT wfe
- EXPORT sev
+ EXPORT sev
EXPORT dmb
EXPORT dsb
- EXPORT isb
+ EXPORT isb
EXPORT smc
EXPORT dcisw
- EXPORT dccsw
- EXPORT dccisw
+ EXPORT dccsw
+ EXPORT dccisw
EXPORT read_dacr
- EXPORT read_ttbr0
- EXPORT read_cpacr
+ EXPORT read_ttbr0
+ EXPORT read_cpacr
EXPORT read_scr
EXPORT read_cpsr
EXPORT read_midr
- EXPORT read_mpidr
- EXPORT read_cntpct
- EXPORT read_cntfrq
+ EXPORT read_mpidr
+ EXPORT read_cntpct
+ EXPORT read_cntfrq
EXPORT read_vmpidr
- EXPORT read_vmidr
+ EXPORT read_vmidr
EXPORT read_id_pfr0
EXPORT read_id_pfr1
EXPORT read_id_dfr0
@@ -49,20 +49,20 @@
EXPORT read_id_mmfr0
EXPORT read_id_mmfr1
EXPORT read_id_mmfr2
- EXPORT read_id_mmfr3
+ EXPORT read_id_mmfr3
EXPORT read_id_isar0
EXPORT read_id_isar1
EXPORT read_id_isar2
EXPORT read_id_isar3
EXPORT read_id_isar4
- EXPORT read_id_isar5
+ EXPORT read_id_isar5
EXPORT read_cpuid
- EXPORT read_aidr
+ EXPORT read_aidr
EXPORT read_ctr
EXPORT read_tcmtr
EXPORT read_tlbtr
- EXPORT read_clusterid
- EXPORT read_sctlr
+ EXPORT read_clusterid
+ EXPORT read_sctlr
EXPORT read_hsctlr
EXPORT read_hdfar
EXPORT read_hpfar
@@ -70,26 +70,26 @@
EXPORT read_hcr
EXPORT read_hdcr
EXPORT read_hcptr
- EXPORT read_hstr
+ EXPORT read_hstr
EXPORT read_cnthctl
- EXPORT read_cntkctl
+ EXPORT read_cntkctl
EXPORT read_cntp_ctl
- EXPORT read_cntp_tval
+ EXPORT read_cntp_tval
EXPORT read_cnthp_ctl
EXPORT read_cnthp_tval
- EXPORT read_cnthp_cval
+ EXPORT read_cnthp_cval
EXPORT read_ttbcr
- EXPORT read_clidr
- EXPORT read_lr
+ EXPORT read_clidr
+ EXPORT read_lr
EXPORT read_sp
EXPORT read_actlr
EXPORT read_nsacr
- EXPORT read_clidr
+ EXPORT read_clidr
EXPORT read_csselr
EXPORT read_ccsidr
EXPORT read_nmrr
EXPORT read_prrr
- EXPORT read_mvbar
+ EXPORT read_mvbar
EXPORT read_vbar
EXPORT read_hsr
EXPORT read_dfar
@@ -97,22 +97,22 @@
EXPORT read_dfsr
EXPORT read_ifsr
EXPORT read_adfsr
- EXPORT read_aifsr
+ EXPORT read_aifsr
EXPORT write_dacr
EXPORT write_prrr
- EXPORT write_nmrr
+ EXPORT write_nmrr
EXPORT write_ttbr0
EXPORT write_cpacr
EXPORT write_nsacr
- EXPORT write_cpsr
+ EXPORT write_cpsr
EXPORT write_scr
EXPORT write_mvbar
EXPORT write_vbar
- EXPORT write_hvbar
+ EXPORT write_hvbar
EXPORT write_vmpidr
- EXPORT write_vmidr
- EXPORT write_csselr
+ EXPORT write_vmidr
+ EXPORT write_csselr
EXPORT write_hcr
EXPORT write_hdcr
EXPORT write_hcptr
@@ -122,64 +122,64 @@
EXPORT write_sp
EXPORT write_lr
EXPORT write_ttbcr
- EXPORT write_cntfrq
+ EXPORT write_cntfrq
EXPORT write_cnthctl
- EXPORT write_cntkctl
+ EXPORT write_cntkctl
EXPORT write_cntp_ctl
- EXPORT write_cntp_tval
+ EXPORT write_cntp_tval
EXPORT write_cnthp_ctl
EXPORT write_cnthp_tval
- EXPORT write_cnthp_cval
+ EXPORT write_cnthp_cval
EXPORT write_hsctlr
EXPORT write_httbr
- EXPORT write_vttbr
+ EXPORT write_vttbr
EXPORT write_htcr
- EXPORT write_vtcr
- EXPORT write_hmair0
+ EXPORT write_vtcr
+ EXPORT write_hmair0
EXPORT write_hmair1
EXPORT write_dfar
EXPORT write_ifar
EXPORT write_dfsr
EXPORT write_ifsr
EXPORT write_adfsr
- EXPORT write_aifsr
-
+ EXPORT write_aifsr
+
EXPORT panic
EXPORT spin_lock
- EXPORT spin_trylock
- EXPORT spin_unlock
- EXPORT copy_words
+ EXPORT spin_trylock
+ EXPORT spin_unlock
+ EXPORT copy_words
EXPORT virt_memset
EXPORT disable_gic_dist
- EXPORT enable_gic_dist
+ EXPORT enable_gic_dist
EXPORT switcher_exit
EXPORT hyp_save
EXPORT num_secondaries
EXPORT virt_dead
- EXPORT get_sp
+ EXPORT get_sp
EXPORT disable_coherency
EXPORT enable_coherency
EXPORT inv_tlb_all
- EXPORT inv_icache_all
+ EXPORT inv_icache_all
EXPORT inv_bpred_is
EXPORT inv_bpred_all
EXPORT inv_icache_mva_pou
EXPORT inv_dcache_mva_poc
EXPORT cln_dcache_mva_pou
- EXPORT cln_dcache_mva_poc
+ EXPORT cln_dcache_mva_poc
EXPORT enable_user_perfmon_access
EXPORT enable_perfmon
EXPORT enable_swp
EXPORT cache_maint_op
EXPORT enter_monitor_mode
EXPORT enter_nonsecure_world
- EXPORT enable_pmu
+ EXPORT enable_pmu
; Cache maintenance op types
INV EQU 0x0
CLN EQU 0x1
CLN_INV EQU 0x2
-
+
AREA |.text|, CODE
read_cntfrq FUNCTION
@@ -191,29 +191,29 @@ write_cntfrq FUNCTION
mcr p15, 0, r0, c14, c0, 0
bx lr
ENDFUNC
-
+
read_cntpct FUNCTION
mrrc p15, 0, r2, r3, c14
str r2, [r0]
- str r3, [r1]
+ str r3, [r1]
bx lr
ENDFUNC
-
+
dcisw FUNCTION
mcr p15, 0, r0, c7, c6, 2
bx lr
- ENDFUNC
+ ENDFUNC
dccsw FUNCTION
mcr p15, 0, r0, c7, c10, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
dccisw FUNCTION
mcr p15, 0, r0, c7, c14, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
virt_dead FUNCTION
b virt_dead
ENDFUNC
@@ -224,28 +224,28 @@ disable_gic_dist FUNCTION
str r2, [r0]
mov r2, #0
str r2, [r1]
- dsb
- pop {pc}
+ dsb
+ pop {pc}
ENDFUNC
enable_gic_dist FUNCTION
push {lr}
str r0, [r1]
- dsb
- pop {pc}
- ENDFUNC
-
+ dsb
+ pop {pc}
+ ENDFUNC
+
smc FUNCTION
push {r4-r12, lr}
smc #0
pop {r4-r12, pc}
ENDFUNC
-
+
dmb FUNCTION
dmb
bx lr
ENDFUNC
-
+
wfi FUNCTION
wfi
bx lr
@@ -269,7 +269,7 @@ switcher_exit FUNCTION
hyp_save FUNCTION
hvc #2
bx lr
- ENDFUNC
+ ENDFUNC
; This function takes three arguments
; r0: Destination start address (must be word aligned)
@@ -284,7 +284,7 @@ copy_words FUNCTION
stmia r0!, {r3, r4, r5, r12}
sub r2, r2, #4
b %b0
-
+
1 cmp r2, #0
beq %f3
2 ldr r3, [r1], #4
@@ -295,8 +295,8 @@ copy_words FUNCTION
3 pop {r4, r5}
bx lr
ENDFUNC
-
-
+
+
virt_memcpy FUNCTION
cmp r2, #0
bxeq lr
@@ -320,7 +320,7 @@ virt_memset FUNCTION
; Functions we need in the runtime entry point, i.e. before we switch pagetables,
; are placed in this area.
-
+
dsb FUNCTION
dsb
bx lr
@@ -329,7 +329,7 @@ dsb FUNCTION
isb FUNCTION
isb
bx lr
- ENDFUNC
+ ENDFUNC
num_secondaries FUNCTION
mrc p15, 1, r0, c9, c0, 2
@@ -342,11 +342,11 @@ read_vmpidr FUNCTION
mrc p15, 4, r0, c0, c0, 5
bx lr
ENDFUNC
-
+
read_vmidr FUNCTION
mrc p15, 4, r0, c0, c0, 0
bx lr
- ENDFUNC
+ ENDFUNC
read_id_pfr0 FUNCTION
mrc p15, 0, r0, c0, c1, 0
@@ -362,12 +362,12 @@ read_id_dfr0 FUNCTION
mrc p15, 0, r0, c0, c1, 2
bx lr
ENDFUNC
-
+
read_id_afr0 FUNCTION
mrc p15, 0, r0, c0, c1, 3
bx lr
ENDFUNC
-
+
read_id_mmfr0 FUNCTION
mrc p15, 0, r0, c0, c1, 4
bx lr
@@ -377,17 +377,17 @@ read_id_mmfr1 FUNCTION
mrc p15, 0, r0, c0, c1, 5
bx lr
ENDFUNC
-
+
read_id_mmfr2 FUNCTION
mrc p15, 0, r0, c0, c1, 6
bx lr
- ENDFUNC
+ ENDFUNC
read_id_mmfr3 FUNCTION
mrc p15, 0, r0, c0, c1, 7
bx lr
ENDFUNC
-
+
read_id_isar0 FUNCTION
mrc p15, 0, r0, c0, c2, 0
bx lr
@@ -397,17 +397,17 @@ read_id_isar1 FUNCTION
mrc p15, 0, r0, c0, c2, 1
bx lr
ENDFUNC
-
+
read_id_isar2 FUNCTION
mrc p15, 0, r0, c0, c2, 2
bx lr
ENDFUNC
-
+
read_id_isar3 FUNCTION
mrc p15, 0, r0, c0, c2, 3
bx lr
ENDFUNC
-
+
read_id_isar4 FUNCTION
mrc p15, 0, r0, c0, c2, 4
bx lr
@@ -416,8 +416,8 @@ read_id_isar4 FUNCTION
read_id_isar5 FUNCTION
mrc p15, 0, r0, c0, c2, 5
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_ctr FUNCTION
mrc p15, 0, r0, c0, c0, 1
bx lr
@@ -431,12 +431,12 @@ read_tcmtr FUNCTION
read_tlbtr FUNCTION
mrc p15, 0, r0, c0, c0, 3
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_aidr FUNCTION
mrc p15, 1, r0, c0, c0, 7
bx lr
- ENDFUNC
+ ENDFUNC
va_to_pa FUNCTION ; Note: assumes conversion will be successful!
mov r1, r0
@@ -458,7 +458,7 @@ read_ttbr0 FUNCTION
dsb
bx lr
ENDFUNC
-
+
write_dacr FUNCTION
mcr p15, 0, r0, c3, c0, 0
isb
@@ -469,7 +469,7 @@ read_cpacr FUNCTION
mrc p15, 0, r0, c1, c0, 2
bx lr
ENDFUNC
-
+
write_cpacr FUNCTION
mcr p15, 0, r0, c1, c0, 2
bx lr
@@ -493,7 +493,7 @@ read_scr FUNCTION
write_scr FUNCTION
mcr p15, 0, r0, c1, c1, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
@@ -512,7 +512,7 @@ read_cpsr FUNCTION
write_cpsr FUNCTION
msr CPSR_c, r0
bx lr
- ENDFUNC
+ ENDFUNC
write_mvbar FUNCTION
mcr p15, 0, r0, c12, c0, 1
@@ -520,32 +520,32 @@ write_mvbar FUNCTION
ENDFUNC
write_vbar FUNCTION
- mcr p15, 0, r0, c12, c0, 0
+ mcr p15, 0, r0, c12, c0, 0
bx lr
ENDFUNC
write_hvbar FUNCTION
- mcr p15, 4, r0, c12, c0, 0
+ mcr p15, 4, r0, c12, c0, 0
bx lr
- ENDFUNC
+ ENDFUNC
read_mvbar FUNCTION
mrc p15, 0, r0, c12, c0, 1
bx lr
ENDFUNC
-
+
read_vbar FUNCTION
- mrc p15, 0, r0, c12, c0, 0
+ mrc p15, 0, r0, c12, c0, 0
bx lr
ENDFUNC
-
+
read_cpuid FUNCTION
mrc p15, 0, r0, c0, c0, 5
ands r0, r0, #0xf
bx lr
ENDFUNC
-read_clusterid FUNCTION
+read_clusterid FUNCTION
mrc p15, 0, r0, c0, c0, 5
lsr r0, r0, #0x8
ands r0, r0, #0xf
@@ -557,32 +557,32 @@ write_ttbr0 FUNCTION
mcr p15, 0, r0, c7, c5, 6
mcr p15, 0, r0, c8, c7, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
read_ttbcr FUNCTION
mrc p15, 0, r0, c2, c0, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_ttbcr FUNCTION
mcr p15, 0, r0, c2, c0, 2
bx lr
- ENDFUNC
+ ENDFUNC
write_vmpidr FUNCTION
mcr p15, 4, r0, c0, c0, 5
isb
bx lr
ENDFUNC
-
+
write_vmidr FUNCTION
mcr p15, 4, r0, c0, c0, 0
isb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_vtcr FUNCTION
mrc p15, 4, r0, c2, c1, 2
bx lr
@@ -597,34 +597,34 @@ read_hdcr FUNCTION
mrc p15, 4, r0, c1, c1, 1
bx lr
ENDFUNC
-
+
read_hcptr FUNCTION
mrc p15, 4, r0, c1, c1, 2
bx lr
ENDFUNC
-
+
read_hstr FUNCTION
mrc p15, 4, r0, c1, c1, 3
bx lr
- ENDFUNC
+ ENDFUNC
write_hcr FUNCTION
mcr p15, 4, r0, c1, c1, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
write_hdcr FUNCTION
mcr p15, 4, r0, c1, c1, 1
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_hcptr FUNCTION
mcr p15, 4, r0, c1, c1, 2
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_hstr FUNCTION
mcr p15, 4, r0, c1, c1, 3
bx lr
@@ -635,7 +635,7 @@ write_httbr FUNCTION
mcr p15, 0, r0, c7, c5, 6
mcr p15, 0, r0, c8, c7, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
@@ -644,10 +644,10 @@ write_vttbr FUNCTION
mcr p15, 0, r0, c7, c5, 6
mcr p15, 0, r0, c8, c7, 0
isb
- dsb
+ dsb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_htcr FUNCTION
mcr p15, 4, r0, c2, c0, 2
bx lr
@@ -656,7 +656,7 @@ write_htcr FUNCTION
write_vtcr FUNCTION
mcr p15, 4, r0, c2, c1, 2
bx lr
- ENDFUNC
+ ENDFUNC
write_hmair0 FUNCTION
mcr p15, 4, r0, c10, c2, 0
@@ -666,14 +666,14 @@ write_hmair0 FUNCTION
write_hmair1 FUNCTION
mcr p15, 4, r0, c10, c2, 1
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_nsacr FUNCTION
mrc p15, 0, r0, c1, c1, 2
bx lr
ENDFUNC
-
-read_sctlr FUNCTION
+
+read_sctlr FUNCTION
mrc p15, 0, r0, c1, c0, 0
bx lr
ENDFUNC
@@ -681,22 +681,22 @@ read_sctlr FUNCTION
write_sctlr FUNCTION
mcr p15, 0, r0, c1, c0, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
-read_hsctlr FUNCTION
+read_hsctlr FUNCTION
mrc p15, 4, r0, c1, c0, 0
bx lr
ENDFUNC
read_hdfar FUNCTION
- mrc p15, 4, r0, c6, c0, 0
+ mrc p15, 4, r0, c6, c0, 0
bx lr
ENDFUNC
-
+
read_hpfar FUNCTION
- mrc p15, 4, r0, c6, c0, 4
+ mrc p15, 4, r0, c6, c0, 4
bx lr
ENDFUNC
@@ -708,10 +708,10 @@ read_hsr FUNCTION
write_hsctlr FUNCTION
mcr p15, 4, r0, c1, c0, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
-
+
read_cnthctl FUNCTION
mrc p15, 4, r0, c14, c1, 0
bx lr
@@ -720,7 +720,7 @@ read_cnthctl FUNCTION
read_cntkctl FUNCTION
mrc p15, 0, r0, c14, c1, 0
bx lr
- ENDFUNC
+ ENDFUNC
read_cnthp_cval FUNCTION
mrrc p15, 6, r0, r1, c14
@@ -736,84 +736,84 @@ read_cntp_tval FUNCTION
mrc p15, 0, r0, c14, c2, 0
bx lr
ENDFUNC
-
+
read_cntp_ctl FUNCTION
mrc p15, 0, r0, c14, c2, 1
bx lr
- ENDFUNC
-
+ ENDFUNC
+
read_cnthp_ctl FUNCTION
mrc p15, 4, r0, c14, c2, 1
bx lr
- ENDFUNC
+ ENDFUNC
write_cnthctl FUNCTION
mcr p15, 4, r0, c14, c1, 0
bx lr
- ENDFUNC
+ ENDFUNC
write_cntkctl FUNCTION
mcr p15, 0, r0, c14, c1, 0
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_cntp_tval FUNCTION
mcr p15, 0, r0, c14, c2, 0
isb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_cntp_ctl FUNCTION
mcr p15, 0, r0, c14, c2, 1
isb
- dsb
+ dsb
bx lr
- ENDFUNC
-
+ ENDFUNC
+
write_cnthp_cval FUNCTION
mcrr p15, 6, r0, r1, c14
isb
- dsb
+ dsb
bx lr
ENDFUNC
write_cnthp_tval FUNCTION
mcr p15, 4, r0, c14, c2, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
-
+
write_cnthp_ctl FUNCTION
mcr p15, 4, r0, c14, c2, 1
isb
- dsb
+ dsb
bx lr
- ENDFUNC
-
-read_clidr FUNCTION
+ ENDFUNC
+
+read_clidr FUNCTION
mrc p15, 1, r0, c0, c0, 1 ; read clidr
bx lr
ENDFUNC
-read_ccsidr FUNCTION
+read_ccsidr FUNCTION
mrc p15, 1, r0, c0, c0, 0 ; read ccsidr
bx lr
ENDFUNC
-read_csselr FUNCTION
+read_csselr FUNCTION
mrc p15, 2, r0, c0, c0, 0 ; read csselr
bx lr
- ENDFUNC
-
-write_csselr FUNCTION
+ ENDFUNC
+
+write_csselr FUNCTION
mcr p15, 2, r0, c0, c0, 0 ; read csselr
isb
- dsb
+ dsb
bx lr
- ENDFUNC
-
-read_actlr FUNCTION
+ ENDFUNC
+
+read_actlr FUNCTION
mrc p15, 0, r0, c1, c0, 1
bx lr
ENDFUNC
@@ -821,64 +821,64 @@ read_actlr FUNCTION
write_actlr FUNCTION
mcr p15, 0, r0, c1, c0, 1
isb
- dsb
+ dsb
bx lr
ENDFUNC
-read_prrr FUNCTION
+read_prrr FUNCTION
mrc p15, 0, r0, c10, c2, 0
bx lr
ENDFUNC
-read_nmrr FUNCTION
+read_nmrr FUNCTION
mrc p15, 0, r0, c10, c2, 1
bx lr
ENDFUNC
-write_prrr FUNCTION
+write_prrr FUNCTION
mcr p15, 0, r0, c10, c2, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
-write_nmrr FUNCTION
+write_nmrr FUNCTION
mcr p15, 0, r0, c10, c2, 1
isb
- dsb
+ dsb
bx lr
- ENDFUNC
+ ENDFUNC
read_dfar FUNCTION
mrc p15, 0, r0, c6, c0, 0
bx lr
ENDFUNC
-
+
read_ifar FUNCTION
- mrc p15, 0, r0, c6, c0, 2
+ mrc p15, 0, r0, c6, c0, 2
bx lr
ENDFUNC
-
+
read_dfsr FUNCTION
- mrc p15, 0, r0, c5, c0, 0
+ mrc p15, 0, r0, c5, c0, 0
bx lr
ENDFUNC
-
+
read_ifsr FUNCTION
- mrc p15, 0, r0, c5, c0, 1
+ mrc p15, 0, r0, c5, c0, 1
bx lr
ENDFUNC
-
+
read_adfsr FUNCTION
mrc p15, 0, r0, c5, c1, 0
bx lr
ENDFUNC
-
+
read_aifsr FUNCTION
- mrc p15, 0, r0, c5, c1, 1
+ mrc p15, 0, r0, c5, c1, 1
bx lr
ENDFUNC
-
+
write_dfar FUNCTION
mcr p15, 0, r0, c6, c0, 0
isb
@@ -889,40 +889,40 @@ write_dfar FUNCTION
write_ifar FUNCTION
mcr p15, 0, r0, c6, c0, 2
isb
- dsb
+ dsb
bx lr
ENDFUNC
write_dfsr FUNCTION
mcr p15, 0, r0, c5, c0, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
write_ifsr FUNCTION
mcr p15, 0, r0, c5, c0, 1
isb
- dsb
+ dsb
bx lr
ENDFUNC
-
+
write_adfsr FUNCTION
mcr p15, 0, r0, c5, c1, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
-
+
write_aifsr FUNCTION
mcr p15, 0, r0, c5, c1, 1
isb
- dsb
+ dsb
bx lr
ENDFUNC
-
+
read_lr FUNCTION
- ; Save r1
+ ; Save r1
push {r1}
and r0, r0, #0x1f
; Read the current cpsr
@@ -931,18 +931,18 @@ read_lr FUNCTION
; Check if the desired lr is of the current mode
cmp r0, r1
moveq r0, LR
- beq read_lr_out
+ beq read_lr_out
; Check if desired lr is of user mode
cmp r0, #0x10
mrseq r0, LR_usr
beq read_lr_out
- ; Check if desired lr is of supervisor mode
+ ; Check if desired lr is of supervisor mode
cmp r0, #0x13
mrseq r0, LR_svc
read_lr_out
pop {r1}
bx lr
- ENDFUNC
+ ENDFUNC
write_lr FUNCTION
; Save r2
@@ -954,12 +954,12 @@ write_lr FUNCTION
; Check if the lr is of the current mode
cmp r0, r2
moveq LR, r1
- beq write_lr_out
+ beq write_lr_out
; Check if the lr is of user mode
cmp r0, #0x10
msreq LR_usr, r1
beq write_lr_out
- ; Check if the lr is of supervisor mode
+ ; Check if the lr is of supervisor mode
cmp r0, #0x13
msreq LR_svc, r1
write_lr_out
@@ -968,7 +968,7 @@ write_lr_out
ENDFUNC
read_sp FUNCTION
- ; Save r1
+ ; Save r1
push {r1}
and r0, r0, #0x1f
; Read the current cpsr
@@ -977,30 +977,30 @@ read_sp FUNCTION
; Check if the desired sp is of the current mode
cmp r0, r1
moveq r0, SP
- beq read_sp_out
+ beq read_sp_out
; Check if desired sp is of user mode
cmp r0, #0x10
mrseq r0, SP_usr
beq read_sp_out
- ; Check if desired sp is of supervisor mode
+ ; Check if desired sp is of supervisor mode
cmp r0, #0x13
mrseq r0, SP_svc
beq read_sp_out
- ; Check if desired sp is of irq mode
+ ; Check if desired sp is of irq mode
cmp r0, #0x12
mrseq r0, SP_irq
- beq read_sp_out
- ; Check if desired sp is of supervisor mode
+ beq read_sp_out
+ ; Check if desired sp is of supervisor mode
cmp r0, #0x1a
mrseq r0, SP_hyp
beq read_sp_out
- ; Check if desired sp is of monitor mode
+ ; Check if desired sp is of monitor mode
cmp r0, #0x16
- mrseq r0, SP_mon
+ mrseq r0, SP_mon
read_sp_out
pop {r1}
bx lr
- ENDFUNC
+ ENDFUNC
write_sp FUNCTION
; Save r2
@@ -1012,32 +1012,32 @@ write_sp FUNCTION
; Check if the sp is of the current mode
cmp r0, r2
moveq SP, r1
- beq write_sp_out
+ beq write_sp_out
; Check if the sp is of user mode
cmp r0, #0x10
msreq SP_usr, r1
beq write_sp_out
- ; Check if the sp is of supervisor mode
+ ; Check if the sp is of supervisor mode
cmp r0, #0x13
msreq SP_svc, r1
beq write_sp_out
- ; Check if the sp is of irq mode
+ ; Check if the sp is of irq mode
cmp r0, #0x12
msreq SP_irq, r1
- beq write_sp_out
- ; Check if the sp is of hyp mode
+ beq write_sp_out
+ ; Check if the sp is of hyp mode
cmp r0, #0x1a
msreq SP_hyp, r1
beq write_sp_out
- ; Check if the sp is of monitor mode
+ ; Check if the sp is of monitor mode
cmp r0, #0x16
- msreq SP_mon, r1
+ msreq SP_mon, r1
write_sp_out
pop {r2}
bx lr
- ENDFUNC
+ ENDFUNC
- ALIGN 4
+ ALIGN 4
;--------------------------------------------------------
; spin_lock
@@ -1053,7 +1053,7 @@ sl_tryloop
MCR p15, 0, r0, c7, c10, 4
bx lr
ENDFUNC
-
+
;--------------------------------------------------------
; spin_lock
;--------------------------------------------------------
@@ -1064,10 +1064,10 @@ spin_trylock FUNCTION
STREXEQ r1, r2, [r0]
MOV r0, r1
MCR p15, 0, r0, c7, c10, 4
- bx lr
+ bx lr
ENDFUNC
-
- ALIGN 4
+
+ ALIGN 4
;--------------------------------------------------------
; spin_unlock
@@ -1076,28 +1076,28 @@ spin_unlock FUNCTION
MOV r1, #0
STR r1, [r0]
MCR p15, 0, r0, c7, c10, 4
- bx lr
+ bx lr
ENDFUNC
-
- ALIGN 4
+
+ ALIGN 4
;--------------------------------------------------------
; panic
;--------------------------------------------------------
panic FUNCTION
isb
- dsb
+ dsb
CPSID aif
- B panic
+ B panic
ENDFUNC
;--------------------------------------------------------------
; Utility function that takes a pointer (r0), stack size (r1).
-; It returns the pointer to the stack offset for the asked cpu
-;--------------------------------------------------------------
+; It returns the pointer to the stack offset for the asked cpu
+;--------------------------------------------------------------
get_sp FUNCTION
ldr r2, =0x2c001800
- ldr r2, [r2]
+ ldr r2, [r2]
and r2, r2, #0xff
clz r2, r2
mov r3, #32
@@ -1105,7 +1105,7 @@ get_sp FUNCTION
mul r2, r2, r1
add r0, r0, r2
bx lr
- ENDFUNC
+ ENDFUNC
disable_coherency FUNCTION
push {lr}
@@ -1113,81 +1113,81 @@ disable_coherency FUNCTION
bic r0, r0, #0x40
bl write_actlr
isb
- dsb
+ dsb
pop {lr}
bx lr
ENDFUNC
-
+
enable_coherency FUNCTION
push {lr}
bl read_actlr
orr r0, r0, #0x40
bl write_actlr
isb
- dsb
+ dsb
pop {lr}
- bx lr
+ bx lr
ENDFUNC
inv_bpred_is FUNCTION
mcr p15, 0, r0, c7, c1, 6
bx lr
ENDFUNC
-
+
inv_bpred_all FUNCTION
mcr p15, 0, r0, c7, c5, 6
bx lr
ENDFUNC
-
+
inv_tlb_all FUNCTION
mcr p15, 0, r0, c8, c7, 0
isb
- dsb
+ dsb
bx lr
ENDFUNC
-
+
inv_icache_all FUNCTION
mcr p15, 0, r10, c7, c5, 0 ; invalidate I cache
isb
dsb
bx lr
ENDFUNC
-
+
inv_icache_mva_pou FUNCTION
mcr p15, 0, r0, c7, c5, 1
isb
dsb
bx lr
ENDFUNC
-
+
cln_dcache_mva_pou FUNCTION
mcr p15, 0, r0, c7, c11, 1
isb
dsb
bx lr
ENDFUNC
-
+
cln_dcache_mva_poc FUNCTION
mcr p15, 0, r0, c7, c10, 1
isb
dsb
- bx lr
+ bx lr
ENDFUNC
inv_dcache_mva_poc FUNCTION
mcr p15, 0, r0, c7, c6, 1
isb
dsb
- bx lr
- ENDFUNC
-
+ bx lr
+ ENDFUNC
+
; Clean/Invalidate/Clean and invalidate a specified cache level.
; Ignore if the level does not exist.
cache_maint_op FUNCTION
push {r4-r11}
dsb
lsl r10, r0, #1 ; start clean at specified cache level
- mrc p15, 1, r0, c0, c0, 1 ; read clidr
+ mrc p15, 1, r0, c0, c0, 1 ; read clidr
10
add r2, r10, r10, lsr #1 ; work out 3x current cache level
mov r3, r0, lsr r2 ; extract cache type bits from clidr
@@ -1206,12 +1206,12 @@ cache_maint_op FUNCTION
ands r7, r7, r3, lsr #13 ; extract max number of the index size
20
mov r9, r4 ; create working copy of max way size
-30
+30
orr r11, r10, r9, lsl r5 ; factor way and cache number into r11
- lsl r6, r9, r5
+ lsl r6, r9, r5
orr r11, r10, r6 ; factor way and cache number into r11
orr r11, r11, r7, lsl r2 ; factor index number into r11
- lsl r6, r7, r2
+ lsl r6, r7, r2
orr r11, r11, r6 ; factor index number into r11
cmp r1, #INV
mcreq p15, 0, r11, c7, c6, 2 ; invalidate by set/way
@@ -1221,7 +1221,7 @@ cache_maint_op FUNCTION
beq %f40
mcr p15, 0, r11, c7, c14, 2 ; clean & invalidate by set/way
; nop ; nop
-40
+40
subs r9, r9, #1 ; decrement the way
bge %b30
subs r7, r7, #1 ; decrement the index
@@ -1231,9 +1231,9 @@ cache_maint_op FUNCTION
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
dsb
isb
- pop {r4-r11}
+ pop {r4-r11}
bx lr
- ENDFUNC
+ ENDFUNC
enable_user_perfmon_access FUNCTION ; V7 and above
mov r0, #1
@@ -1269,7 +1269,7 @@ enter_monitor_mode FUNCTION
bx lr
ENDFUNC
-enter_nonsecure_world FUNCTION
+enter_nonsecure_world FUNCTION
push {r4-r7}
mov r4, sp ; Save current sp
mov r5, lr ; Save current lr
@@ -1282,9 +1282,9 @@ enter_nonsecure_world FUNCTION
hyp_entry ; We are now in HYP mode
; Set the HYP spsr to itself, so that the entry point
; does not see the difference between a function call
- ; and an exception return.
- msr spsr_cxsf, r7
- blx r0
+ ; and an exception return.
+ msr spsr_cxsf, r7
+ blx r0
msr spsr_cxsf, r6 ; Setup SPSR to jump to NS SVC mode
adr r7, ns_svc_entry
msr elr_hyp, r7
@@ -1294,7 +1294,7 @@ ns_svc_entry
mov lr, r5
pop {r4-r7}
bx lr
- ENDFUNC
+ ENDFUNC
enable_pmu FUNCTION
mov r0, #0x0000003f
@@ -1311,10 +1311,10 @@ enable_pmu FUNCTION
mcr p15, 0, r1, c9, c12, 1 ; Enable counters
isb
mov r0, #0x3
- mrc p15, 0, r1, c9, c12, 0 ;
+ mrc p15, 0, r1, c9, c12, 0 ;
orr r1, r1, r0
mcr p15, 0, r1, c9, c12, 0 ; Reset and Master Enable counters
bx lr
ENDFUNC
-
+
END
diff --git a/bootwrapper/helpers.h b/bootwrapper/helpers.h
index 07ffc47..0afe8fe 100644
--- a/bootwrapper/helpers.h
+++ b/bootwrapper/helpers.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef _VIRT_HELPERS_H_
diff --git a/bootwrapper/kernel.S b/bootwrapper/kernel.S
index 064075d..705bd6c 100644
--- a/bootwrapper/kernel.S
+++ b/bootwrapper/kernel.S
@@ -1,25 +1,25 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
-
+ ; permission.
+ ;
+
AREA |kernel|, CODE, ALIGN=2
EXPORT kernel_start
kernel_start
diff --git a/bootwrapper/makemap b/bootwrapper/makemap
index 0983e2f..664fefa 100755
--- a/bootwrapper/makemap
+++ b/bootwrapper/makemap
@@ -1,24 +1,24 @@
#! /bin/env perl
#
# Copyright (c) 2012, ARM Limited. All rights reserved.
-#
+#
# Redistribution and use in source and binary forms, with
# or without modification, are permitted provided that the
# following conditions are met:
-#
+#
# Redistributions of source code must retain the above
-# copyright notice, this list of conditions and the
+# copyright notice, this list of conditions and the
# following disclaimer.
#
# Redistributions in binary form must reproduce the
-# above copyright notice, this list of conditions and
-# the following disclaimer in the documentation
+# above copyright notice, this list of conditions and
+# the following disclaimer in the documentation
# and/or other materials provided with the distribution.
-#
+#
# Neither the name of ARM nor the names of its
# contributors may be used to endorse or promote products
# derived from this software without specific prior written
-# permission.
+# permission.
#
use strict;
diff --git a/bootwrapper/uart.c b/bootwrapper/uart.c
index 8ea104f..965cb62 100644
--- a/bootwrapper/uart.c
+++ b/bootwrapper/uart.c
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
/*
diff --git a/bootwrapper/vectors.S b/bootwrapper/vectors.S
index 00af8cc..9ccf9a5 100644
--- a/bootwrapper/vectors.S
+++ b/bootwrapper/vectors.S
@@ -1,24 +1,24 @@
;
; Copyright (c) 2012, ARM Limited. All rights reserved.
- ;
+ ;
; Redistribution and use in source and binary forms, with
; or without modification, are permitted provided that the
; following conditions are met:
- ;
+ ;
; Redistributions of source code must retain the above
- ; copyright notice, this list of conditions and the
+ ; copyright notice, this list of conditions and the
; following disclaimer.
;
; Redistributions in binary form must reproduce the
- ; above copyright notice, this list of conditions and
- ; the following disclaimer in the documentation
+ ; above copyright notice, this list of conditions and
+ ; the following disclaimer in the documentation
; and/or other materials provided with the distribution.
- ;
+ ;
; Neither the name of ARM nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior written
- ; permission.
- ;
+ ; permission.
+ ;
AREA vectors, CODE, ALIGN=8
PRESERVE8
diff --git a/bootwrapper/vgic.h b/bootwrapper/vgic.h
index 084e593..3bb4f11 100644
--- a/bootwrapper/vgic.h
+++ b/bootwrapper/vgic.h
@@ -1,23 +1,23 @@
/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
- *
+ *
* Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the
+ * copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
- * above copyright notice, this list of conditions and
- * the following disclaimer in the documentation
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
* and/or other materials provided with the distribution.
- *
+ *
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
- * permission.
+ * permission.
*/
#ifndef __VGIC_H__