juno: Various tidyups

3 files changed, 18 insertions, 23 deletions

diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c
index 78e5d52..96dc854 100644
--- a/plat/juno/bl1_plat_setup.c
+++ b/plat/juno/bl1_plat_setup.c
@@ -37,7 +37,7 @@
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
+ * of trusted RAM
  ******************************************************************************/
 extern unsigned long __COHERENT_RAM_START__;
 extern unsigned long __COHERENT_RAM_END__;
@@ -59,7 +59,7 @@ extern unsigned long __BL1_RAM_END__;
 #define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__)
 
 
-/* Data structure which holds the extents of the trusted SRAM for BL1*/
+/* Data structure which holds the extents of the trusted RAM for BL1 */
 static meminfo bl1_tzram_layout;
 
 meminfo *bl1_plat_sec_mem_layout(void)
@@ -103,9 +103,8 @@ void bl1_early_platform_setup(void)
 }
 
 /*******************************************************************************
- * Function which will evaluate how much of the trusted ram has been gobbled
- * up by BL1 and return the base and size of whats available for loading BL2.
- * Its called after coherency and the MMU have been turned on.
+ * Function which will perform any remaining platform-specific setup that can
+ * occur after the MMU and data cache have been enabled.
  ******************************************************************************/
 void bl1_platform_setup(void)
 {
diff --git a/plat/juno/bl2_plat_setup.c b/plat/juno/bl2_plat_setup.c
index 957f7d4..28fac80 100644
--- a/plat/juno/bl2_plat_setup.c
+++ b/plat/juno/bl2_plat_setup.c
@@ -36,7 +36,7 @@
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
+ * of trusted RAM
  ******************************************************************************/
 extern unsigned long __RO_START__;
 extern unsigned long __RO_END__;
@@ -66,7 +66,7 @@ extern unsigned long __COHERENT_RAM_END__;
 /* Pointer to memory visible to both BL2 and BL3-1 for passing data */
 extern unsigned char **bl2_el_change_mem_ptr;
 
-/* Data structure which holds the extents of the trusted SRAM for BL2 */
+/* Data structure which holds the extents of the trusted RAM for BL2 */
 static meminfo bl2_tzram_layout
 __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
 		section("tzfw_coherent_mem")));
@@ -86,8 +86,8 @@ bl31_args *bl2_get_bl31_args_ptr(void)
 }
 
 /*******************************************************************************
- * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
- * in x0. This memory layout is sitting at the base of the free trusted SRAM.
+ * BL1 has passed the extents of the trusted RAM that should be visible to BL2
+ * in x0. This memory layout is sitting at the base of the free trusted RAM.
  * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
  ******************************************************************************/
 void bl2_early_platform_setup(meminfo *mem_layout,
@@ -100,13 +100,12 @@ void bl2_early_platform_setup(meminfo *mem_layout,
 	bl2_tzram_layout.free_size = mem_layout->free_size;
 	bl2_tzram_layout.attr = mem_layout->attr;
 	bl2_tzram_layout.next = 0;
-
-	return;
 }
 
 /*******************************************************************************
- * Perform platform specific setup. For now just initialize the memory location
- * to use for passing arguments to BL3-1.
+ * Perform platform specific setup, i.e. initialize the IO layer, load BL3-0
+ * image and initialise the memory location to use for passing arguments to
+ * BL3-1.
  ******************************************************************************/
 void bl2_platform_setup()
 {
diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c
index 3d2137f..eb00287 100644
--- a/plat/juno/bl31_plat_setup.c
+++ b/plat/juno/bl31_plat_setup.c
@@ -34,7 +34,7 @@
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
+ * of trusted RAM
  ******************************************************************************/
 extern unsigned long __RO_START__;
 extern unsigned long __RO_END__;
@@ -98,12 +98,10 @@ el_change_info *bl31_get_next_image_info(uint32_t type)
  * Perform any BL3-1 specific platform actions. Here is an opportunity to copy
  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
  * are lost (potentially). This needs to be done before the MMU is initialized
- * so that the memory layout can be used while creating page tables. On the FVP
- * we know that BL2 has populated the parameters in secure DRAM. So we just use
- * the reference passed in 'from_bl2' instead of copying. The 'data' parameter
- * is not used since all the information is contained in 'from_bl2'. Also, BL2
- * has flushed this information to memory, so we are guaranteed to pick up good
- * data
+ * so that the memory layout can be used while creating page tables. The 'data'
+ * parameter is not used since all the information is contained in 'from_bl2'.
+ * Also, BL2 has flushed this information to memory, so we are guaranteed to
+ * pick up good data
  ******************************************************************************/
 void bl31_early_platform_setup(bl31_args *from_bl2,
 			       void *data)
@@ -112,10 +110,9 @@ void bl31_early_platform_setup(bl31_args *from_bl2,
 }
 
 /*******************************************************************************
- * Initialize the gic, configure the CLCD and zero out variables needed by the
- * secondaries to boot up correctly.
+ * Initialize the MHU and the GIC.
  ******************************************************************************/
-void bl31_platform_setup()
+void bl31_platform_setup(void)
 {
 	unsigned int counter_base_frequency;
 	/* Initialize the gic cpu and distributor interfaces */