diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2014-02-03 14:10:17 +0000 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-03-12 16:03:33 +0000 |
| commit | 06176707bd2c56f7eb16a7d2b1c0f7bb67d5829b (patch) | |
| tree | 2d3a099d80b709d9075beb28add77e212546feaa | |
| parent | 7f6dba15fe8216cf8aad9778ef76bb242d95d92e (diff) | |
juno: BL1: default to building bypass rom
Juno has a "taped out" BL1.
To run your own BL1 on the board, you have to place it in a "ROM bypass"
address and configure the platform to boot from there.
The agreed bypass address is an offset of 0x03EC0000 from the start of
NOR flash (0x08000000), which equates to 0x0BEC0000.
To run the model using a BL1 in bypass mode, you should use a parameter
set something like this:
<path to>/FVP_CSS_Juno3 \
-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
--data css.cluster1.cpu0=bl1.bin@0x0BEC0000 \
-C soc.scc.apps_alt_boot=0x0BEC0000
To build BL1 as a ROM located at address zero, you can over-ride the
default value for TZROM_BASE by passing parameters to make, eg:
ASFLAGS="-D TZROM_BASE=0x00000000" \
CFLAGS="-D TZROM_BASE=0x00000000" \
CROSS_COMPILE=aarch64-linux-gnu- \
make PLAT=juno DEBUG=1 all
Then you can launch the model using a command such as:
<path to>/FVP_CSS_Juno3 \
-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
-C css.trustedBootROMloader.fname=<path to>/bl1.bin \
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
| -rw-r--r-- | plat/juno/platform.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/plat/juno/platform.h b/plat/juno/platform.h index e6f8a41..1b902ea 100644 --- a/plat/juno/platform.h +++ b/plat/juno/platform.h @@ -77,8 +77,6 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -#define TZROM_BASE 0x00000000 -#define TZROM_SIZE 0x00010000 #define MHU_SECURE_BASE 0x04000000 #define MHU_SECURE_SIZE 0x00001000 @@ -94,6 +92,13 @@ #define FLASH_BASE 0x08000000 #define FLASH_SIZE 0x04000000 +#define BL1_ROM_BYPASS_OFFSET 0x03EC0000 // agreed BYPASS offset from start of NOR flash + +#ifndef TZROM_BASE +#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET // Use the agreed BYPASS address +#endif +#define TZROM_SIZE 0x00010000 + #define EMMC_BASE 0x0c000000 #define EMMC_SIZE 0x04000000 |